mirror of
https://github.com/eried/portapack-mayhem.git
synced 2024-10-01 01:26:06 -04:00
116 lines
2.9 KiB
C++
116 lines
2.9 KiB
C++
/*
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* Copyright (C) 2015 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "cpld_update.hpp"
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#include "hackrf_gpio.hpp"
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#include "portapack_hal.hpp"
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#include "jtag_target_gpio.hpp"
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#include "cpld_max5.hpp"
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#include "cpld_xilinx.hpp"
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#include "portapack_cpld_data.hpp"
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#include "hackrf_cpld_data.hpp"
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bool cpld_update_if_necessary() {
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jtag::GPIOTarget target {
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portapack::gpio_cpld_tck,
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portapack::gpio_cpld_tms,
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portapack::gpio_cpld_tdi,
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portapack::gpio_cpld_tdo
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};
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jtag::JTAG jtag { target };
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cpld::max5::CPLD cpld { jtag };
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/* Unknown state */
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cpld.reset();
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cpld.run_test_idle();
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/* Run-Test/Idle */
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if( !cpld.idcode_ok() ) {
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return false;
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}
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/* Enter ISP:
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* Ensures that the I/O pins transition smoothly from user mode to ISP
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* mode. All pins are tri-stated.
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*/
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cpld.enter_isp();
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/* If silicon ID doesn't match, there's a serious problem. Leave CPLD
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* in passive state.
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*/
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if( !cpld.silicon_id_ok() ) {
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return false;
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}
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/* Verify CPLD contents against current bitstream. */
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auto ok = cpld.verify(
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portapack::cpld::block_0,
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portapack::cpld::block_1
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);
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/* CPLD verifies incorrectly. Erase and program with current bitstream. */
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if( !ok ) {
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ok = cpld.program(
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portapack::cpld::block_0,
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portapack::cpld::block_1
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);
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}
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/* If programming OK, reset CPLD to user mode. Otherwise leave it in
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* passive (ISP) state.
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*/
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if( ok ) {
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cpld.exit_isp();
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}
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return ok;
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}
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static jtag::GPIOTarget jtag_target_hackrf() {
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return {
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hackrf::one::gpio_cpld_tck,
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hackrf::one::gpio_cpld_tms,
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hackrf::one::gpio_cpld_tdi,
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hackrf::one::gpio_cpld_tdo,
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};
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}
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bool cpld_hackrf_load_sram() {
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auto jtag_target_hackrf_cpld = jtag_target_hackrf();
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cpld::xilinx::XC2C64A hackrf_cpld { jtag_target_hackrf_cpld };
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hackrf_cpld.write_sram(hackrf::one::cpld::verify_blocks);
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const auto ok = hackrf_cpld.verify_sram(hackrf::one::cpld::verify_blocks);
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return ok;
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}
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bool cpld_hackrf_verify_eeprom() {
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auto jtag_target_hackrf_cpld = jtag_target_hackrf();
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cpld::xilinx::XC2C64A hackrf_cpld { jtag_target_hackrf_cpld };
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const auto ok = hackrf_cpld.verify_eeprom(hackrf::one::cpld::verify_blocks);
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return ok;
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}
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