mirror of
https://github.com/eried/portapack-mayhem.git
synced 2024-12-16 03:04:34 -05:00
899 lines
44 KiB
C++
Executable File
899 lines
44 KiB
C++
Executable File
/*
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ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
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Copyright (C) 2014 Jared Boone, ShareBrained Technology
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Licensed under the Apache License, Version 2.0 (the "License");
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you may not use this file except in compliance with the License.
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You may obtain a copy of the License at
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http://www.apache.org/licenses/LICENSE-2.0
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Unless required by applicable law or agreed to in writing, software
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distributed under the License is distributed on an "AS IS" BASIS,
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WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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See the License for the specific language governing permissions and
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limitations under the License.
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*/
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#include "ch.h"
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#include "hal.h"
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#include <array>
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bool hackrf_r9;
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#if HAL_USE_PAL || defined(__DOXYGEN__)
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/**
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* @brief PAL setup.
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* @details Digital I/O ports static configuration as defined in @p board.h.
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* This variable is used by the HAL when initializing the PAL driver.
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*/
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/**
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* CoolRunner (HackRF) CPLD:
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* CoolRunner-II devices have internal pull-ups on TDI, TMS, and TCK.
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* It is not necessary to externally terminate JTAG pins with internal termination; they can be
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* left floating. External pull-ups on pins with internal termination is allowed, but not
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* necessary. External pull-down termination is not recommended as it would conflict with
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* the internal pull-ups
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*
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* LPC43xx pull-ups come on line when 3V3 supply voltage reaches about 2V.
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*
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* 3V3 supply:
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* Ramps up in about 1ms.
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*
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* 1V8 supply:
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* Ramps up in about 1ms.
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* EN1V8 has a 10K pull-down on the HackRF and is pulled up (very gently) by the LPC43xx
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* bootloader at boot time. So until the EN1V8 pin is reconfigured as an output, the enable
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* pin on the 1V8 supply sits at about 0.55V, which feels untidy...
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* 1V8 supply is activated when GPIO is driven high by user code.
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*/
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const PALConfig pal_default_config = {
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.P = {
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{ // GPIO0
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.data
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= (1 << 15) // P1_20: CS_XCVR
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| (1 << 14) // P2_10: AMP_BYPASS
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| (0 << 13) // P1_18: SGPIO12, HOST_Q_INVERT
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| (0 << 12) // P1_17: SGPIO11, HOST_DIRECTION
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| (1 << 11) // P1_4: SSP1_MOSI
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| (1 << 10) // P1_3: SSP1_MISO
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| (0 << 9) // P1_2: Varies by revision, float until detection
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| (0 << 8) // P1_1: Varies by revision, float until detection
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| (0 << 7) // P2_7: Varies by revision, float until detection
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| (0 << 6) // P3_6: SPIFI_MISO
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| (1 << 5) // P6_6: SGPIO5, HOST_DATA5
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| (1 << 4) // P1_0: SGPIO7, HOST_DATA7
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| (1 << 3) // P1_16: SGPIO3, HOST_DATA3
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| (1 << 2) // P1_15: SGPIO2, HOST_DATA2
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| (1 << 1) // P0_1: SGPIO1, HOST_DATA1
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| (1 << 0) // P0_0: SGPIO0, HOST_DATA0
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,
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.dir
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= (1 << 15) // P1_20: CS_XCVR
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| (1 << 14) // P2_10: AMP_BYPASS
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| (1 << 13) // P1_18: SGPIO12, HOST_Q_INVERT
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| (0 << 12) // P1_17: SGPIO11, HOST_DIRECTION
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| (0 << 11) // P1_4: SSP1_MOSI
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| (0 << 10) // P1_3: SSP1_MISO
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| (0 << 9) // P1_2: Varies by revision, float until detection
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| (0 << 8) // P1_1: Varies by revision, float until detection
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| (0 << 7) // P2_7: Varies by revision, float until detection
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| (0 << 6) // P3_6: SPIFI_MISO
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| (0 << 5) // P6_6: SGPIO5, HOST_DATA5
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| (0 << 4) // P1_0: SGPIO7, HOST_DATA7
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| (0 << 3) // P1_16: SGPIO3, HOST_DATA3
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| (0 << 2) // P1_15: SGPIO2, HOST_DATA2
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| (0 << 1) // P0_1: SGPIO1, HOST_DATA1
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| (0 << 0) // P0_0: SGPIO0, HOST_DATA0
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},
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{ // GPIO1
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.data
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= (1 << 15) // P3_5: SPIFI_SIO2
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| (1 << 14) // P3_4: SPIFI_SIO3
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| (1 << 13) // P2_13: PortaPack DIR
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| (1 << 12) // P2_12: !RX_AMP_PWR
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| (0 << 11) // P2_11: RX_AMP
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| (0 << 10) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
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| (1 << 9) // P1_6: SD_CMD
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| (1 << 8) // P1_5: SD_POW, PortaPack CPLD.TDO(O) (input with pull up)
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| (1 << 7) // P1_14: SGPIO10, HOST_DISABLE
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| (1 << 6) // P1_13: SD_CD
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| (1 << 5) // P1_12: SD_DAT3
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| (1 << 4) // P1_11: SD_DAT2
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| (1 << 3) // P1_10: SD_DAT1
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| (1 << 2) // P1_9: SD_DAT0
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| (1 << 1) // P1_8: PortaPack CPLD.TMS(I)
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| (0 << 0) // P1_7: !MIX_BYPASS
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,
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.dir
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= (0 << 15) // P3_5: SPIFI_SIO2
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| (0 << 14) // P3_4: SPIFI_SIO3
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| (0 << 13) // P2_13: PortaPack DIR
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| (1 << 12) // P2_12: !RX_AMP_PWR
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| (1 << 11) // P2_11: RX_AMP
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| (0 << 10) // P2_9: 10K PD, BOOT3, PortaPack LCD_WRX
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| (0 << 9) // P1_6: SD_CMD
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| (0 << 8) // P1_5: SD_POW, PortaPack CPLD.TDO(O) (input with pull up)
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| (0 << 7) // P1_14: SGPIO10, HOST_DISABLE
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| (0 << 6) // P1_13: SD_CD
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| (0 << 5) // P1_12: SD_DAT3
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| (0 << 4) // P1_11: SD_DAT2
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| (0 << 3) // P1_10: SD_DAT1
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| (0 << 2) // P1_9: SD_DAT0
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| (0 << 1) // P1_8: PortaPack CPLD.TMS(I) (output only when needed, pull up internal to CPLD)
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| (1 << 0) // P1_7: !MIX_BYPASS
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},
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{ // GPIO2
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.data
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= (0 << 15) // P5_6: TX_AMP
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| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| (1 << 12) // P5_3: RX_MIX_BP
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| (0 << 11) // P5_2: TX_MIX_BP
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| (0 << 10) // P5_1: LP
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| (0 << 9) // P5_0: Varies by revision, float until detection
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| (0 << 8) // P6_12: LED3 (TX)
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| (1 << 7) // P5_7: CS_AD
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| (0 << 6) // P4_6: XCVR_EN, 10K PD
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| (0 << 5) // P4_5: RXENABLE
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| (0 << 4) // P4_4: Varies by revision, float until detection
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| (1 << 3) // P4_3: SGPIO9, HOST_CAPTURE
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| (0 << 2) // P4_2: LED2 (RX)
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| (0 << 1) // P4_1: LED1 (USB)
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| (1 << 0) // P4_0: HP
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,
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.dir
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= (1 << 15) // P5_6: TX_AMP
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| (1 << 14) // P5_5: MIXER_RESETX, 10K PU
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| (1 << 13) // P5_4: MIXER_ENX, 10K PU
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| (1 << 12) // P5_3: RX_MIX_BP
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| (1 << 11) // P5_2: TX_MIX_BP
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| (1 << 10) // P5_1: LP
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| (0 << 9) // P5_0: Varies by revision, float until detection
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| (1 << 8) // P6_12: LED3 (TX)
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| (1 << 7) // P5_7: CS_AD
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| (1 << 6) // P4_6: XCVR_EN, 10K PD
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| (1 << 5) // P4_5: RXENABLE
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| (0 << 4) // P4_4: Varies by revision, float until detection
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| (0 << 3) // P4_3: SGPIO9, HOST_CAPTURE
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| (1 << 2) // P4_2: LED2 (RX)
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| (1 << 1) // P4_1: LED1 (USB)
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| (1 << 0) // P4_0: HP
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},
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{ // GPIO3
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.data
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= (1 << 15) // P7_7: PortaPack GPIO3_15(IO)
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| (1 << 14) // P7_6: PortaPack GPIO3_14(IO)
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| (1 << 13) // P7_5: PortaPack GPIO3_13(IO)
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| (1 << 12) // P7_4: PortaPack GPIO3_12(IO)
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| (1 << 11) // P7_3: PortaPack GPIO3_11(IO)
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| (1 << 10) // P7_2: PortaPack GPIO3_10(IO)
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| (1 << 9) // P7_1: PortaPack GPIO3_9(IO)
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| (1 << 8) // P7_0: PortaPack GPIO3_8(IO)
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| (1 << 7) // P6_11: VREGMODE
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| (0 << 6) // P6_10: Varies by revision, float until detection
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| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
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| (1 << 4) // P6_5: HackRF CPLD.TMS(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
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| (1 << 3) // P6_4: MIXER_SDATA
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| (1 << 2) // P6_3: SGPIO4, HOST_DATA4
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| (1 << 1) // P6_2: HackRF CPLD.TDI(I), PortaPack I2S0_RX_SDA(O), PortaPack CPLD.TDI(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
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| (1 << 0) // P6_1: HackRF CPLD.TCK(I), PortaPack CPLD.TCK(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
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,
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.dir
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= (0 << 15) // P7_7: PortaPack GPIO3_15(IO)
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| (0 << 14) // P7_6: PortaPack GPIO3_14(IO)
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| (0 << 13) // P7_5: PortaPack GPIO3_13(IO)
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| (0 << 12) // P7_4: PortaPack GPIO3_12(IO)
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| (0 << 11) // P7_3: PortaPack GPIO3_11(IO)
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| (0 << 10) // P7_2: PortaPack GPIO3_10(IO)
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| (0 << 9) // P7_1: PortaPack GPIO3_9(IO)
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| (0 << 8) // P7_0: PortaPack GPIO3_8(IO)
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| (1 << 7) // P6_11: VREGMODE
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| (0 << 6) // P6_10: Varies by revision, float until detection
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| (1 << 5) // P6_9: !TX_AMP_PWR, 10K PU
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| (0 << 4) // P6_5: HackRF CPLD.TMS(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
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| (0 << 3) // P6_4: MIXER_SDATA
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| (0 << 2) // P6_3: SGPIO4, HOST_DATA4
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| (0 << 1) // P6_2: HackRF CPLD.TDI(I), PortaPack I2S0_RX_SDA(O), PortaPack CPLD.TDI(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
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| (0 << 0) // P6_1: HackRF CPLD.TCK(I), PortaPack CPLD.TCK(I) (output only when needed, pull-up internal to CPLD when 1V8 present)
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},
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{ // GPIO4
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.data
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= (1 << 11) // P9_6: SGPIO8, SGPIO_CLK
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,
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.dir
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= (0 << 11) // P9_6: SGPIO8, SGPIO_CLK
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},
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{ // GPIO5
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.data
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= (1 << 18) // P9:5: HackRF CPLD.TDO(O) (input with pull up)
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| (1 << 16) // P6_8: MIX_BYPASS
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| (0 << 15) // P6_7: Varies by revision, float until detection
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| (1 << 14) // P4_10: SGPIO15, CPLD (unused)
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| (1 << 13) // P4_9: SGPIO14, CPLD (unused)
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| (0 << 12) // P4_8: Varies by revision, float until detection
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| (1 << 11) // P3_8: SPIFI_CS
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| (1 << 10) // P3_7: SPIFI_MOSI
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| (1 << 9) // P3_2: I2S0_RX_SDA
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| (1 << 8) // P3_1: I2S0_RX_WS
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| (0 << 7) // P2_8: BOOT2
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| (0 << 6) // P2_6: MIXER_SCLK
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| (0 << 5) // P2_5: Varies by revision, float until detection
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| (1 << 4) // P2_4: PortaPack LCD_RDX
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| (0 << 3) // P2_3: PortaPack LCD_TE
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| (1 << 2) // P2_2: SGPIO6, HOST_DATA6
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| (0 << 1) // P2_1: PortaPack ADDR
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| (1 << 0) // P2_0: PortaPack IO_STBX
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,
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.dir
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= (0 << 18) // P9_5: HackRF CPLD.TDO(O) (input with pull up)
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| (1 << 16) // P6_8: MIX_BYPASS
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| (0 << 15) // P6_7: Varies by revision, float until detection
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| (0 << 14) // P4_10: SGPIO15, CPLD (unused)
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| (0 << 13) // P4_9: SGPIO14, CPLD (unused)
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| (0 << 12) // P4_8: Varies by revision, float until detection
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| (0 << 11) // P3_8: SPIFI_CS
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| (0 << 10) // P3_7: SPIFI_MOSI
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| (0 << 9) // P3_2: I2S0_RX_SDA
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| (0 << 8) // P3_1: I2S0_RX_WS
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| (0 << 7) // P2_8: BOOT2
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| (0 << 6) // P2_6: MIXER_SCLK
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| (0 << 5) // P2_5: Varies by revision, float until detection
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| (0 << 4) // P2_4: PortaPack LCD_RDX
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| (0 << 3) // P2_3: PortaPack LCD_TE
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| (0 << 2) // P2_2: SGPIO6, HOST_DATA6
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| (0 << 1) // P2_1: PortaPack ADDR
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| (0 << 0) // P2_0: PortaPack IO_STBX
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},
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{ // GPIO6
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.data = 0,
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.dir = 0
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},
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{ // GPIO7
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.data = 0,
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.dir = 0
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},
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},
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.SCU = {
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/* Configure GP_CLKIN as soon as possible. It's an output at boot time, and the Si5351C doesn't
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* reset when the reset button is pressed, so it could still be output enabled.
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*/
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{ 4, 7, scu_config_normal_drive_t { .mode=1, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* GP_CLKIN/P72/MCU_CLK: SI5351C.CLK7(O) */
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/* HackRF: LEDs. Configured early so we can use them to indicate boot status. */
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{ 4, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* LED1: LED1.A(I) */
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{ 4, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* LED2: LED2.A(I) */
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{ 6, 12, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* LED3: LED3.A(I) */
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/* Power control */
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{ 6, 11, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* VREGMODE/P69: TPS62410.MODE/DATA(I) */
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/* HackRF: I2C0 */
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/* Glitch filter operates at 3ns instead of 50ns due to the WM8731
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* returning an ACK very fast (170ns) and confusing the I2C state
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* machine into thinking there was a bus error. It looks like the
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* MCU sees SDA fall before SCL falls, indicating a START at the
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* point an ACK is expected. With the glitch filter off or set to
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* 3ns, it's probably still a bit tight timing-wise, but improves
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* reliability on some problem units.
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*/
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{ 25, 1,
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scu_config_sfsi2c0_t {
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.scl_efp=1, // SCL: 3ns glitch
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.scl_ehd=0, // SCL: Standard/Fast mode
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.scl_ezi=1, // SCL: Input enabled
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.scl_zif=0, // SCL: Enable input glitch filter
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.sda_efp=1, // SDA: 3ns glitch
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.sda_ehd=0, // SDA: Standard/Fast mode
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.sda_ezi=1, // SDA: Input enabled
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.sda_zif=0 // SDA: Enable input glitch filter
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}
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},
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/* Radio section control */
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{ 1, 3, scu_config_normal_drive_t { .mode=5, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* SSP1_MISO/P41: MAX2837.DOUT(O) */
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{ 1, 4, scu_config_normal_drive_t { .mode=5, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* SSP1_MOSI/P40: MAX2837.DIN(I), MAX5864.DIN(I) */
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{ 1, 7, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* !MIX_BYPASS/P35: U1.VCTL1(I), U11.VCTL2(I), U9.V2(I) */
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{ 1, 19, scu_config_normal_drive_t { .mode=1, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* SSP1_SCK/P39: MAX2837.SCLK(I), MAX5864.SCLK(I) */
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{ 1, 20, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CS_XCVR/P53: MAX2837.CS(I) */
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{ 2, 6, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* MIXER_SCLK/P31: 33pF, RFFC5072.SCLK(I) */
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{ 2, 10, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* AMP_BYPASS/P50: U14.V2(I), U12.V2(I) */
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{ 2, 11, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* RX_AMP/P49: U12.V1(I), U14.V3(I) */
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{ 2, 12, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* !RX_AMP_PWR/P52: 10K PU, Q1.G(I), power to U13 (RX amp) */
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{ 4, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* HP/P44: U6.VCTL1(I), U5.VCTL2(I) */
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{ 4, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* RXENABLE/P56: MAX2837.RXENABLE(I) */
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{ 4, 6, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* XCVR_EN: 10K PD, MAX2837.ENABLE(I) */
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{ 5, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* LP/P45: U6.VCTL2(I), U5.VCTL1(I) */
|
|
{ 5, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* TX_MIX_BP/P46: U9.V1(I) */
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|
{ 5, 3, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* RX_MIX_BP/P47: U9.V3(I) */
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|
{ 5, 4, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* MIXER_ENX/P32: 10K PU, 33pF, RFFC5072.ENX(I) */
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|
{ 5, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* MIXER_RESETX/P33: 10K PU, 33pF, RFFC5072.RESETX(I) */
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|
{ 5, 6, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* TX_AMP/P48: U12.V3(I), U14.V1(I) */
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|
{ 5, 7, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CS_AD/P54: MAX5864.CS(I) */
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|
{ 6, 4, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* MIXER_SDATA/P27: 33pF, RFFC5072.SDATA(IO) */
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|
{ 6, 8, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* MIX_BYPASS/P34: U1.VCTL2(I), U11.VCTL1(I) */
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|
{ 6, 9, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* !TX_AMP_PWR/P51: 10K PU, Q2.G(I), power to U25 (TX amp) */
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|
|
|
/* SGPIO for sample transfer interface to HackRF CPLD. */
|
|
{ 0, 0, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO0/P75/BANK2F3M3: CPLD.89/HOST_DATA0(IO) */
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|
{ 0, 1, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO1/BANK2F3M5: CPLD.79/HOST_DATA1(IO) */
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|
{ 1, 15, scu_config_normal_drive_t { .mode=2, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO2/BANK2F3M9: CPLD.74/HOST_DATA2(IO) */
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|
{ 1, 16, scu_config_normal_drive_t { .mode=2, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO3/BANK2F3M10: CPLD.72/HOST_DATA3(IO) */
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|
{ 6, 3, scu_config_normal_drive_t { .mode=2, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO4/BANK2F3M14: CPLD.67/HOST_DATA4(IO) */
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|
{ 6, 6, scu_config_normal_drive_t { .mode=2, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO5/BANK2F3M15: CPLD.64/HOST_DATA5(IO) */
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|
{ 2, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO6/BANK2F3M16: CPLD.61/HOST_DATA6(IO) */
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|
{ 1, 0, scu_config_normal_drive_t { .mode=6, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SGPIO7/P76/BANK2F3M7: CPLD.77/HOST_DATA7(IO) */
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|
{ 9, 6, scu_config_normal_drive_t { .mode=6, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* SGPIO8/SGPIO_CLK/P60: SI5351C.CLK2(O) */
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|
{ 4, 3, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=1 } }, /* SGPIO9/P77/BANK2F3M1: CPLD.91/HOST_CAPTURE(O) */
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|
{ 1, 14, scu_config_normal_drive_t { .mode=6, .epd=0, .epun=0, .ehs=1, .ezi=0, .zif=0 } }, /* SGPIO10/P78/BANK2F3M8: CPLD.76/HOST_DISABLE(I) */
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|
{ 1, 17, scu_config_normal_drive_t { .mode=6, .epd=1, .epun=1, .ehs=1, .ezi=0, .zif=0 } }, /* SGPIO11/P79/BANK2F3M11: CPLD.71/HOST_DIRECTION(I) */
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|
{ 1, 18, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* SGPIO12/BANK2F3M12: CPLD.70/HOST_INVERT(I) */
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|
{ 4, 9, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* SGPIO14/BANK2F3M4: CPLD.81/CPLD_P81 */
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|
{ 4, 10, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* SGPIO15/BANK2F3M6: CPLD.78/CPLD_P78 */
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|
|
|
/* HackRF: CPLD */
|
|
{ 6, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CPLD_TCK: CPLD.TCK(I), PortaPack CPLD.TCK(I) */
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|
{ 6, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* CPLD_TDI: CPLD.TDI(I), PortaPack I2S0_RX_SDA(O), PortaPack CPLD.TDI(I) */
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|
{ 6, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CPLD_TMS: CPLD.TMS(I) */
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|
{ 9, 5, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* CPLD_TDO: CPLD.TDO(O) */
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|
|
|
/* PortaPack CPLD */
|
|
{ 1, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* SD_POW: PortaPack CPLD.TDO(O) */
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|
{ 1, 8, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* SD_VOLT0: PortaPack CPLD.TMS(I) */
|
|
|
|
/* Miscellaneous */
|
|
{ 6, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* I2S0_RX_MCLK: Unused */
|
|
{ 15, 4, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* I2S0_RX_SCK: Unused */
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|
|
|
/* Usage of these pins varies by revision, float until detection */
|
|
{ 1, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 1, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 2, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 2, 7, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 4, 4, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 4, 8, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 5, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 6, 7, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
{ 6, 10, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } },
|
|
}
|
|
};
|
|
|
|
/* Additional GPIO configuration for HackRF OG */
|
|
static const std::array<gpio_setup_t, 6> gpio_setup_og { {
|
|
{ // GPIO0
|
|
.data
|
|
= (0 << 9) // P1_2: 10K PD, BOOT1
|
|
| (1 << 8) // P1_1: 10K PU, BOOT0
|
|
| (1 << 7) // P2_7: 10K PU, ISP
|
|
,
|
|
.dir
|
|
= (0 << 9) // P1_2: 10K PD, BOOT1
|
|
| (0 << 8) // P1_1: 10K PU, BOOT0
|
|
| (0 << 7) // P2_7: 10K PU, ISP
|
|
},
|
|
{ // GPIO1
|
|
.data = 0,
|
|
.dir = 0
|
|
},
|
|
{ // GPIO2
|
|
.data
|
|
= (1 << 9) // P5_0: !VAA_ENABLE
|
|
| (0 << 4) // P4_4: TXENABLE
|
|
,
|
|
.dir
|
|
= (1 << 9) // P5_0: !VAA_ENABLE
|
|
| (1 << 4) // P4_4: TXENABLE
|
|
},
|
|
{ // GPIO3
|
|
.data
|
|
= (0 << 6) // P6_10: EN1V8, 10K PD
|
|
,
|
|
.dir
|
|
= (1 << 6) // P6_10: EN1V8, 10K PD
|
|
},
|
|
{ // GPIO4
|
|
.data = 0,
|
|
.dir = 0
|
|
},
|
|
{ // GPIO5
|
|
.data
|
|
= (0 << 15) // P6_7: TX
|
|
| (0 << 12) // P4_8: SGPIO13, HOST_SYNC_EN
|
|
| (1 << 5) // P2_5: RX
|
|
,
|
|
.dir
|
|
= (1 << 15) // P6_7: TX
|
|
| (0 << 12) // P4_8: SGPIO13, HOST_SYNC_EN
|
|
| (1 << 5) // P2_5: RX
|
|
},
|
|
} };
|
|
|
|
/* Additional GPIO configuration for HackRF r9 */
|
|
static const std::array<gpio_setup_t, 6> gpio_setup_r9 { {
|
|
{ // GPIO0
|
|
.data
|
|
= (0 << 9) // P1_2: 10K PD, BOOT1, CLKOUT_EN
|
|
| (1 << 8) // P1_1: 10K PU, BOOT0, MCU_CLK_EN
|
|
| (1 << 7) // P2_7: 10K PU, ISP, RX
|
|
,
|
|
.dir
|
|
= (0 << 9) // P1_2: 10K PD, BOOT1, CLKOUT_EN
|
|
| (0 << 8) // P1_1: 10K PU, BOOT0, MCU_CLK_EN
|
|
| (0 << 7) // P2_7: 10K PU, ISP, RX
|
|
},
|
|
{ // GPIO1
|
|
.data = 0,
|
|
.dir = 0
|
|
},
|
|
{ // GPIO2
|
|
.data
|
|
= (1 << 9) // P5_0: EN1V8, 10K PD
|
|
| (1 << 4) // P4_4: !ANT_BIAS
|
|
,
|
|
.dir
|
|
= (1 << 9) // P5_0: EN1V8, 10K PD
|
|
| (1 << 4) // P4_4: !ANT_BIAS
|
|
},
|
|
{ // GPIO3
|
|
.data
|
|
= (1 << 6) // P6_10: !VAA_ENABLE
|
|
,
|
|
.dir
|
|
= (1 << 6) // P6_10: !VAA_ENABLE
|
|
},
|
|
{ // GPIO4
|
|
.data = 0,
|
|
.dir = 0
|
|
},
|
|
{ // GPIO5
|
|
.data
|
|
= (0 << 15) // P6_7: CLKIN_EN
|
|
| (0 << 12) // P4_8: CLKIN_DETECT
|
|
| (0 << 5) // P2_5: HOST_SYNC_EN
|
|
,
|
|
.dir
|
|
= (1 << 15) // P6_7: CLKIN_EN
|
|
| (0 << 12) // P4_8: CLKIN_DETECT
|
|
| (0 << 5) // P2_5: HOST_SYNC_EN
|
|
},
|
|
} };
|
|
|
|
/* Additional SCU configuration for HackRF OG */
|
|
static const std::array<scu_setup_t, 9> pins_setup_og { {
|
|
/* Power control */
|
|
{ 5, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
|
|
{ 6, 10, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* EN1V8/P70: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
|
|
|
|
/* Radio section control */
|
|
{ 2, 5, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* RX/P43: U7.VCTL1(I), U10.VCTL1(I), U2.VCTL1(I) */
|
|
{ 4, 4, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* TXENABLE/P55: MAX2837.TXENABLE(I) */
|
|
{ 6, 7, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* TX/P42: U7.VCTL2(I), U10.VCTL2(I), U2.VCTL2(I) */
|
|
|
|
/* SGPIO for sample transfer interface to HackRF CPLD. */
|
|
{ 4, 8, scu_config_normal_drive_t { .mode=4, .epd=1, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* SGPIO13/BANK2F3M2: CPLD.90/HOST_SYNC_EN(I) */
|
|
|
|
/* Miscellaneous */
|
|
{ 1, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* P1_1/P74: 10K PU, BOOT0 */
|
|
{ 1, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* P1_2/P73: 10K PD, BOOT1 */
|
|
{ 2, 7, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* ISP: 10K PU, Unused */
|
|
} };
|
|
|
|
/* Additional SCU configuration for HackRF r9 */
|
|
static const std::array<scu_setup_t, 9> pins_setup_r9 { {
|
|
/* Power control */
|
|
{ 6, 10, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* !VAA_ENABLE: 10K PU, Q3.G(I), power to VAA */
|
|
{ 5, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* EN1V8: 10K PD, TPS62410.EN2(I), 1V8LED.A(I) */
|
|
|
|
/* Radio section control */
|
|
{ 2, 7, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* RX/ISP/P96: U7.VCTL(I), U10.VCTL(I), U2.VCTL(I) */
|
|
{ 4, 4, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* !ANT_BIAS: 10K PU, Q4.G(I) */
|
|
|
|
/* SGPIO for sample transfer interface to HackRF CPLD. */
|
|
{ 2, 5, scu_config_normal_drive_t { .mode=4, .epd=1, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* BANK2F3M2: CPLD.90/HOST_SYNC_EN(I) */
|
|
|
|
/* Clock control */
|
|
{ 1, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* MCU_CLK_EN/BOOT0: 10K PU, U28.1A(I) */
|
|
{ 1, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CLKOUT_EN/BOOT1: 10K PD, U28.2A(I) */
|
|
{ 6, 7, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CLKIN_EN: U16.SEL(I), U26.1A(I) */
|
|
|
|
/* Miscellaneous */
|
|
{ 4, 8, scu_config_normal_drive_t { .mode=1, .epd=1, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* CLKIN_DETECT: U26.2Y(O) */
|
|
} };
|
|
|
|
#endif
|
|
|
|
static const std::array<scu_setup_t, 26> pins_setup_portapack { {
|
|
{ 2, 0, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* U0_TXD: PortaPack P2_0/IO_STBX */
|
|
{ 2, 1, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* U0_RXD: PortaPack P2_1/ADDR */
|
|
{ 2, 3, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* I2C1_SDA: PortaPack P2_3/LCD_TE */
|
|
{ 2, 4, scu_config_normal_drive_t { .mode=4, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* I2C1_SCL: PortaPack P2_4/LCD_RDX */
|
|
{ 2, 8, scu_config_normal_drive_t { .mode=1, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* P2_8: 10K PD, BOOT2, DFU switch, PortaPack P2_8/<unused> */
|
|
{ 2, 9, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* P2_9: 10K PD, BOOT3, PortaPack P2_9/LCD_WRX */
|
|
{ 2, 13, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* P2_13: PortaPack P2_13/DIR */
|
|
{ 7, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_8: PortaPack GPIO3_8(IO) */
|
|
{ 7, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_9: PortaPack GPIO3_9(IO) */
|
|
{ 7, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_10: PortaPack GPIO3_10(IO) */
|
|
{ 7, 3, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_11: PortaPack GPIO3_11(IO) */
|
|
{ 7, 4, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_12: PortaPack GPIO3_12(IO) */
|
|
{ 7, 5, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_13: PortaPack GPIO3_13(IO) */
|
|
{ 7, 6, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_14: PortaPack GPIO3_14(IO) */
|
|
{ 7, 7, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } }, /* GPIO3_15: PortaPack GPIO3_15(IO) */
|
|
|
|
/* PortaPack: Audio */
|
|
{ 3, 0, scu_config_normal_drive_t { .mode=2, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* I2S0_TX_SCK: PortaPack I2S0_TX_SCK(I) */
|
|
{ 3, 1, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* I2S0_RX_WS: PortaPack I2S0_TX_WS(I). Input enabled to fold back into RX. */
|
|
{ 3, 2, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=0, .ehs=0, .ezi=0, .zif=0 } }, /* I2S0_RX_SDA: PortaPack I2S0_TX_SDA(I) */
|
|
{ 24, 2, scu_config_normal_drive_t { .mode=6, .epd=1, .epun=1, .ehs=0, .ezi=0, .zif=0 } }, /* I2S0_TX_CLK: PortaPack I2S0_TX_MCLK */
|
|
|
|
/* PortaPack: SD card socket */
|
|
{ 24, 0, scu_config_normal_drive_t { .mode=4, .epd=1, .epun=1, .ehs=0, .ezi=1, .zif=1 } }, /* SD_CLK: PortaPack SD.CLK, enable input buffer for timing feedback? */
|
|
{ 1, 6, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* SD_CMD: PortaPack SD.CMD(IO) */
|
|
{ 1, 9, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* SD_DAT0: PortaPack SD.DAT0(IO) */
|
|
{ 1, 10, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* SD_DAT1: PortaPack SD.DAT1(IO) */
|
|
{ 1, 11, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* SD_DAT2: PortaPack SD.DAT2(IO) */
|
|
{ 1, 12, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=1 } }, /* SD_DAT3: PortaPack SD.DAT3(IO) */
|
|
{ 1, 13, scu_config_normal_drive_t { .mode=7, .epd=0, .epun=0, .ehs=0, .ezi=1, .zif=0 } }, /* SD_CD: PortaPack SD.CD(O) */
|
|
} };
|
|
|
|
static const std::array<scu_setup_t, 6> pins_setup_spifi { {
|
|
{ 3, 3, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SPIFI_SCK: W25Q80BV.CLK(I), enable input buffer for timing feedback */
|
|
{ 3, 4, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SPIFI_SIO3/P82: W25Q80BV.HOLD(IO) */
|
|
{ 3, 5, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SPIFI_SIO2/P81: W25Q80BV.WP(IO) */
|
|
{ 3, 6, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SPIFI_MISO: W25Q80BV.DO(IO) */
|
|
{ 3, 7, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SPIFI_MOSI: W25Q80BV.DI(IO) */
|
|
{ 3, 8, scu_config_normal_drive_t { .mode=3, .epd=0, .epun=1, .ehs=1, .ezi=1, .zif=1 } }, /* SPIFI_CS/P68: W25Q80BV.CS(I) */
|
|
} };
|
|
|
|
template<size_t N>
|
|
void setup_gpios(const std::array<gpio_setup_t, N>& pins_setup) {
|
|
for (size_t i = 0; i < N; i++) {
|
|
LPC_GPIO->PIN[i] |= pins_setup[i].data;
|
|
LPC_GPIO->DIR[i] |= pins_setup[i].dir;
|
|
}
|
|
}
|
|
|
|
static void setup_pin(const scu_setup_t& pin_setup) {
|
|
LPC_SCU->SFSP[pin_setup.port][pin_setup.pin] = pin_setup.config;
|
|
}
|
|
|
|
template<size_t N>
|
|
void setup_pins(const std::array<scu_setup_t, N>& pins_setup) {
|
|
for(const auto& pin_setup : pins_setup) {
|
|
setup_pin(pin_setup);
|
|
}
|
|
}
|
|
|
|
/*
|
|
* HackRF One r9 has a pull-up on GPIO3_6 (P6_10) and a pull-down on GPIO2_9 (P5_0).
|
|
* HackRF One OG has a pull-down on GPIO3_6 (P6_10) and a pull-up on GPIO2_9 (P5_0).
|
|
*/
|
|
static const scu_setup_t pin_setup_detect { 5, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=1, .zif=0 } };
|
|
|
|
/* Check resistor on GPIO2_9 (P5_0) to detect HackRF hardware revision. */
|
|
extern "C" bool detect_hackrf_r9() {
|
|
setup_pin(pin_setup_detect);
|
|
LPC_GPIO->DIR[2] &= ~(1 << 9);
|
|
return LPC_GPIO->W2[9] == 0;
|
|
}
|
|
|
|
static void configure_spifi(void) {
|
|
setup_pins(pins_setup_spifi);
|
|
|
|
/* Tweak SPIFI mode */
|
|
LPC_SPIFI->CTRL =
|
|
(0xffff << 0) /* Timeout */
|
|
| (0x1 << 16) /* CS high time in "clocks - 1" */
|
|
| (0 << 21) /* 0: Attempt speculative prefetch on data accesses */
|
|
| (0 << 22) /* 0: No interrupt on command ended */
|
|
| (0 << 23) /* 0: SCK driven low after rising edge at which last bit of command is captured. Stays low while CS# is high. */
|
|
| (0 << 27) /* 0: Cache prefetching enabled */
|
|
| (0 << 28) /* 0: Quad protocol, IO3:0 */
|
|
| (1 << 29) /* 1: Read data sampled on falling edge of clock */
|
|
| (1 << 30) /* 1: Read data is sampled using feedback clock from SCK pin */
|
|
| (0 << 31) /* 0: DMA request disabled */
|
|
;
|
|
|
|
/* Throttle up the SPIFI interface to 96MHz (IDIVA=PLL1 / 3) */
|
|
LPC_CGU->IDIVB_CTRL.word =
|
|
( 0 << 0) /* PD */
|
|
| ( 2 << 2) /* IDIV (/3) */
|
|
| ( 1 << 11) /* AUTOBLOCK */
|
|
| ( 9 << 24) /* PLL1 */
|
|
;
|
|
}
|
|
|
|
void configure_pins_portapack(void) {
|
|
LPC_GPIO->DIR[1] |= (1 << 13) | (1 << 10);
|
|
LPC_GPIO->DIR[3] |= (0xff << 8);
|
|
LPC_GPIO->DIR[5] |= (1 << 4) | (1 << 1) | (1 << 0);
|
|
setup_pins(pins_setup_portapack);
|
|
}
|
|
|
|
static const motocon_pwm_resources_t motocon_pwm_resources = {
|
|
.base = { .clk = &LPC_CGU->BASE_APB1_CLK, .stat = &LPC_CCU1->BASE_STAT, .stat_mask = (1 << 1) },
|
|
.branch = { .cfg = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_CFG, .stat = &LPC_CCU1->CLK_APB1_MOTOCON_PWM_STAT },
|
|
.reset = { .output_index = 38 },
|
|
};
|
|
|
|
static const scu_setup_t pin_setup_vaa_enablex_pwm = { 5, 0, scu_config_normal_drive_t { .mode=1, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } };
|
|
static const scu_setup_t pin_setup_vaa_enablex_gpio_og = { 5, 0, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } };
|
|
static const scu_setup_t pin_setup_vaa_enablex_gpio_r9 = { 6, 10, scu_config_normal_drive_t { .mode=0, .epd=0, .epun=1, .ehs=0, .ezi=0, .zif=0 } };
|
|
|
|
/* VAA powers:
|
|
* MAX5864 analog section.
|
|
* MAX2837 registers and other functions.
|
|
* RFFC5072 analog section.
|
|
*
|
|
* Beware that power applied to pins of the MAX2837 may
|
|
* show up on VAA and start powering other components on the
|
|
* VAA net. So turn on VAA before driving pins from MCU to
|
|
* MAX2837.
|
|
*/
|
|
void vaa_power_on(void) {
|
|
/* Very twitchy process for powering up VAA without glitching the 3.3V rail, which can send the
|
|
* microcontroller into reset.
|
|
*
|
|
* Controlling timing while running from SPIFI flash is tricky, hence use of a PWM peripheral...
|
|
*/
|
|
if (hackrf_r9) {
|
|
/*
|
|
* There is enough VCC->VAA leakage prior to VAA activation from IO pins on
|
|
* HackRF One r9 that slowing down activation like this isn't necessary, but
|
|
* we do it just in case a different start-up sequence in the future results
|
|
* in less leakage.
|
|
*/
|
|
setup_pin(pin_setup_vaa_enablex_gpio_r9); // P6_10 GPIO3[ 6]: !VAA_ENABLE, 10K PU
|
|
for (uint32_t i = 0; i < 1000; i++) {
|
|
LPC_GPIO->W3[6] = 1;
|
|
LPC_GPIO->W3[6] = 0;
|
|
}
|
|
} else {
|
|
/* Configure and enable MOTOCONPWM peripheral clocks.
|
|
* Assume IDIVC is running the post-bootloader configuration, outputting 96MHz derived from PLL1.
|
|
*/
|
|
base_clock_enable(&motocon_pwm_resources.base);
|
|
branch_clock_enable(&motocon_pwm_resources.branch);
|
|
peripheral_reset(&motocon_pwm_resources.reset);
|
|
|
|
/* Combination of pulse duration and duty cycle was arrived at empirically, to keep supply glitching
|
|
* to +/- 0.15V.
|
|
*/
|
|
const uint32_t cycle_period = 256;
|
|
uint32_t enable_period = 2;
|
|
LPC_MCPWM->TC2 = 0;
|
|
LPC_MCPWM->MAT2 = cycle_period - enable_period;
|
|
LPC_MCPWM->LIM2 = cycle_period;
|
|
|
|
/* Switch !VAA_ENABLE pin from GPIO to MOTOCONPWM peripheral output, now that the peripheral is configured. */
|
|
setup_pin(pin_setup_vaa_enablex_pwm); // P5_0 /GPIO2[ 9]/MCOB2: !VAA_ENABLE, 10K PU
|
|
|
|
/* Start the PWM operation. */
|
|
LPC_MCPWM->CON_SET = (1 << 16);
|
|
|
|
/* Wait until VAA rises to approximately 90% of final voltage. */
|
|
/* Timing assumes we're running immediately after the bootloader: 96 MHz from IRC+PLL1
|
|
*/
|
|
while(enable_period < cycle_period) {
|
|
{ volatile uint32_t delay = 2000; while(delay--); }
|
|
enable_period <<= 1;
|
|
LPC_MCPWM->MAT2 = cycle_period - enable_period;
|
|
}
|
|
|
|
/* Hold !VAA_ENABLE active using a GPIO, so we can reclaim and shut down the MOTOCONPWM peripheral. */
|
|
LPC_GPIO->CLR[2] = (1 << 9); // !VAA_ENABLE
|
|
LPC_GPIO->DIR[2] |= (1 << 9);
|
|
setup_pin(pin_setup_vaa_enablex_gpio_og); // P5_0 /GPIO2[ 9]/MCOB2: !VAA_ENABLE, 10K PU
|
|
|
|
peripheral_reset(&motocon_pwm_resources.reset);
|
|
branch_clock_disable(&motocon_pwm_resources.branch);
|
|
base_clock_disable(&motocon_pwm_resources.base);
|
|
}
|
|
}
|
|
|
|
void vaa_power_off(void) {
|
|
// TODO: There's a lot of other stuff that must be done to prevent
|
|
// leakage from +3V3 into VAA.
|
|
if (hackrf_r9) {
|
|
LPC_GPIO->W3[6] = 1;
|
|
} else {
|
|
LPC_GPIO->W2[9] = 1;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief Early initialization code.
|
|
* @details This initialization must be performed just after stack setup
|
|
* and before any other initialization.
|
|
*/
|
|
extern "C" void __early_init(void) {
|
|
/*
|
|
* Upon exit from bootloader into SPIFI boot mode:
|
|
*
|
|
* Enabled:
|
|
* PLL1: IRC, M=/24, N=/1, P=/1, autoblock, direct = 288 MHz
|
|
* IDIVA: IRC /1 = 12 MHz
|
|
* IDIVB: PLL1 /9, autoblock = 32 MHz
|
|
* IDIVC: PLL1 /3, autoblock = 96 MHz
|
|
* IDIVD: IRC /1 = 12 MHz
|
|
* IDIVE: IRC /1 = 12 MHz
|
|
* BASE_M4_CLK: IDIVC, autoblock
|
|
* BASE_SPIFI_CLK: IDIVB, autoblock
|
|
*
|
|
* Disabled:
|
|
* XTAL_OSC
|
|
* PLL0USB
|
|
* PLL0AUDIO
|
|
*/
|
|
/* LPC43xx M4 takes about 500 usec to get to __early_init
|
|
* Before __early_init, LPC bootloader runs and starts our code. In user code, the process stack
|
|
* is initialized, hardware floating point is initialized, and stacks are zeroed,
|
|
*/
|
|
const uint32_t CORTEX_M4_CPUID = 0x410fc240;
|
|
const uint32_t CORTEX_M4_CPUID_MASK = 0xff0ffff0;
|
|
|
|
if( (SCB->CPUID & CORTEX_M4_CPUID_MASK) == CORTEX_M4_CPUID ) {
|
|
/* Enable unaligned exception handler */
|
|
SCB_CCR |= (1 << 3);
|
|
|
|
/* Enable MemManage, BusFault, UsageFault exception handlers */
|
|
SCB_SHCSR |= (1 << 18) | (1 << 17) | (1 << 16);
|
|
|
|
/* "The reset delay is counted in IRC clock cycles. If the core frequency
|
|
* CCLK is much higher than the IRC frequency, add a software delay of
|
|
* fCCLK/fIRC clock cycles between resetting and accessing any of the
|
|
* peripheral blocks."
|
|
*/
|
|
|
|
/* Don't reset these peripherals, as they're operating during initialization:
|
|
* WWDT, CREG, SCU, SPIFI
|
|
*/
|
|
LPC_RGU->RESET_CTRL[0] =
|
|
(1U << 16) // LCD_RST
|
|
| (1U << 17) // USB0_RST
|
|
| (1U << 18) // USB1_RST
|
|
| (1U << 19) // DMA_RST
|
|
| (1U << 20) // SDIO_RST
|
|
| (1U << 21) // EMC_RST
|
|
| (1U << 22) // ETHERNET_RST
|
|
| (1U << 28) // GPIO_RST
|
|
;
|
|
LPC_RGU->RESET_CTRL[1] =
|
|
(1U << 0) // TIMER0_RST
|
|
| (1U << 1) // TIMER1_RST
|
|
| (1U << 2) // TIMER2_RST
|
|
| (1U << 3) // TIMER3_RST
|
|
| (1U << 4) // RITIMER_RST
|
|
| (1U << 5) // SCT_RST
|
|
| (1U << 6) // MOTOCONPWM_RST
|
|
| (1U << 7) // QEI_RST
|
|
| (1U << 8) // ADC0_RST
|
|
| (1U << 9) // ADC1_RST
|
|
| (1U << 10) // DAC_RST
|
|
| (1U << 12) // UART0_RST
|
|
| (1U << 13) // UART1_RST
|
|
| (1U << 14) // UART2_RST
|
|
| (1U << 15) // UART3_RST
|
|
| (1U << 16) // I2C0_RST
|
|
| (1U << 17) // I2C1_RST
|
|
| (1U << 18) // SSP0_RST
|
|
| (1U << 19) // SSP1_RST
|
|
| (1U << 20) // I2S_RST
|
|
| (1U << 22) // CAN1_RST
|
|
| (1U << 23) // CAN0_RST
|
|
| (1U << 24) // M0APP_RST
|
|
| (1U << 25) // SGPIO_RST
|
|
| (1U << 26) // SPI_RST
|
|
| (1U << 28) // ADCHS_RST
|
|
;
|
|
|
|
configure_spifi();
|
|
|
|
LPC_CCU1->CLK_M4_M0APP_CFG.RUN = true;
|
|
LPC_CREG->M0APPMEMMAP = LPC_SPIFI_DATA_CACHED_BASE + 0x0;
|
|
LPC_RGU->RESET_CTRL[1] = 0;
|
|
|
|
/* Prevent the M4 from doing any more initializing by sleep-waiting forever...
|
|
* ...until the M0 resets the M4 with some code to run.
|
|
*/
|
|
while(1) {
|
|
__WFE();
|
|
}
|
|
}
|
|
}
|
|
|
|
extern "C" void __late_init(void) {
|
|
/*
|
|
* System initializations.
|
|
* - HAL initialization, this also initializes the configured device drivers
|
|
* and performs the board-specific initializations.
|
|
* - Kernel initialization, the main() function becomes a thread and the
|
|
* RTOS is active.
|
|
*/
|
|
halInit();
|
|
|
|
/* After this call, scheduler, systick, heap, etc. are available. */
|
|
/* By doing chSysInit() here, it runs before C++ constructors, which may
|
|
* require the heap.
|
|
*/
|
|
chSysInit();
|
|
}
|
|
|
|
/**
|
|
* @brief Board-specific initialization code.
|
|
* @todo Add your board-specific code, if any.
|
|
*/
|
|
extern "C" void boardInit(void) {
|
|
/* Detect HackRF variant */
|
|
hackrf_r9 = detect_hackrf_r9();
|
|
/* Configure variant-dependent pins. */
|
|
if (hackrf_r9) {
|
|
setup_gpios(gpio_setup_r9);
|
|
setup_pins(pins_setup_r9);
|
|
} else {
|
|
setup_gpios(gpio_setup_og);
|
|
setup_pins(pins_setup_og);
|
|
}
|
|
vaa_power_on();
|
|
if (hackrf_r9) {
|
|
LPC_GPIO->W2[9] = 1;
|
|
} else {
|
|
LPC_GPIO->W3[6] = 1;
|
|
}
|
|
}
|
|
|
|
extern "C" void _default_exit(void) {
|
|
if (hackrf_r9) {
|
|
LPC_GPIO->W2[9] = 0;
|
|
} else {
|
|
LPC_GPIO->W3[6] = 0;
|
|
}
|
|
vaa_power_off();
|
|
|
|
chSysDisable();
|
|
|
|
systick_stop();
|
|
|
|
/* Don't reset these peripherals, as they're operating during shutdown:
|
|
* WWDT, CREG, SCU, SPIFI, GPIO, M0APP
|
|
*/
|
|
LPC_RGU->RESET_CTRL[0] =
|
|
(1U << 16) // LCD_RST
|
|
| (1U << 17) // USB0_RST
|
|
| (1U << 18) // USB1_RST
|
|
| (1U << 19) // DMA_RST
|
|
| (1U << 20) // SDIO_RST
|
|
| (1U << 21) // EMC_RST
|
|
| (1U << 22) // ETHERNET_RST
|
|
//| (1U << 28) // GPIO_RST
|
|
;
|
|
LPC_RGU->RESET_CTRL[1] =
|
|
(1U << 0) // TIMER0_RST
|
|
| (1U << 1) // TIMER1_RST
|
|
| (1U << 2) // TIMER2_RST
|
|
| (1U << 3) // TIMER3_RST
|
|
| (1U << 4) // RITIMER_RST
|
|
| (1U << 5) // SCT_RST
|
|
| (1U << 6) // MOTOCONPWM_RST
|
|
| (1U << 7) // QEI_RST
|
|
| (1U << 8) // ADC0_RST
|
|
| (1U << 9) // ADC1_RST
|
|
| (1U << 10) // DAC_RST
|
|
| (1U << 12) // UART0_RST
|
|
| (1U << 13) // UART1_RST
|
|
| (1U << 14) // UART2_RST
|
|
| (1U << 15) // UART3_RST
|
|
| (1U << 16) // I2C0_RST
|
|
| (1U << 17) // I2C1_RST
|
|
| (1U << 18) // SSP0_RST
|
|
| (1U << 19) // SSP1_RST
|
|
| (1U << 20) // I2S_RST
|
|
| (1U << 22) // CAN1_RST
|
|
| (1U << 23) // CAN0_RST
|
|
//| (1U << 24) // M0APP_RST
|
|
| (1U << 25) // SGPIO_RST
|
|
| (1U << 26) // SPI_RST
|
|
| (1U << 28) // ADCHS_RST
|
|
;
|
|
}
|