mirror of
https://github.com/eried/portapack-mayhem.git
synced 2024-12-24 06:49:24 -05:00
64 lines
1.2 KiB
INI
64 lines
1.2 KiB
INI
update=Mon 19 Jun 2017 03:56:47 PM PDT
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version=1
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last_client=kicad
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[cvpcb]
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version=1
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NetIExt=net
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[cvpcb/libraries]
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EquName1=devcms
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[general]
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version=1
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[eeschema]
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version=1
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LibDir=../../../library-kicad
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[eeschema/libraries]
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LibName1=portapack_h1-rescue
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LibName2=hackrf_expansion
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LibName3=passive
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LibName4=supply
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LibName5=trs_jack
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LibName6=battery
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LibName7=sd
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LibName8=ck
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LibName9=altera
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LibName10=regulator
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LibName11=tp
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LibName12=header
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LibName13=hole
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LibName14=sharebrained
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LibName15=fiducial
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LibName16=eastrising
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LibName17=on_semi
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LibName18=asahi_kasei
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LibName19=ti
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LibName20=diode
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[pcbnew]
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version=1
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PageLayoutDescrFile=
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LastNetListRead=portapack_h1.net
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PadDrill=0
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PadDrillOvalY=0
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PadSizeH=2.25
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PadSizeV=2.25
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PcbTextSizeV=1.5
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PcbTextSizeH=1.5
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PcbTextThickness=0.3
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ModuleTextSizeV=0.6095999999999999
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ModuleTextSizeH=0.6095999999999999
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ModuleTextSizeThickness=0.12
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SolderMaskClearance=0.07619999999999999
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SolderMaskMinWidth=0.1016
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DrawSegmentWidth=0.1524
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BoardOutlineThickness=0.09999999999999999
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ModuleOutlineThickness=0.1524
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[schematic_editor]
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version=1
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PageLayoutDescrFile=
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PlotDirectoryName=
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SubpartIdSeparator=0
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SubpartFirstId=65
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NetFmtName=Pcbnew
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SpiceForceRefPrefix=0
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SpiceUseNetNumbers=0
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LabSize=60
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