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https://github.com/eried/portapack-mayhem.git
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797e63a590
Determine hardware version and use one of two CPLD bitstream files.
128 lines
2.9 KiB
Python
Executable File
128 lines
2.9 KiB
Python
Executable File
#!/usr/bin/env python
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#
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# Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
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#
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# This file is part of PortaPack.
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#
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# This program is free software; you can redistribute it and/or modify
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# it under the terms of the GNU General Public License as published by
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# the Free Software Foundation; either version 2, or (at your option)
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# any later version.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; see the file COPYING. If not, write to
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# the Free Software Foundation, Inc., 51 Franklin Street,
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# Boston, MA 02110-1301, USA.
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#
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# Very fragile code to extract data from Altera MAX V CPLD SVF
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import sys
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if len(sys.argv) != 3:
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print('Usage: <command> <Altera MAX V CPLD SVF file path> <revision name>')
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sys.exit(-1)
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f = open(sys.argv[1], 'r')
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revision_name = sys.argv[2]
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calculate_crc = False
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# !PROGRAM
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# SIR 10 TDI (203);
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# RUNTEST 93 TCK;
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# SDR 13 TDI (0000);
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# SIR 10 TDI (2F4);
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# RUNTEST 93 TCK;
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# while:
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# SDR 16 TDI (7FFF);
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# RUNTEST 1800 TCK;
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# SIR 10 TDI (203);
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# RUNTEST 93 TCK;
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# SDR 13 TDI (0001);
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# SIR 10 TDI (2F4);
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# RUNTEST 93 TCK;
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phase = None
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block_0 = []
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block_1 = []
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current_block = None
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for line in f:
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line = line.strip().upper()
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if line == '!PROGRAM':
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phase = 'block_0'
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current_block = block_0
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elif line == '!VERIFY':
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phase = 'verify'
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current_block = None
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if phase == 'block_0':
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if line == 'SDR 13 TDI (0001);':
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phase = 'block_1'
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current_block = block_1
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if phase == 'block_0' or phase == 'block_1':
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if line.startswith('SDR 16 TDI ('):
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sdr_value = int(line.split('(', 1)[1][:4], 16)
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#print('0x%04x,' % sdr_value)
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current_block.append(sdr_value)
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def print_block(block):
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for n in range(0, len(block), 8):
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chunk = block[n:n+8]
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line = ['0x%04x,' % v for v in chunk]
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print('\t%s' % ' '.join(line))
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def crc32(blocks):
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import zlib
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crc_bytes = []
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for block in blocks:
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for word in block:
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crc_bytes.append((word >> 0) & 0xff)
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crc_bytes.append((word >> 8) & 0xff)
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return zlib.crc32(bytearray(crc_bytes)) & 0xffffffff
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print("""#include "portapack_cpld_data.hpp"
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#include <cstdint>
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#include <array>
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namespace portapack {
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namespace cpld {
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namespace %s {
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""" % revision_name)
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print('const std::array<uint16_t, %d> block_0 { {' % len(block_0))
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print_block(block_0)
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print("""} };
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""")
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print('const std::array<uint16_t, %d> block_1 { {' % len(block_1))
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print_block(block_1)
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print("""} };
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} /* namespace %s */
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} /* namespace cpld */
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} /* namespace portapack */
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""" % revision_name)
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if calculate_crc:
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# Apply post-programming modification to make post-programming CRC correct:
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programmed_block_0 = block_0[:]
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programmed_block_0[0] &= 0xfbff
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crc = crc32((programmed_block_0, block_1))
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print('%08x' % crc)
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