mirror of
https://github.com/eried/portapack-mayhem.git
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920b98f7c9
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
188 lines
5.2 KiB
VHDL
188 lines
5.2 KiB
VHDL
--
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-- Copyright (C) 2012 Jared Boone, ShareBrained Technology, Inc.
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--
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-- This file is part of PortaPack.
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--
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-- This program is free software; you can redistribute it and/or modify
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-- it under the terms of the GNU General Public License as published by
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-- the Free Software Foundation; either version 2, or (at your option)
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-- any later version.
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--
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-- This program is distributed in the hope that it will be useful,
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-- but WITHOUT ANY WARRANTY; without even the implied warranty of
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-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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-- GNU General Public License for more details.
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--
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-- You should have received a copy of the GNU General Public License
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-- along with this program; see the file COPYING. If not, write to
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-- the Free Software Foundation, Inc., 51 Franklin Street,
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-- Boston, MA 02110-1301, USA.
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library ieee;
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use ieee.std_logic_1164.all;
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entity top is
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port (
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MCU_D : inout std_logic_vector(7 downto 0);
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MCU_DIR : in std_logic;
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MCU_IO_STBX : in std_logic;
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MCU_LCD_WRX : in std_logic;
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MCU_ADDR : in std_logic;
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MCU_LCD_TE : out std_logic;
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MCU_P2_8 : in std_logic;
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MCU_LCD_RDX : in std_logic;
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TP_U : out std_logic;
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TP_D : out std_logic;
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TP_L : out std_logic;
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TP_R : out std_logic;
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SW_SEL : in std_logic;
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SW_ROT_A : in std_logic;
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SW_ROT_B : in std_logic;
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SW_U : in std_logic;
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SW_D : in std_logic;
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SW_L : in std_logic;
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SW_R : in std_logic;
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LCD_RESETX : out std_logic;
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LCD_RS : out std_logic;
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LCD_WRX : out std_logic;
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LCD_RDX : out std_logic;
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LCD_DB : inout std_logic_vector(15 downto 0);
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LCD_TE : in std_logic;
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LCD_BACKLIGHT : out std_logic;
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AUDIO_RESETX : out std_logic;
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REF_EN : out std_logic;
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GPS_RESETX : out std_logic;
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GPS_TX_READY : in std_logic;
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GPS_TIMEPULSE : in std_logic
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);
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end top;
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architecture rtl of top is
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signal switches : std_logic_vector(7 downto 0);
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type data_direction_t is (from_mcu, to_mcu);
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signal data_dir : data_direction_t;
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signal mcu_data_out_lcd : std_logic_vector(7 downto 0);
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signal mcu_data_out_io : std_logic_vector(7 downto 0);
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signal mcu_data_out : std_logic_vector(7 downto 0);
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signal mcu_data_in : std_logic_vector(7 downto 0);
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signal lcd_data_in : std_logic_vector(15 downto 0);
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signal lcd_data_in_mux : std_logic_vector(7 downto 0);
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signal lcd_data_out : std_logic_vector(15 downto 0);
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signal lcd_data_in_q : std_logic_vector(7 downto 0) := (others => '0');
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signal lcd_data_out_q : std_logic_vector(7 downto 0) := (others => '0');
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signal tp_q : std_logic_vector(7 downto 0) := (others => '0');
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signal lcd_reset_q : std_logic := '1';
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signal lcd_backlight_q : std_logic := '0';
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signal audio_reset_q : std_logic := '1';
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signal ref_en_q : std_logic := '0';
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signal dir_read : boolean;
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signal dir_write : boolean;
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signal lcd_read_strobe : boolean;
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signal lcd_write_strobe : boolean;
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signal lcd_write : boolean;
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signal io_strobe : boolean;
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signal io_read_strobe : boolean;
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signal io_write_strobe : boolean;
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begin
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-- I/O data
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switches <= LCD_TE & not SW_ROT_B & not SW_ROT_A & not SW_SEL & not SW_U & not SW_D & not SW_L & not SW_R;
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TP_U <= tp_q(3) when tp_q(7) = '1' else 'Z';
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TP_D <= tp_q(2) when tp_q(6) = '1' else 'Z';
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TP_L <= tp_q(1) when tp_q(5) = '1' else 'Z';
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TP_R <= tp_q(0) when tp_q(4) = '1' else 'Z';
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LCD_BACKLIGHT <= lcd_backlight_q;
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MCU_LCD_TE <= LCD_TE;
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-- State management
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data_dir <= to_mcu when MCU_DIR = '1' else from_mcu;
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dir_read <= (data_dir = to_mcu);
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dir_write <= (data_dir = from_mcu);
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io_strobe <= (MCU_IO_STBX = '0');
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io_read_strobe <= io_strobe and dir_read;
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lcd_read_strobe <= (MCU_LCD_RDX = '0');
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lcd_write <= not lcd_read_strobe;
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-- LCD interface
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LCD_RS <= MCU_ADDR;
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LCD_RDX <= MCU_LCD_RDX;
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LCD_WRX <= MCU_LCD_WRX;
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lcd_data_out <= lcd_data_out_q & mcu_data_in;
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lcd_data_in <= LCD_DB;
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LCD_DB <= lcd_data_out when lcd_write else (others => 'Z');
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-- Reference clock
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REF_EN <= ref_en_q;
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-- Peripheral reset control
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LCD_RESETX <= not lcd_reset_q;
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AUDIO_RESETX <= not audio_reset_q;
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GPS_RESETX <= '1';
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-- MCU interface
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mcu_data_out_lcd <= lcd_data_in(15 downto 8) when lcd_read_strobe else lcd_data_in_q;
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mcu_data_out_io <= switches;
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mcu_data_out <= mcu_data_out_io when io_read_strobe else mcu_data_out_lcd;
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mcu_data_in <= MCU_D;
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MCU_D <= mcu_data_out when dir_read else (others => 'Z');
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-- Synchronous behaviors:
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-- LCD write: Capture LCD high byte on LCD_WRX falling edge.
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process(MCU_LCD_WRX, mcu_data_in)
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begin
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if falling_edge(MCU_LCD_WRX) then
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lcd_data_out_q <= mcu_data_in;
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end if;
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end process;
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-- LCD read: Capture LCD low byte on LCD_RD falling edge.
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process(MCU_LCD_RDX, lcd_data_in)
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begin
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if rising_edge(MCU_LCD_RDX) then
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lcd_data_in_q <= lcd_data_in(7 downto 0);
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end if;
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end process;
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-- I/O write (to resistive touch panel): Capture data from
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-- MCU and hold on TP pins until further notice.
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process(MCU_IO_STBX, dir_write, mcu_data_in, MCU_ADDR)
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begin
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if rising_edge(MCU_IO_STBX) and dir_write then
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if MCU_ADDR = '0' then
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tp_q <= mcu_data_in;
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else
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lcd_reset_q <= mcu_data_in(0);
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audio_reset_q <= mcu_data_in(1);
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ref_en_q <= mcu_data_in(6);
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lcd_backlight_q <= mcu_data_in(7);
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end if;
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end if;
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end process;
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end rtl;
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