mirror of
https://github.com/eried/portapack-mayhem.git
synced 2024-10-01 01:26:06 -04:00
134 lines
3.5 KiB
C++
134 lines
3.5 KiB
C++
/*
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* Copyright (C) 2015 Jared Boone, ShareBrained Technology, Inc.
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*
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* This file is part of PortaPack.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2, or (at your option)
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* any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; see the file COPYING. If not, write to
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* the Free Software Foundation, Inc., 51 Franklin Street,
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* Boston, MA 02110-1301, USA.
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*/
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#include "cpu_clock.hpp"
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#include <ch.h>
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#include <hal.h>
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#include "lpc43xx_cpp.hpp"
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using namespace lpc43xx;
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constexpr uint32_t systick_count(const uint32_t clock_source_f) {
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return clock_source_f / CH_FREQUENCY;
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}
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constexpr uint32_t systick_load(const uint32_t clock_source_f) {
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return systick_count(clock_source_f) - 1;
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}
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constexpr auto systick_count_irc = systick_load(clock_source_irc_f);
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constexpr auto systick_count_pll1 = systick_load(clock_source_pll1_f);
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constexpr auto systick_count_pll1_step = systick_load(clock_source_pll1_step_f);
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static void set_clock(LPC_CGU_BASE_CLK_Type& clk, const cgu::CLK_SEL clock_source) {
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clk.AUTOBLOCK = 1;
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clk.CLK_SEL = toUType(clock_source);
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}
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void cpu_clock_irc() {
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/* Set M4 clock to safe default speed (~12MHz IRC) */
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set_clock(LPC_CGU->BASE_M4_CLK, cgu::CLK_SEL::IRC);
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systick_adjust_period(systick_count_irc);
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halLPCSetSystemClock(clock_source_irc_f);
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}
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void cpu_xtal_start() {
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LPC_CGU->XTAL_OSC_CTRL.BYPASS = 0;
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LPC_CGU->XTAL_OSC_CTRL.HF = 0;
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LPC_CGU->XTAL_OSC_CTRL.ENABLE = 0;
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halPolledDelay(US2RTT(250));
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}
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void cpu_clock_max_speed() {
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/* Incantation from LPC43xx UM10503 section 12.2.1.1, to bring the M4
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* core clock speed to the 110 - 204MHz range.
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*/
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cpu_clock_irc();
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cpu_xtal_start();
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/* Step into the 90-110MHz M4 clock range */
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cgu::pll1::ctrl({
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.pd = 0,
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.bypass = 0,
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.fbsel = 0,
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.direct = 0,
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.psel = 0,
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.autoblock = 1,
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.nsel = 0,
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.msel = 16,
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.clk_sel = cgu::CLK_SEL::XTAL,
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});
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while( !cgu::pll1::is_locked() );
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/* Switch M4 clock to PLL1 running at intermediate rate */
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set_clock(LPC_CGU->BASE_M4_CLK, cgu::CLK_SEL::PLL1);
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systick_adjust_period(systick_count_pll1_step);
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halLPCSetSystemClock(clock_source_pll1_step_f);
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/* Delay >50us at 90-110MHz clock speed */
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halPolledDelay(US2RTT(50));
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/* Remove /2P divider from PLL1 output to achieve full speed */
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cgu::pll1::direct();
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systick_adjust_period(systick_count_pll1);
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halLPCSetSystemClock(clock_source_pll1_f);
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}
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void cpu_start_audio_pll() {
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cgu::pll0audio::ctrl({
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.pd = 1,
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.bypass = 0,
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.directi = 0,
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.directo = 0,
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.clken = 0,
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.frm = 0,
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.autoblock = 1,
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.pllfract_req = 1,
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.sel_ext = 0,
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.mod_pd = 0,
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.clk_sel = cgu::CLK_SEL::XTAL,
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});
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/* For 12MHz clock source, 48kHz audio rate, 256Fs MCLK:
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* Fout=12.288MHz, Fcco=417.792MHz
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* PDEC=3, NDEC=1, PLLFRACT=0x1a1cac
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*/
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cgu::pll0audio::mdiv({
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.mdec = 0x5B6A,
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});
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cgu::pll0audio::np_div({
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.pdec = 3,
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.ndec = 1,
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});
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cgu::pll0audio::frac({
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.pllfract_ctrl = 0x1a1cac,
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});
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cgu::pll0audio::power_up();
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while( !cgu::pll0audio::is_locked() );
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cgu::pll0audio::clock_enable();
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set_clock(LPC_CGU->BASE_AUDIO_CLK, cgu::CLK_SEL::PLL0AUDIO);
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}
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