portapack-mayhem/hardware/portapack_h1/lcd_sw_sd.sch
Maescool 920b98f7c9 Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.

* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.

* Schematic: Update power net labels.

* Schematic: Update footprint names to match library changes.

* Schematic: Update header vendor and part numbers.

* Schematic: Specify (arbitrary) value for PDN# net.

* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.

* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.

* Schematic: Update copyright year.

* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.

* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.

* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...

* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.

* PCB: Update copyright on drawing.

* Update schematic and PCB date and revision.

* gitignore: Sublime Text editor project/workspace files

* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...

* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.

* LPC43xx: Add CGU IDIVx struct/union type.

* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.

* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)

* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.

* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.

* MAX V CPLD: Reverse verify data checking logic to make it a little faster.

* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.

* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.

* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...

* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

* CPLD: Add pins and logic for new PortaPack hardware feature(s).

* CPLD: Bitstream to support new hardware features.

* Clock Generator: Add a couple more setter methods for ClockControl registers.

* Clock Manager: Use shared MCU CLKIN clock control configuration constant.

* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

* Clock Manager: Remove redundant clock generator output enable.

* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.

* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...

* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

* PortaPack IO: Expose method to set reference oscillator enable pin.

* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

* Pin configuration: Disable input buffers on pins that are never read.

* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.

* Remove unused board files.

* Add LPC43xx functions.

* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

* LPC43xx: Add MCPWM peripheral struct.

* clock generator: Use recommended PLL reset register value.

Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.

* GPIO: Tweak masking of SCU function.

I don't remember why I thought this was necessary...

* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

* SCU: Add struct to hold pin configuration.

* PAL: Add functions to address The Glitch.

https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/

* PAL/board: New IO initialization code

Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.

* Merge M0 and M4 to eliminate need for bootstrap firmware

During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.

* Pins: Miscellaneous SCU configuration tweaks.

* Little code clarity improvement.

* bootstrap: Remove, not necessary.

* Clock Manager: Large re-working to support external references.

* Fix merge conflicts
2019-01-11 06:56:21 +00:00

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EESchema Schematic File Version 4
LIBS:portapack_h1-cache
EELAYER 26 0
EELAYER END
$Descr A4 11693 8268
encoding utf-8
Sheet 3 6
Title "PortaPack H1"
Date "2018-08-20"
Rev "20180820"
Comp "ShareBrained Technology, Inc."
Comment1 "Copyright © 2014-2018 Jared Boone"
Comment2 "License: GNU General Public License, version 2"
Comment3 ""
Comment4 ""
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$Comp
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$Comp
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$Comp
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$Comp
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$Comp
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$Comp
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$Comp
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$Comp
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$Comp
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$Comp
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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Entry Wire Line
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$Comp
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Wire Wire Line
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Wire Wire Line
3200 6300 3100 6300
Wire Wire Line
2200 6500 3200 6500
Wire Wire Line
2200 6400 3200 6400
Wire Wire Line
2200 6200 3200 6200
Wire Wire Line
2200 6000 3200 6000
Wire Wire Line
2200 5900 3200 5900
Wire Wire Line
2200 5800 3200 5800
Wire Wire Line
2800 5700 2800 6100
Connection ~ 2800 6100
Connection ~ 8000 1800
Wire Wire Line
9200 2500 10000 2500
Wire Wire Line
9200 2600 10000 2600
Wire Wire Line
9200 2700 10000 2700
Wire Wire Line
9200 2800 10000 2800
Wire Wire Line
9200 2900 10000 2900
Wire Wire Line
9200 3000 10000 3000
Wire Wire Line
9200 3100 10000 3100
Wire Wire Line
9200 3200 10000 3200
Wire Wire Line
9600 4400 10000 4400
Wire Wire Line
9600 4300 10000 4300
Wire Wire Line
7900 1800 8000 1800
Wire Wire Line
9600 4500 10000 4500
Wire Wire Line
9200 3300 10000 3300
Wire Wire Line
9200 3400 10000 3400
Wire Wire Line
9200 3500 10000 3500
Wire Wire Line
9200 3600 10000 3600
Wire Wire Line
9200 3700 10000 3700
Wire Wire Line
9200 3800 10000 3800
Wire Wire Line
9200 3900 10000 3900
Wire Wire Line
9200 4000 10000 4000
Wire Wire Line
9900 6000 10000 6000
Wire Wire Line
9600 5500 10000 5500
Wire Wire Line
9600 5400 10000 5400
Wire Wire Line
9600 5300 10000 5300
Wire Wire Line
10000 5200 9600 5200
Wire Wire Line
9600 4700 10000 4700
Wire Wire Line
9800 5000 10000 5000
Wire Wire Line
9800 4800 9900 4800
Wire Wire Line
10000 5100 9900 5100
Wire Wire Line
10000 1400 9900 1400
Wire Wire Line
10000 1500 9900 1500
$Comp
L power:+1V8 #PWR042
U 1 1 58BA7696
P 9900 1400
F 0 "#PWR042" H 9900 1540 20 0001 C CNN
F 1 "+1V8" H 9900 1510 30 0000 C CNN
F 2 "" H 9900 1400 60 0000 C CNN
F 3 "" H 9900 1400 60 0000 C CNN
1 9900 1400
0 -1 -1 0
$EndComp
Text HLabel 9550 900 0 60 Input ~ 0
LCD_VBL
Text Notes 1200 2700 0 60 ~ 0
EN/DIM: 200k PD internal, enable > 1.3V, disable < 0.4V\nRSET: not required, default 25mA current\nUVLO: 2.0V typ
Text HLabel 4100 3000 2 60 Input ~ 0
LCD_VBL
$Comp
L Device:C C14
U 1 1 58D0DFA2
P 4000 3300
F 0 "C14" H 4050 3400 50 0000 L CNN
F 1 "1U" H 4050 3200 50 0000 L CNN
F 2 "ipc_capc:IPC_CAPC160X80X90L35N" H 4000 3300 60 0001 C CNN
F 3 "" H 4000 3300 60 0000 C CNN
F 4 "Murata" H 4000 3300 60 0001 C CNN "Mfr"
F 5 "GRM188R61C105KA93D" H 4000 3300 60 0001 C CNN "Part"
1 4000 3300
-1 0 0 -1
$EndComp
$Comp
L power:GND #PWR043
U 1 1 58D0E0F8
P 4000 3600
F 0 "#PWR043" H 4000 3600 30 0001 C CNN
F 1 "GND" H 4000 3530 30 0001 C CNN
F 2 "" H 4000 3600 60 0000 C CNN
F 3 "" H 4000 3600 60 0000 C CNN
1 4000 3600
1 0 0 -1
$EndComp
Connection ~ 4000 3000
Wire Wire Line
9900 1600 9900 1700
Wire Wire Line
9900 1600 10000 1600
Wire Wire Line
9900 1900 10000 1900
Wire Wire Line
9900 2300 9900 2400
Wire Wire Line
9900 2200 9900 2300
Wire Wire Line
9900 2100 9900 2200
Wire Wire Line
9900 2000 9900 2100
Wire Wire Line
9900 4800 10000 4800
Wire Wire Line
2800 6100 3200 6100
Wire Wire Line
8000 1800 10000 1800
Wire Wire Line
4000 3000 4100 3000
Wire Wire Line
3700 3100 3700 3200
Wire Wire Line
3700 3500 3700 3700
Wire Wire Line
4000 3450 4000 3600
Wire Wire Line
4000 3000 4000 3150
Wire Wire Line
2400 6100 2400 6950
Wire Wire Line
2400 7250 2400 7400
Wire Wire Line
2800 7250 2800 7400
Wire Wire Line
2800 6100 2800 6950
Wire Wire Line
8000 1800 8000 2000
Wire Wire Line
8000 2300 8000 2500
Wire Bus Line
9100 2100 9100 3900
$EndSCHEMATC