Commit Graph

25 Commits

Author SHA1 Message Date
jLynx
e3da9d4cb2
Included DLL files (#654) 2022-05-21 12:11:03 +12:00
jLynx
d98f2b40df Added exe's 2022-04-06 20:52:01 +12:00
eried
a07683b2a6 Merge branch 'next' 2021-11-24 14:58:11 +01:00
heurist1
b499380448 Keep items with loc above those without
Removed fixsbt and added a new state of signal without position. Positions stay higher than non positions.
2021-10-29 16:59:52 +01:00
Erwin Ried
1207bac215 Ignore python venvs 2020-10-24 22:26:31 +02:00
eried
4675ecff59 Update .gitignore 2020-07-02 06:43:54 +02:00
Erwin Ried
e889a54e55 Example sound clips
From www.myinstants.com
2020-05-24 21:40:28 +02:00
Maescool
920b98f7c9 Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.

* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.

* Schematic: Update power net labels.

* Schematic: Update footprint names to match library changes.

* Schematic: Update header vendor and part numbers.

* Schematic: Specify (arbitrary) value for PDN# net.

* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.

* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.

* Schematic: Update copyright year.

* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.

* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.

* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...

* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.

* PCB: Update copyright on drawing.

* Update schematic and PCB date and revision.

* gitignore: Sublime Text editor project/workspace files

* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...

* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.

* LPC43xx: Add CGU IDIVx struct/union type.

* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.

* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)

* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.

* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.

* MAX V CPLD: Reverse verify data checking logic to make it a little faster.

* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.

* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.

* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...

* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.

* CPLD: Add pins and logic for new PortaPack hardware feature(s).

* CPLD: Bitstream to support new hardware features.

* Clock Generator: Add a couple more setter methods for ClockControl registers.

* Clock Manager: Use shared MCU CLKIN clock control configuration constant.

* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.

* Clock Manager: Remove redundant clock generator output enable.

* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.

* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.

* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.

* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.

* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.

* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.

* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...

* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.

* PortaPack IO: Expose method to set reference oscillator enable pin.

* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.

* Pin configuration: Disable input buffers on pins that are never read.

* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."

This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.

* Remove unused board files.

* Add LPC43xx functions.

* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.

* LPC43xx: Add MCPWM peripheral struct.

* clock generator: Use recommended PLL reset register value.

Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.

* GPIO: Tweak masking of SCU function.

I don't remember why I thought this was necessary...

* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.

* SCU: Add struct to hold pin configuration.

* PAL: Add functions to address The Glitch.

https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/

* PAL/board: New IO initialization code

Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.

* Merge M0 and M4 to eliminate need for bootstrap firmware

During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.

* Pins: Miscellaneous SCU configuration tweaks.

* Little code clarity improvement.

* bootstrap: Remove, not necessary.

* Clock Manager: Large re-working to support external references.

* Fix merge conflicts
2019-01-11 06:56:21 +00:00
furrtek
96828262d7 SD card files cleanup 2018-05-15 23:47:08 +01:00
furrtek
86a2790716 Removed numbers station samples 2018-05-15 23:37:26 +01:00
furrtek
986b54e43f Added ADSB RX details view
ADSB RX: Details and map view shouldn't freeze anymore
Added instructions to generate world_map.bin
2017-08-28 07:05:31 +01:00
furrtek
8e99bccd41 Started work on APRS (AX25) 2017-05-25 21:08:33 +01:00
furrtek
0102a34286 Reverted WFM mode to working state
TXView in ADSB TX
Lockable TXView
POCSAG TX bugfix with Alphanum and Numeric only
Testing Labels widget
2017-02-12 04:05:21 +00:00
furrtek
884d0c4f58 Missing toolchain-arm-cortex-m.cmake file 2017-02-11 23:12:49 +00:00
furrtek
f39954856e Ignores 2017-01-10 19:52:52 +00:00
furrtek
55ba0b5e06 Cleanup, random mode in DTMF TX 2016-09-23 20:17:29 +02:00
furrtek
d049553750 Removed terminator.img from ignore 2016-09-23 12:26:50 +02:00
furrtek
1b9465716f HH:MM in POCSAG RX 2016-08-23 14:35:14 +02:00
furrtek
0a549c8192 Manual frequency input in POCSAG RX
Changed firmware file name
2016-08-23 11:27:10 +02:00
furrtek
2177456b7e Ignore cmake files 2016-07-27 03:18:25 +02:00
furrtek
b4a113be59 Handwriting fixes 2016-05-11 01:03:42 +02:00
furrtek
00ee78f533 Play dead init 2015-09-15 22:34:36 +02:00
Jared Boone
9bf6ea2873 Additional .gitignores for build products. 2015-07-08 16:01:11 -07:00
Jared Boone
7962c3d7c6 More .gitignores. 2015-07-08 09:23:05 -07:00
Jared Boone
04b3388d7e Initial commit 2015-07-06 16:05:41 -07:00