Thanks @euquiq for a more common solution to the bug.
Added RX gain control.
Now we have full gain controls!
Merged PTT and Voice activation into one option selector.(allowing RIGHT BUTTON to work with PTT off)
This patch addresses the issue detected in: https://github.com/eried/portapack-mayhem/issues/159
This patch will revert the behavior of the function to_string_short_freq
into using spaces on the left of the integer part of the frequency (as it did originally).
When upgrading the scanner app, I did change the behavior of this function eliminating those spaces, so I could gain some characters-worth of space inside the scanner, but I failed to detect that it introduced some lack of padding on the rx->audio app.
Now, it is back as before, and I also did update the scanner so it can cope with the "extra spaces" this function now adds (again).
A bug that enabling audio RX resets the TX gain (perhaps because that changing to receiving mode modifies some registers) inspired me to add this gain control.
Commented out some steps which don't require for the VU meter to work again.
Moved some widgets for gain control.
Added CRC calculation for Vaisala radiosondes.
Added a Checkbox on APP for turning ON / OFF CRC. When CRC on, malformed packets are ignored.
Connected existing CRC function for METEOMAN sondes, using the same "CRC" checkbox logic.
Added the Vaisala RS41 data packet decoding.
Changed the default freq from 402.0 to 402.7 Mhz, since it is more popular freq.
Lowered the frequency stepping, so it is easier to fine-tune the exact freq center, if needed.
Sonde's Serial ID is passed into the VIEW MAP, so now the sonde is labelled on the map.
Earlier code did not start with squelch totally open, but a tiny bit closed. (now at app loading, squelch is truly set up with the same value it shows on screen).
I also hardcoded the NFM sampling rate and baseband bandwidth. It seemed "the right thing to do".
You can enable RX and adjust VOLUME and SQUELCH into your liking.
Sadly enough, you will NOT be able to use VOICE ACTIVATION when RX is enabled (to ensure there will be NO audio feedback defeating the VA sensing)
A "bug" that won over me, but perhaps and hopefully other coder can easily fix: The Vumeter will momentarily "dissappear" when enabling RX. But it will reappear as soon as you start TX. Or when you turn off RX.
I enabled the PEAK LEVEL MARK on the Vumeter, so you can easily see in which level your input voice / signal is peaking and regulate the MIC gain accordingly in an easier / more robust way.
Side enhancement: Took off the dark green, yellow and red coloring from the vumeter when no signal is present, and replaced it with dark_grey. I know that some coloring is "eye-candy" but the vu-meter is more readable with this new contrast.
The file rename function needs to be called with full_path/old_name and full_path/new_name.
Instead, it was called with full_path/old_name and new_name ... thus the renamed file ended on the root dir (path not preserved).
Squelch value now goes from -90 to +20 and it's directly compared against the max_db parameter returned from each freq scanned by the radio subsystem, with no adjusts or manipulation (you adjust the number as will be used).
Less squelch means weaker signals will trigger it. (as expected).
There was a tiny cosmetic bug when you deleted a frequency from the scanning memory: The description was not erased from screen and you could see it while the scan did not resume.
There was another bug on the pause button: If you asked for another manual scan range when paused, the button kept the text "RESUME" (its text was not reset to "PAUSE" again).
Added buttons for:
Change scanning direction (ascending / descending)
Saving current freq into the SCANNER.TXT file
(Please notice that, on the other hand -for safety issues- the DEL FQ button, deletes the frequency only from the temp memory on the actual scanning session, but does NOT erases the freq. inside the SCANNER.TXT)
Also there are other bug fixes and scanning speed enhancements.
MIC TX button :Shortcut for jumping into TX -> MIC app.
FREQ DEL button: Deletes currently displayed frequency from temporary scanning memory. Ideal to get rid of those not wanted "noisy" freqs in the middle of a range scan.
Also, some code optimizations thrown in.
I changed width in pixels of the "fine-tune cursor" from 2 to 5 , and then re-centered the cursor, from 120 to 118 to accomodate the shift in width.
I was inspired by this old ISSUE on Havoc's repository, where at the end @furrtek commented the need to make the red tick bigger in the future (but forgot / was swamped with other ehnancements / issues):
https://github.com/furrtek/portapack-havoc/issues/172
When scanner finds a freq with high dbi, it locks into it "listening" a bit more (less than a second) for either confirm or discard it as an actual high dbi or just a spurious thing.
The big number frequency changes color accordingly: Grey = just scanning, yellow = locking in, Green = Found something, allowing the user to listen.
New ui_scanner, inspired on AlainD's (alain00091) PR: https://github.com/eried/portapack-mayhem/pull/80
It includes the following:
1) A big frequency numbers display.
2) A Manual scan section (you can input a frequency range (START / END), choose a STEP value from an available of standard frequency intervals, and press SCAN button.
3) An AM / WFM / NFM scan mode selector, changing "on the fly".
4) A PAUSE / RESUME button, which will make the scanner to stop upon you listening something of interest
5) AUDIO APP button, a quick shortcut into the analog audio visualizing / recording app, with the mode, frequency, amp, LNA, VGA settings already in tune with the scanner.
6) Two enums are added to freqman.hpp, reserved for compatibility with AlainD's proposed freqman's app and / or further enhancement. More on this topic:
ORIGINAL scanner just used one frequency step, when creating scanning frequency ranges, which was unacceptable. AlainD enhanced freqman in order to pass different steppings along with ranges. This seems an excellent idea, and I preserved that aspect on my current implementation of thisscanner, while adding those enums into the freqman just to keep the door open for AlainD's freqman in the future.
7) I did eliminate the extra blank spaces added by function to_string_short_freq() which created unnecessary spacing in every app where there is need for a SHORT string, from a frequency number. (SHORT!, no extra spaces!!)
8) I also maintained AlainD idea of capping the number of frequencies which are dynamically created for each range and stored inside a memory based db. While AlainD capped the number into 400 frequencies, I was able to up that value a bit more, into 500.
Cheers!
As shown in https://github.com/eried/portapack-mayhem/issues/88 ...
Tiny bug but probably responsible for badly forming datetime in several apps, as it is used in ACARS, POCSAG and ADSB_TX (and of course AIS RX)
Lowered the scale -10 ºC so it accomodates less than zero temperatures, present sometimes when cold starting the system.
Added 1 char for temperature label length.
Adjusted the max2837 sensor value -> ºC temp result, by normalizing the conversion to correctly display the standard 25ºC, mentioned in Datasheet.
It reads the antennas definition from a txt file:
WHIPCALC/ANTENNAS.TXT
Inside the textfile you place each antenna you own with the following sintaxis:
<antenna label> <elements length in mm, separated by a space>
For example:
ANT500 185 315 450 586 724 862
Input the required frequency, adjust the wave type (full / half / quarter, etc.) and the calculator will return the antenna length (metric and imperial) while also calculating how much you need to expand the fitting antennas you got defined on the txt.
It may return up to 8 matching antennas, which is more than enough (normally you will have 2, perhaps 3 telescopic antennas around for your portapack)
If by any chance your antennas txt got more than 8 antennas, and more than 8 matches the length of the freq / wave you want, it will only show the first 8 matching antennas and will warn you at the bottom that there are even more results (hidden).
All calculations now are rounded into the best integer, considering first decimal, so precision is double than the original antenna calculator app.
Icons disappear when they are rolled over using the jog wheel and the colour is set to
ui::color::white()
Fixed by changing the colours of the icons to something other than ui::color::white()
* Analog TV app (PAL)
* Icon on main menu
* Analog TV should be yellow
Works for PAL only know, it would be nice to add NTSC in the future, or some customizable sync
* ui_transmitter : Added rf_amp field
* ui_transmitter : Added color grading depending on gain settings
* Removed TransmitterModel::set_rf_amp(bool) call from every apps loading ui_transmit
* transmitter_model : RF_amp disabled by default
* APRS Tx app : Fixed frequency keypad not showing up
* Morse Tx app : Removed TransmitterModel::set_lna() and TransmitterModel::set_vga() calls
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Release: Add generation of MD5SUMS, SHA256SUMS during "make release"
* Clock generator: Match clock output currents to HackRF firmware.
Someday, we will share a code base again...
* CMake: Make "firmware" target part of the "all" target.
So now an unqualified "make" will make the firmware binary.
* CMake: Change how HackRF firmware is incorporated into binary.
Use the separate HackRF "RAM" binary. Get rid of the strip-dfu utility, since there's no longer a need to extract the binary from the DFU.
* CMake: Renamed GIT_REVISION* -> GIT_VERSION* to match HackRF build env.
* CMake: Bring git version handling closer to HackRF for code reuse.
* Travis-CI: Rework CI release artifact output.
* Travis-CI: Don't assign PROJECT_NAME within deploy-nightly.sh
* Travis-CI: Oops, don't include distro package for compiler...
...when also installing it from a third-party PPA.
* Travis-CI: Update GCC package, old one seems "retired"?
* Travis-CI: OK, the gcc-arm-none-eabi package is NOT current. Undoing...
* Travis-CI: Path oopsies.
* Travis-CI: More path confusion. I think this will do it. *touch wood*
* Travis-CI: Update build message sent to FreeNode #portapack IRC.
* Travis-CI: Break out BUILD_DATE from BUILD_NAME.
* Travis-CI: Introduce build directories, include MD5 and SHA256 hashes.
* Travis-CI: Fix MD5SUMS/SHA256SUMS paths.
* Travis-CI: Fix typo generating name for binary links.
* Power: Keep 1V8 off until after VAA is brought up.
* Power: Bring up VAA in several steps to keep voltage swing small.
* About: Show longer commit/tag version string.
* Versioning: Report non-CI builds with "local-" version prefix.
* Travis-CI: Report new nightly build site in IRC notification.
* Change use of GIT_VERSION to VERSION_STRING
Required by prior merge.
* Git: add "hackrf" submodule.
* CMake: Use hackrf submodule for build, stop pulling during build.
* Travis: Fix build paths due to CMake submodule changes.
* Travis: Explicitly update submodules recursively
* Revert "Travis: Explicitly update submodules recursively"
This reverts commit b246438d805f431e727e01b7407540e932e89ee1.
* Travis: Try to sort out hackrf submodule output paths...
* Travis: I don't know what I'm doing.
* CMake: "make firmware" problem due to target vs. path used for dependency.
* HackRF: Incorporate YAML security fix.
* CMake: Fix more places where targets should be used...
...instead of paths to outputs.
* CMake: Add DFU file to "make firmware" outputs
* HackRF: Update submodule for CMake m0_bin.s path fix.
* added encoder support to alphanum
* added encoder support to freq-keypad
* UI Redesign -
added BtnGrid & NewButton widgets and created a new button-based
layout, with both encoder and touchscreen are supported.
* Scanner changes:
- using SCANNER.TXT for frequencies, ranges also supported. file
format is the same as any other frequency file, thus can be edited
via the Frequency Manager.
- add nfm bw selector & time-to-wait to the UI
- add SCANNER.TXT to sdcard dir
orignal idea & scanner file adopted from user 'bicurico'
* small changes to scanner
* remember last category on frequency manager
* fix: cast int16_t instead of uint16_t (although i doubt we will
have more than 32767 buttons in the array...)
* added a missing last_category_id on freq manager
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Setup: Format clock reference frequency in MHz, not Hz.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
* Pin config: VREGMODE=1, add other pins for completeness, comment detail
* Pin setup: More useful comments.
* Pin setup: Change some defaults, only set up PortaPack pins if detected.
* Pin setup: Disable LPC pull-ups on PP CPLD data bus, as CPLD is pulling up.
* Baseband: Allow larger HackRF firmware image.
* HackRF: Remove USER_INTERFACE CMake variable.
* CPLD: Make use of HackRF CPLD tool to generate code.
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
