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188 Commits 3 Branches 442 Tags 434 MiB
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6 Commits

Author SHA1 Message Date
Jared Boone
4974774f82 Simplify PLL math when correcting for PPM. 2015-08-25 17:56:03 -07:00
Jared Boone
fe7dcdc613 Function to adjust clock generator XTAL PLL frequency. 
Needed to switch PLLA to operate in fractional mode.
 2015-08-24 12:09:11 -07:00
Jared Boone
8797aa9758 Stop audio PLL if shutting down GP_CLKIN clock source. 2015-08-01 13:45:52 -07:00
Jared Boone
bfc73a6675 Move update_peripheral_clocks 
Incorrect order of operations would hang execution if switching to IRC.
 2015-08-01 13:44:52 -07:00
Jared Boone
c025a2bba2 Code to shut down ClockManager-controlled devices. 2015-08-01 13:43:58 -07:00
Jared Boone
dc6fee8370 Initial firmware commit. 2015-07-08 08:39:24 -07:00