Switch RFFC5072, MAX2837 back to 40MHz reference.

Turns out the MAX2837 can't tune the necessary range when given a 50MHz reference. Oops.
This commit is contained in:
Jared Boone 2015-09-02 17:45:19 -07:00
parent 293337b647
commit f1ca3fe5bb
2 changed files with 6 additions and 14 deletions

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@ -163,24 +163,16 @@ constexpr si5351::MultisynthFractional si5351_ms_10m {
};
constexpr auto si5351_ms_3_10m_reg = si5351_ms_10m.reg(3);
constexpr si5351::MultisynthFractional si5351_ms_50m {
constexpr si5351::MultisynthFractional si5351_ms_40m {
.f_src = si5351_vco_f,
.a = 16,
.a = 20,
.b = 0,
.c = 1,
.r_div = 0,
};
// constexpr si5351::MultisynthFractional si5351_ms_40m {
// .f_src = si5351_vco_f,
// .a = 20,
// .b = 0,
// .c = 1,
// .r_div = 0,
// };
constexpr auto si5351_ms_rffc5072 = si5351_ms_50m;
constexpr auto si5351_ms_max2837 = si5351_ms_50m;
constexpr auto si5351_ms_rffc5072 = si5351_ms_40m;
constexpr auto si5351_ms_max2837 = si5351_ms_40m;
constexpr auto si5351_ms_4_reg = si5351_ms_rffc5072.reg(clock_generator_output_first_if);
constexpr auto si5351_ms_5_reg = si5351_ms_max2837.reg(clock_generator_output_second_if);

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@ -49,8 +49,8 @@ constexpr ClockFrequency ssp1_pclk_f = base_m4_clk_f;
constexpr ClockFrequency max5864_spi_f = 20000000U;
constexpr ClockFrequency max2837_spi_f = 20000000U;
constexpr ClockFrequency rffc5072_reference_f = 50000000U;
constexpr ClockFrequency max2837_reference_f = 50000000U;
constexpr ClockFrequency rffc5072_reference_f = 40000000U;
constexpr ClockFrequency max2837_reference_f = 40000000U;
constexpr ClockFrequency mcu_clkin_f = 40000000U;
constexpr uint8_t si5351_i2c_address = 0x60;