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refactoring

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This commit is contained in:
bernd-herzog 2023-05-05 12:46:59 +02:00
parent 75718c79b9
commit da6c6bb03c
3 changed files with 18 additions and 54 deletions
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22
firmware/application/portapack.cpp
View File

@ -489,20 +489,14 @@ bool init() {
chThdSleepMilliseconds(10);
auto pp_config = portapack_cpld_config();
auto cpld_update_possible = portapack::cpld::update_possible(); //QFP100 CPLD fails this check. skip CPLD update
auto cpld_update_necessary = cpld_update_possible && portapack::cpld::update_necessary(pp_config);
if ( cpld_update_necessary ) {
auto ok = portapack::cpld::update(pp_config);
if( !ok ) {
chThdSleepMilliseconds(10);
// Mode left (R1) and right (R2,H2,H2+) bypass going into hackrf mode after failing CPLD update
// Mode center (autodetect), up (R1) and down (R2,H2,H2) will go into hackrf mode after failing CPLD update
if (load_config() != 3 /* left */ && load_config() != 4 /* right */){
shutdown_base();
return false;
}
uint32_t result = portapack::cpld::update_if_necessary(portapack_cpld_config());
if ( result == 3 /* program failed */ ) {
chThdSleepMilliseconds(10);
// Mode left (R1) and right (R2,H2,H2+) bypass going into hackrf mode after failing CPLD update
// Mode center (autodetect), up (R1) and down (R2,H2,H2) will go into hackrf mode after failing CPLD update
if (load_config() != 3 /* left */ && load_config() != 4 /* right */){
shutdown_base();
return false;
}
}

43
firmware/common/cpld_update.cpp
View File

@ -33,7 +33,9 @@
namespace portapack {
namespace cpld {
bool update_possible() {
uint32_t update_if_necessary(
const Config config
) {
jtag::GPIOTarget target {
portapack::gpio_cpld_tck,
portapack::gpio_cpld_tms,
@ -49,7 +51,7 @@ bool update_possible() {
/* Run-Test/Idle */
if( !cpld.idcode_ok() ) {
return false;
return 1;
}
cpld.sample();
@ -60,43 +62,16 @@ bool update_possible() {
* in passive state.
*/
if( !cpld.silicon_id_ok() ) {
return false;
return 2;
}
return true;
}
bool update_necessary(
const Config config
) {
jtag::GPIOTarget target {
portapack::gpio_cpld_tck,
portapack::gpio_cpld_tms,
portapack::gpio_cpld_tdi,
portapack::gpio_cpld_tdo
};
jtag::JTAG jtag { target };
CPLD cpld { jtag };
/* Verify CPLD contents against current bitstream. */
auto ok = cpld.verify(config.block_0, config.block_1);
return !ok;
}
bool update(
const Config config
) {
jtag::GPIOTarget target {
portapack::gpio_cpld_tck,
portapack::gpio_cpld_tms,
portapack::gpio_cpld_tdi,
portapack::gpio_cpld_tdo
};
jtag::JTAG jtag { target };
CPLD cpld { jtag };
/* CPLD verifies incorrectly. Erase and program with current bitstream. */
auto ok = cpld.program(config.block_0, config.block_1);
if( !ok ) {
ok = cpld.program(config.block_0, config.block_1);
}
/* If programming OK, reset CPLD to user mode. Otherwise leave it in
* passive (ISP) state.
@ -111,7 +86,7 @@ bool update(
cpld.disable();
}
return ok;
return ok ? 0 : 3;
}
} /* namespace cpld */

7
firmware/common/cpld_update.hpp
View File

@ -27,13 +27,8 @@
namespace portapack {
namespace cpld {
bool update_possible();
bool update_necessary(
const Config config
);
bool update(
uint32_t update_if_necessary(
const Config config
);