Minor Improvement (Extending_min_CLK_out_from_10khz_to_4khz) (#1675)

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Brumi-2021 2023-12-26 07:11:14 +01:00 committed by GitHub
parent 7bf3e02f6c
commit a85357a8af
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2 changed files with 3 additions and 3 deletions

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@ -194,8 +194,8 @@ SetRadioView::SetRadioView(
field_clkout_freq.set_value(pmem::clkout_freq());
field_clkout_freq.on_change = [this](SymField&) {
if (field_clkout_freq.to_integer() < 10)
field_clkout_freq.set_value(10);
if (field_clkout_freq.to_integer() < 4) // Min. CLK out of Si5351A/B/C-B is 2.5khz , but in our application -intermediate freq 800Mhz-,Min working CLK=4khz.
field_clkout_freq.set_value(4);
if (field_clkout_freq.to_integer() > 60000)
field_clkout_freq.set_value(60000);
};