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Adding Rx IQ error phase CAL to SPEC Audio_App (#1963)

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Brumi-2021 2024-03-09 23:46:38 +01:00 • committed by GitHub
parent 73c29f666f
commit 9d8132978f
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9 changed files with 125 additions and 17 deletions
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33
firmware/application/hw/max2837.cpp
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@ -150,7 +150,7 @@ void MAX2837::init() {
}
void MAX2837::set_tx_LO_iq_phase_calibration(const size_t v) {
/* IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
/* TX IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
// TX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,0,1 (5dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Tx_Calibration); // write to ram 3 LOGIC Pins .
@ -324,14 +324,41 @@ bool MAX2837::set_frequency(const rf::Frequency lo_frequency) {
return true;
}
void MAX2837::set_rx_lo_iq_calibration(const size_t v) {
/*
void MAX2837::set_rx_lo_iq_calibration(const size_t v) { // Original code , rewritten below
_map.r.rx_top_rx_bias.RX_IQERR_SPI_EN = 1;
_dirty[Register::RX_TOP_RX_BIAS] = 1;
_map.r.rxrf_2.iqerr_trim = v;
_dirty[Register::RXRF_2] = 1;
flush();
}
*/
void MAX2837::set_rx_LO_iq_phase_calibration(const size_t v) {
/* RX IQ phase deg CAL adj (+4 ...-4) in 32 steps (5 bits), 00000 = +4deg (Q lags I by 94degs, default), 01111 = +0deg, 11111 = -4deg (Q lags I by 86degs) */
// RX calibration , Logic pins , ENABLE, RXENABLE, TXENABLE = 1,1,0 (3dec), and Reg address 16, D1 (CAL mode 1):DO (CHIP ENABLE 1)
set_mode(Mode::Rx_Calibration); // write to ram 3 LOGIC Pins .
gpio_max283x_enable.output();
gpio_max2837_rxenable.output();
gpio_max2837_txenable.output();
_map.r.spi_en.CAL_SPI = 1; // Register Settings reg address 16, D1 (CAL mode 1)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (CHIP ENABLE 1)
flush_one(Register::SPI_EN);
_map.r.rx_top_rx_bias.RX_IQERR_SPI_EN = 1; // reg 8 D9, RX LO IQ Phase calibration SPI control. Active when Address 8 D<9> = 1.
flush_one(Register::RX_TOP_RX_BIAS);
_map.r.rxrf_2.iqerr_trim = v; // reg 1 D9:D5, RX LO I/Q Phase SPI 5 bits Adjust
flush_one(Register::RXRF_2);
// Exit Calibration mode, Go back to reg 16, D1:D0 , Out of CALIBRATION , back to default conditions, but keep CS activated.
_map.r.spi_en.CAL_SPI = 0; // Register Settings reg address 16, D1 (0 = Normal operation (default)
_map.r.spi_en.EN_SPI = 1; // Register Settings reg address 16, DO (1 = Chip select enable )
flush_one(Register::SPI_EN);
}
void MAX2837::set_rx_bias_trim(const size_t v) {
_map.r.rx_top_rx_bias.EN_Bias_Trim = 1;