mirror of
https://github.com/eried/portapack-mayhem.git
synced 2025-07-23 15:01:14 -04:00
Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
This commit is contained in:
Maescool
Furrtek
parent
bbb5dc3c12
commit
920b98f7c9
71 changed files with 9292 additions and 7067 deletions
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@ -100,53 +100,16 @@ bool get_ext_clock() {
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void poll_ext_clock() {
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auto clkin_status = clock_generator.clkin_status();
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if (clkin_status != prev_clkin_status) {
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prev_clkin_status = clkin_status;
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StatusRefreshMessage message { };
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EventDispatcher::send_message(message);
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clock_manager.init();
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clock_manager.init_peripherals();
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}
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}
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class Power {
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public:
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void init() {
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/* VAA powers:
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* MAX5864 analog section.
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* MAX2837 registers and other functions.
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* RFFC5072 analog section.
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*
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* Beware that power applied to pins of the MAX2837 may
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* show up on VAA and start powering other components on the
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* VAA net. So turn on VAA before driving pins from MCU to
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* MAX2837.
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*/
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/* Turn on VAA */
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gpio_vaa_disable.clear();
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gpio_vaa_disable.output();
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/* 1V8 powers CPLD internals.
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*/
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/* Turn on 1V8 */
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gpio_1v8_enable.set();
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gpio_1v8_enable.output();
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/* Set VREGMODE for switching regulator on HackRF One */
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gpio_vregmode.set();
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gpio_vregmode.output();
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}
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void shutdown() {
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gpio_1v8_enable.clear();
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gpio_vaa_disable.set();
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}
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private:
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};
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static Power power;
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enum class PortaPackModel {
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R1_20150901,
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@ -187,6 +150,25 @@ Backlight* backlight() {
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: static_cast<portapack::Backlight*>(&backlight_on_off);
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}
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static void configure_unused_mcu_peripherals_power_down(const bool power_down) {
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LPC_CGU->IDIVD_CTRL.PD = power_down;
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LPC_CGU->IDIVE_CTRL.PD = power_down;
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LPC_CGU->BASE_USB1_CLK.PD = power_down;
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LPC_CGU->BASE_SPI_CLK.PD = power_down;
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LPC_CGU->BASE_PHY_RX_CLK.PD = power_down;
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LPC_CGU->BASE_PHY_TX_CLK.PD = power_down;
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LPC_CGU->BASE_LCD_CLK.PD = power_down;
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LPC_CGU->BASE_SSP0_CLK.PD = power_down;
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LPC_CGU->BASE_UART0_CLK.PD = power_down;
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LPC_CGU->BASE_UART1_CLK.PD = power_down;
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LPC_CGU->BASE_UART2_CLK.PD = power_down;
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LPC_CGU->BASE_UART3_CLK.PD = power_down;
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LPC_CGU->BASE_OUT_CLK.PD = power_down;
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LPC_CGU->BASE_CGU_OUT0_CLK.PD = power_down;
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LPC_CGU->BASE_CGU_OUT1_CLK.PD = power_down;
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}
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static void configure_unused_mcu_peripherals(const bool enabled) {
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/* Disabling these peripherals reduces "idle" (PortaPack at main
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* menu) current by 42mA.
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@ -196,9 +178,17 @@ static void configure_unused_mcu_peripherals(const bool enabled) {
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*
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* RITIMER: M0 SysTick substitute (because M0 has no SysTick)
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* TIMER3: M0 cycle/PCLK counter
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* IDIVB: Clock for SPI (set up in bootstrap code)
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* IDIVC: I2S audio clock
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*/
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const uint32_t clock_run_state = enabled ? 1 : 0;
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const bool power_down = !enabled;
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if( power_down == false ) {
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// Power up peripheral clocks *before* enabling run state.
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configure_unused_mcu_peripherals_power_down(power_down);
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}
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LPC_CCU1->CLK_APB3_I2C1_CFG.RUN = clock_run_state;
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LPC_CCU1->CLK_APB3_DAC_CFG.RUN = clock_run_state;
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@ -230,6 +220,11 @@ static void configure_unused_mcu_peripherals(const bool enabled) {
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LPC_CCU2->CLK_APB0_UART1_CFG.RUN = clock_run_state;
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LPC_CCU2->CLK_APB0_USART0_CFG.RUN = clock_run_state;
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LPC_CCU2->CLK_APB0_SSP0_CFG.RUN = clock_run_state;
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if( power_down == true ) {
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// Power down peripheral clocks *after* disabling run state.
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configure_unused_mcu_peripherals_power_down(power_down);
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}
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}
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static void disable_unused_mcu_peripheral_clocks() {
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@ -243,9 +238,6 @@ static void enable_unused_mcu_peripheral_clocks() {
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static void shutdown_base() {
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clock_manager.shutdown();
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power.shutdown();
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// TODO: Wait a bit for supplies to discharge?
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chSysDisable();
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systick_stop();
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@ -256,49 +248,8 @@ static void shutdown_base() {
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}
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bool init() {
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for(const auto& pin : pins) {
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pin.init();
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}
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clock_manager.init_peripherals();
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/* Configure other pins */
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/* Glitch filter operates at 3ns instead of 50ns due to the WM8731
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* returning an ACK very fast (170ns) and confusing the I2C state
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* machine into thinking there was a bus error. It looks like the
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* MCU sees SDA fall before SCL falls, indicating a START at the
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* point an ACK is expected. With the glitch filter off or set to
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* 3ns, it's probably still a bit tight timing-wise, but improves
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* reliability on some problem units.
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*/
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LPC_SCU->SFSI2C0 =
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(1U << 0) // SCL: 3ns glitch
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| (0U << 2) // SCL: Standard/Fast mode
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| (1U << 3) // SCL: Input enabled
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| (0U << 7) // SCL: Enable input glitch filter
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| (1U << 8) // SDA: 3ns glitch
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| (0U << 10) // SDA: Standard/Fast mode
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| (1U << 11) // SDA: Input enabled
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| (0U << 15) // SDA: Enable input glitch filter
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;
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disable_unused_mcu_peripheral_clocks();
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LPC_CREG->CREG0 |= (1 << 5); // Disable USB0 PHY
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power.init();
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gpio_max5864_select.set();
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gpio_max5864_select.output();
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gpio_max2837_select.set();
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gpio_max2837_select.output();
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led_usb.setup();
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led_rx.setup();
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led_tx.setup();
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clock_manager.init();
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clock_manager.set_reference_ppb(persistent_memory::correction_ppb());
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clock_manager.run_at_full_speed();
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if( !portapack::cpld::update_if_necessary(portapack_cpld_config()) ) {
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shutdown_base();
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@ -311,6 +262,9 @@ bool init() {
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portapack::io.init();
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clock_manager.init_clock_generator();
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clock_manager.set_reference_ppb(persistent_memory::correction_ppb());
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audio::init(portapack_audio_codec());
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clock_manager.enable_first_if_clock();
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@ -340,12 +294,109 @@ void shutdown() {
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shutdown_base();
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}
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/* Bootstrap runs from SPIFI on the M4, immediately after the LPC43xx built-in
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* boot ROM runs.
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*/
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/* After boot ROM executes:
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* PLL1 is at 288MHz (IRC * 24)
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* IDIVB_CTRL = PLL1 / 9 = 32MHz
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* IDIVC_CTRL = PLL1 / 3 = 96MHz
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* BASE_SPIFI_CLK.CLK_SEL = IDIVB
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* BASE_M4_CLK.CLK_SEL = IDIVC?
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*/
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static void configure_spifi(void) {
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constexpr Pin pins_spifi[] = {
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{ 3, 3, PinConfig::spifi_sck(3) }, /* SPIFI_SCK: W25Q80BV.CLK(I), enable input buffer for timing feedback */
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{ 3, 4, PinConfig::spifi_inout(3) }, /* SPIFI_SIO3/P82: W25Q80BV.HOLD(IO) */
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{ 3, 5, PinConfig::spifi_inout(3) }, /* SPIFI_SIO2/P81: W25Q80BV.WP(IO) */
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{ 3, 6, PinConfig::spifi_inout(3) }, /* SPIFI_MISO: W25Q80BV.DO(IO) */
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{ 3, 7, PinConfig::spifi_inout(3) }, /* SPIFI_MOSI: W25Q80BV.DI(IO) */
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{ 3, 8, PinConfig::spifi_cs(3) }, /* SPIFI_CS/P68: W25Q80BV.CS(I) */
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};
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for(const auto& pin : pins_spifi) {
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pin.init();
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}
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/* Tweak SPIFI mode */
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LPC_SPIFI->CTRL =
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(0xffff << 0) /* Timeout */
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| (0x1 << 16) /* CS high time in "clocks - 1" */
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| (0 << 21) /* 0: Attempt speculative prefetch on data accesses */
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| (0 << 22) /* 0: No interrupt on command ended */
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| (0 << 23) /* 0: SCK driven low after rising edge at which last bit of command is captured. Stays low while CS# is high. */
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| (0 << 27) /* 0: Cache prefetching enabled */
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| (0 << 28) /* 0: Quad protocol, IO3:0 */
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| (1 << 29) /* 1: Read data sampled on falling edge of clock */
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| (1 << 30) /* 1: Read data is sampled using feedback clock from SCK pin */
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| (0 << 31) /* 0: DMA request disabled */
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;
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/* Throttle up the SPIFI interface to 96MHz (IDIVA=PLL1 / 3) */
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LPC_CGU->IDIVB_CTRL.word =
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( 0 << 0) /* PD */
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| ( 2 << 2) /* IDIV (/3) */
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| ( 1 << 11) /* AUTOBLOCK */
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| ( 9 << 24) /* PLL1 */
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;
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}
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extern "C" {
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void __early_init(void) {
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/*
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* Upon exit from bootloader into SPIFI boot mode:
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*
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* Enabled:
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* PLL1: IRC, M=/24, N=/1, P=/1, autoblock, direct = 288 MHz
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* IDIVA: IRC /1 = 12 MHz
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* IDIVB: PLL1 /9, autoblock = 32 MHz
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* IDIVC: PLL1 /3, autoblock = 96 MHz
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* IDIVD: IRC /1 = 12 MHz
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* IDIVE: IRC /1 = 12 MHz
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* BASE_M4_CLK: IDIVC, autoblock
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* BASE_SPIFI_CLK: IDIVB, autoblock
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*
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* Disabled:
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* XTAL_OSC
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* PLL0USB
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* PLL0AUDIO
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*/
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/* LPC43xx M4 takes about 500 usec to get to __early_init
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* Before __early_init, LPC bootloader runs and starts our code. In user code, the process stack
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* is initialized, hardware floating point is initialized, and stacks are zeroed,
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*/
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const uint32_t CORTEX_M4_CPUID = 0x410fc240;
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const uint32_t CORTEX_M4_CPUID_MASK = 0xff0ffff0;
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if( (SCB->CPUID & CORTEX_M4_CPUID_MASK) == CORTEX_M4_CPUID ) {
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/* Enable unaligned exception handler */
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SCB_CCR |= (1 << 3);
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/* Enable MemManage, BusFault, UsageFault exception handlers */
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SCB_SHCSR |= (1 << 18) | (1 << 17) | (1 << 16);
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reset();
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// disable_unused_mcu_peripheral_clocks();
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configure_spifi();
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LPC_CCU1->CLK_M4_M0APP_CFG.RUN = true;
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LPC_CREG->M0APPMEMMAP = LPC_SPIFI_DATA_CACHED_BASE + 0x0;
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LPC_RGU->RESET_CTRL[1] = 0;
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/* Prevent the M4 from doing any more initializing by sleep-waiting forever...
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* ...until the M0 resets the M4 with some code to run.
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*/
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while(1) {
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__WFE();
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}
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}
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}
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void __late_init(void) {
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reset();
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/*
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* System initializations.
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* - HAL initialization, this also initializes the configured device drivers
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Reference in a new issue