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Improve argument and retval types for my M4 SIMD intrinsics.

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This commit is contained in:
Jared Boone 2015-12-28 16:49:31 -08:00
parent 8453741252
commit 90cd2a6794
1 changed files with 24 additions and 24 deletions
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48
firmware/chibios-portapack/os/hal/platforms/LPC43xx_M4/lpc43xx_m4.h
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@ -134,34 +134,34 @@ typedef enum IRQn {
/* Overload of __SXTB16() to add ROR argument, since using __ROR() as an /* Overload of __SXTB16() to add ROR argument, since using __ROR() as an
* argument to the existing __SXTB16() doesn't produce optimum/sane code. * argument to the existing __SXTB16() doesn't produce optimum/sane code.
*/ */
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTB16(uint32_t rm, uint32_t ror) __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SXTB16(uint32_t rm, uint32_t ror)
{ {
uint32_t rd; int32_t rd;
__ASM volatile ("sxtb16 %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror)); __ASM volatile ("sxtb16 %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror));
return rd; return rd;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTH(uint32_t rm, uint32_t ror) __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SXTH(uint32_t rm, uint32_t ror)
{ {
uint32_t rd; int32_t rd;
__ASM volatile ("sxth %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror)); __ASM volatile ("sxth %0, %1, ror %2" : "=r" (rd) : "r" (rm), "I" (ror));
return rd; return rd;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLATB(uint32_t rm, uint32_t rs, uint32_t rn) { __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMLATB(uint32_t rm, uint32_t rs, uint32_t rn) {
uint32_t rd; int32_t rd;
__ASM volatile ("smlatb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn)); __ASM volatile ("smlatb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn));
return rd; return rd;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMLABB(uint32_t rm, uint32_t rs, uint32_t rn) { __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMLABB(uint32_t rm, uint32_t rs, uint32_t rn) {
uint32_t rd; int32_t rd;
__ASM volatile("smlabb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn)); __ASM volatile("smlabb %0, %1, %2, %3" : "=r" (rd) : "r" (rm), "r" (rs), "r" (rn));
return rd; return rd;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SXTAH(uint32_t rn, uint32_t rm, uint32_t ror) { __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SXTAH(uint32_t rn, uint32_t rm, uint32_t ror) {
uint32_t rd; int32_t rd;
__ASM volatile("sxtah %0, %1, %2, ror %3" : "=r" (rd) : "r" (rn), "r" (rm), "I" (ror)); __ASM volatile("sxtah %0, %1, %2, ror %3" : "=r" (rd) : "r" (rn), "r" (rm), "I" (ror));
return rd; return rd;
} }
@ -172,37 +172,37 @@ __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __BFI(uint32_t rd, u
return rd; return rd;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULBB(uint32_t op1, uint32_t op2) { __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULBB(uint32_t op1, uint32_t op2) {
uint32_t result; int32_t result;
__ASM volatile ("smulbb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smulbb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result; return result;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULBT(uint32_t op1, uint32_t op2) { __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULBT(uint32_t op1, uint32_t op2) {
uint32_t result; int32_t result;
__ASM volatile ("smulbt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smulbt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result; return result;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULTB(uint32_t op1, uint32_t op2) { __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULTB(uint32_t op1, uint32_t op2) {
uint32_t result; int32_t result;
__ASM volatile ("smultb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smultb %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result; return result;
} }
__attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __SMULTT(uint32_t op1, uint32_t op2) { __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __SMULTT(uint32_t op1, uint32_t op2) {
uint32_t result; int32_t result;
__ASM volatile ("smultt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); __ASM volatile ("smultt %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
return result; return result;
} }
#undef __SMLALD #undef __SMLALD
__attribute__( ( always_inline ) ) static inline uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) __attribute__( ( always_inline ) ) static inline int64_t __SMLALD (uint32_t op1, uint32_t op2, int64_t acc)
{ {
union llreg_u{ union llreg_u{
uint32_t w32[2]; uint32_t w32[2];
uint64_t w64; int64_t w64;
} llr; } llr;
llr.w64 = acc; llr.w64 = acc;
@ -213,11 +213,11 @@ __attribute__( ( always_inline ) ) static inline uint64_t __SMLALD (uint32_t op1
#undef __SMLALDX #undef __SMLALDX
__attribute__( ( always_inline ) ) static inline uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) __attribute__( ( always_inline ) ) static inline int64_t __SMLALDX (uint32_t op1, uint32_t op2, int64_t acc)
{ {
union llreg_u{ union llreg_u{
uint32_t w32[2]; uint32_t w32[2];
uint64_t w64; int64_t w64;
} llr; } llr;
llr.w64 = acc; llr.w64 = acc;
@ -228,11 +228,11 @@ __attribute__( ( always_inline ) ) static inline uint64_t __SMLALDX (uint32_t op
#undef __SMLSLD #undef __SMLSLD
__attribute__( ( always_inline ) ) static inline uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) __attribute__( ( always_inline ) ) static inline int64_t __SMLSLD (uint32_t op1, uint32_t op2, int64_t acc)
{ {
union llreg_u{ union llreg_u{
uint32_t w32[2]; uint32_t w32[2];
uint64_t w64; int64_t w64;
} llr; } llr;
llr.w64 = acc; llr.w64 = acc;