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CPLD: Use correct bitstream for updating hardware.

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Determine hardware version and use one of two CPLD bitstream files.
This commit is contained in:
Jared Boone 2017-05-31 22:28:07 -07:00
parent 73d62367d1
commit 797e63a590
10 changed files with 15722 additions and 4037 deletions
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22
firmware/application/CMakeLists.txt
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@ -71,8 +71,11 @@ set(USE_FPU no)
# Project, sources and paths # Project, sources and paths
# #
set(CPLD_SVF_PATH ${HARDWARE_PATH}/portapack_h1/cpld/20150901/output_files/portapack_h1_cpld.svf) set(CPLD_20150901_SVF_PATH ${HARDWARE_PATH}/portapack_h1/cpld/20150901/output_files/portapack_h1_cpld.svf)
set(CPLD_DATA_CPP ${CMAKE_CURRENT_BINARY_DIR}/portapack_cpld_data.cpp) set(CPLD_20150901_DATA_CPP ${CMAKE_CURRENT_BINARY_DIR}/portapack_cpld_20150901_data.cpp)
set(CPLD_20170522_SVF_PATH ${HARDWARE_PATH}/portapack_h1/cpld/20170522/output_files/portapack_h1_cpld.svf)
set(CPLD_20170522_DATA_CPP ${CMAKE_CURRENT_BINARY_DIR}/portapack_cpld_20170522_data.cpp)
set(HACKRF_CPLD_DATA_HPP ${CMAKE_CURRENT_BINARY_DIR}/hackrf_cpld_data.hpp) set(HACKRF_CPLD_DATA_HPP ${CMAKE_CURRENT_BINARY_DIR}/hackrf_cpld_data.hpp)
set(HACKRF_CPLD_DATA_CPP ${CMAKE_CURRENT_BINARY_DIR}/hackrf_cpld_data.cpp) set(HACKRF_CPLD_DATA_CPP ${CMAKE_CURRENT_BINARY_DIR}/hackrf_cpld_data.cpp)
@ -194,7 +197,8 @@ set(CPPSRC
${COMMON}/jtag.cpp ${COMMON}/jtag.cpp
${COMMON}/jtag_tap.cpp ${COMMON}/jtag_tap.cpp
cpld_update.cpp cpld_update.cpp
${CPLD_DATA_CPP} ${CPLD_20150901_DATA_CPP}
${CPLD_20170522_DATA_CPP}
${HACKRF_CPLD_DATA_CPP} ${HACKRF_CPLD_DATA_CPP}
) )
@ -310,9 +314,15 @@ include(${RULESPATH}/rules.cmake)
############################################################################## ##############################################################################
add_custom_command( add_custom_command(
OUTPUT ${CPLD_DATA_CPP} OUTPUT ${CPLD_20150901_DATA_CPP}
COMMAND ${EXTRACT_CPLD_DATA} ${CPLD_SVF_PATH} >${CPLD_DATA_CPP} COMMAND ${EXTRACT_CPLD_DATA} ${CPLD_20150901_SVF_PATH} rev_20150901 >${CPLD_20150901_DATA_CPP}
DEPENDS ${EXTRACT_CPLD_DATA} ${CPLD_SVF_PATH} DEPENDS ${EXTRACT_CPLD_DATA} ${CPLD_20150901_SVF_PATH}
)
add_custom_command(
OUTPUT ${CPLD_20170522_DATA_CPP}
COMMAND ${EXTRACT_CPLD_DATA} ${CPLD_20170522_SVF_PATH} rev_20170522 >${CPLD_20170522_DATA_CPP}
DEPENDS ${EXTRACT_CPLD_DATA} ${CPLD_20170522_SVF_PATH}
) )
add_custom_command( add_custom_command(

16
firmware/application/cpld_update.cpp
View File

@ -27,10 +27,12 @@
#include "jtag_target_gpio.hpp" #include "jtag_target_gpio.hpp"
#include "cpld_max5.hpp" #include "cpld_max5.hpp"
#include "cpld_xilinx.hpp" #include "cpld_xilinx.hpp"
#include "portapack_cpld_data.hpp"
#include "hackrf_cpld_data.hpp" #include "hackrf_cpld_data.hpp"
bool cpld_update_if_necessary() { bool cpld_update_if_necessary(
const std::array<uint16_t, 3328>& block_0,
const std::array<uint16_t, 512>& block_1
) {
jtag::GPIOTarget target { jtag::GPIOTarget target {
portapack::gpio_cpld_tck, portapack::gpio_cpld_tck,
portapack::gpio_cpld_tms, portapack::gpio_cpld_tms,
@ -63,17 +65,11 @@ bool cpld_update_if_necessary() {
} }
/* Verify CPLD contents against current bitstream. */ /* Verify CPLD contents against current bitstream. */
auto ok = cpld.verify( auto ok = cpld.verify(block_0, block_1);
portapack::cpld::block_0,
portapack::cpld::block_1
);
/* CPLD verifies incorrectly. Erase and program with current bitstream. */ /* CPLD verifies incorrectly. Erase and program with current bitstream. */
if( !ok ) { if( !ok ) {
ok = cpld.program( ok = cpld.program(block_0, block_1);
portapack::cpld::block_0,
portapack::cpld::block_1
);
} }
/* If programming OK, reset CPLD to user mode. Otherwise leave it in /* If programming OK, reset CPLD to user mode. Otherwise leave it in

8
firmware/application/cpld_update.hpp
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@ -22,7 +22,13 @@
#ifndef __CPLD_UPDATE_H__ #ifndef __CPLD_UPDATE_H__
#define __CPLD_UPDATE_H__ #define __CPLD_UPDATE_H__
bool cpld_update_if_necessary(); #include <cstdint>
#include <array>
bool cpld_update_if_necessary(
const std::array<uint16_t, 3328>& block_0,
const std::array<uint16_t, 512>& block_1
);
bool cpld_hackrf_load_sram(); bool cpld_hackrf_load_sram();
bool cpld_hackrf_verify_eeprom(); bool cpld_hackrf_verify_eeprom();

9
firmware/application/portapack.cpp
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@ -22,6 +22,7 @@
#include "portapack.hpp" #include "portapack.hpp"
#include "portapack_hal.hpp" #include "portapack_hal.hpp"
#include "portapack_dma.hpp" #include "portapack_dma.hpp"
#include "portapack_cpld_data.hpp"
#include "portapack_persistent_memory.hpp" #include "portapack_persistent_memory.hpp"
#include "hackrf_hal.hpp" #include "hackrf_hal.hpp"
@ -174,9 +175,15 @@ void init() {
clock_manager.set_reference_ppb(persistent_memory::correction_ppb()); clock_manager.set_reference_ppb(persistent_memory::correction_ppb());
clock_manager.run_at_full_speed(); clock_manager.run_at_full_speed();
if( !cpld_update_if_necessary() ) { if( portapack_model() == PortaPackModel::R2_20170522 ) {
if( !cpld_update_if_necessary(portapack::cpld::rev_20170522::block_0, portapack::cpld::rev_20170522::block_1) ) {
chSysHalt(); chSysHalt();
} }
} else {
if( !cpld_update_if_necessary(portapack::cpld::rev_20150901::block_0, portapack::cpld::rev_20150901::block_1) ) {
chSysHalt();
}
}
if( !cpld_hackrf_load_sram() ) { if( !cpld_hackrf_load_sram() ) {
chSysHalt(); chSysHalt();

7
firmware/common/portapack_cpld_data.hpp
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@ -28,8 +28,15 @@
namespace portapack { namespace portapack {
namespace cpld { namespace cpld {
namespace rev_20150901 {
extern const std::array<uint16_t, 3328> block_0; extern const std::array<uint16_t, 3328> block_0;
extern const std::array<uint16_t, 512> block_1; extern const std::array<uint16_t, 512> block_1;
} /* namespace rev_20150901 */
namespace rev_20170522 {
extern const std::array<uint16_t, 3328> block_0;
extern const std::array<uint16_t, 512> block_1;
} /* namespace rev_20170522 */
} /* namespace cpld */ } /* namespace cpld */
} /* namespace portapack */ } /* namespace portapack */

11
firmware/tools/extract_cpld_data.py
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@ -25,11 +25,12 @@
import sys import sys
if len(sys.argv) != 2: if len(sys.argv) != 3:
print('Usage: <command> <Altera MAX V CPLD SVF file path>') print('Usage: <command> <Altera MAX V CPLD SVF file path> <revision name>')
sys.exit(-1) sys.exit(-1)
f = open(sys.argv[1], 'r') f = open(sys.argv[1], 'r')
revision_name = sys.argv[2]
calculate_crc = False calculate_crc = False
@ -98,7 +99,8 @@ print("""#include "portapack_cpld_data.hpp"
namespace portapack { namespace portapack {
namespace cpld { namespace cpld {
""") namespace %s {
""" % revision_name)
print('const std::array<uint16_t, %d> block_0 { {' % len(block_0)) print('const std::array<uint16_t, %d> block_0 { {' % len(block_0))
print_block(block_0) print_block(block_0)
@ -111,9 +113,10 @@ print_block(block_1)
print("""} }; print("""} };
} /* namespace %s */
} /* namespace cpld */ } /* namespace cpld */
} /* namespace portapack */ } /* namespace portapack */
""") """ % revision_name)
if calculate_crc: if calculate_crc:
# Apply post-programming modification to make post-programming CRC correct: # Apply post-programming modification to make post-programming CRC correct:

8029
hardware/portapack_h1/cpld/20150901/output_files/portapack_h1_cpld.svf
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File diff suppressed because it is too large Load Diff

2
hardware/portapack_h1/cpld/20150901/portapack_h1_cpld.qsf
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE 5M40ZE64C5
set_global_assignment -name TOP_LEVEL_ENTITY top set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014" set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0 set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85

11651
hardware/portapack_h1/cpld/20170522/output_files/portapack_h1_cpld.svf Normal file
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File diff suppressed because it is too large Load Diff

2
hardware/portapack_h1/cpld/20170522/portapack_h1_cpld.qsf
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@ -41,7 +41,7 @@ set_global_assignment -name DEVICE 5M40ZE64C5
set_global_assignment -name TOP_LEVEL_ENTITY top set_global_assignment -name TOP_LEVEL_ENTITY top
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1 set_global_assignment -name ORIGINAL_QUARTUS_VERSION 13.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014" set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:24:55 APRIL 29, 2014"
set_global_assignment -name LAST_QUARTUS_VERSION 14.1.0 set_global_assignment -name LAST_QUARTUS_VERSION "16.1.2 Lite Edition"
set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files set_global_assignment -name PROJECT_OUTPUT_DIRECTORY output_files
set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0 set_global_assignment -name MIN_CORE_JUNCTION_TEMP 0
set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85 set_global_assignment -name MAX_CORE_JUNCTION_TEMP 85