mirror of
https://github.com/eried/portapack-mayhem.git
synced 2025-07-21 14:09:12 -04:00
Adding support for HackRF One R9, as per https://github.com/sharebrained/portapack-hackrf/pull/187
This commit is contained in:
phil-stumpy
parent
7e20cea6d7
commit
66ba6442b1
35 changed files with 2001 additions and 464 deletions
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@ -41,12 +41,18 @@ constexpr si5351::Inputs si5351_inputs {
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static_assert(si5351_inputs.f_xtal == si5351_xtal_f, "XTAL output frequency wrong");
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static_assert(si5351_inputs.f_clkin_out() == si5351_clkin_f, "CLKIN output frequency wrong");
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constexpr si5351::PLLInputSource::Type si5351_pll_input_sources {
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constexpr si5351::PLLInputSource::Type si5351c_pll_input_sources {
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si5351::PLLInputSource::PLLA_Source_XTAL
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| si5351::PLLInputSource::PLLB_Source_CLKIN
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| si5351::PLLInputSource::CLKIN_Div1
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};
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constexpr si5351::PLLInputSource::Type si5351a_pll_input_sources {
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si5351::PLLInputSource::PLLA_Source_XTAL
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| si5351::PLLInputSource::PLLB_Source_XTAL
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| si5351::PLLInputSource::CLKIN_Div1
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};
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constexpr si5351::PLL si5351_pll_xtal_25m {
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.f_in = si5351_inputs.f_xtal,
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.a = 32,
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@ -61,7 +67,8 @@ constexpr si5351::PLL si5351_pll_clkin_10m {
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.b = 0,
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.c = 1,
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};
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constexpr auto si5351_pll_b_clkin_reg = si5351_pll_clkin_10m.reg(1);
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constexpr auto si5351c_pll_b_clkin_reg = si5351_pll_clkin_10m.reg(1);
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constexpr auto si5351a_pll_a_clkin_reg = si5351_pll_clkin_10m.reg(0);
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static_assert(si5351_pll_xtal_25m.f_vco() == si5351_vco_f, "PLL XTAL frequency wrong");
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static_assert(si5351_pll_xtal_25m.p1() == 3584, "PLL XTAL P1 wrong");
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@ -98,7 +105,7 @@ constexpr si5351::MultisynthFractional si5351_ms_0_8m {
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.c = 1,
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.r_div = 1,
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};
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constexpr auto si5351_ms_0_8m_reg = si5351_ms_0_8m.reg(clock_generator_output_codec);
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constexpr auto si5351c_ms_0_8m_reg = si5351_ms_0_8m.reg(clock_generator_output_og_codec);
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constexpr si5351::MultisynthFractional si5351_ms_group {
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.f_src = si5351_vco_f,
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@ -107,8 +114,17 @@ constexpr si5351::MultisynthFractional si5351_ms_group {
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.c = 1,
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.r_div = 0,
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};
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constexpr auto si5351_ms_1_group_reg = si5351_ms_group.reg(clock_generator_output_cpld);
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constexpr auto si5351_ms_2_group_reg = si5351_ms_group.reg(clock_generator_output_sgpio);
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constexpr auto si5351c_ms_1_group_reg = si5351_ms_group.reg(clock_generator_output_og_cpld);
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constexpr auto si5351c_ms_2_group_reg = si5351_ms_group.reg(clock_generator_output_og_sgpio);
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constexpr si5351::MultisynthFractional si5351_ms_16m {
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.f_src = si5351_vco_f,
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.a = 50,
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.b = 0,
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.c = 1,
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.r_div = 0,
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};
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constexpr auto si5351a_ms_1_sgpio_16m_reg = si5351_ms_16m.reg(clock_generator_output_r9_sgpio);
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constexpr si5351::MultisynthFractional si5351_ms_10m {
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.f_src = si5351_vco_f,
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@ -117,7 +133,8 @@ constexpr si5351::MultisynthFractional si5351_ms_10m {
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.c = 1,
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.r_div = 0,
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};
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constexpr auto si5351_ms_3_10m_reg = si5351_ms_10m.reg(3);
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constexpr auto si5351c_ms_3_10m_reg = si5351_ms_10m.reg(3);
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constexpr auto si5351a_ms_2_mcu_10m_reg = si5351_ms_10m.reg(clock_generator_output_r9_mcu_clkin);
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constexpr si5351::MultisynthFractional si5351_ms_40m {
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.f_src = si5351_vco_f,
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@ -128,10 +145,11 @@ constexpr si5351::MultisynthFractional si5351_ms_40m {
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};
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constexpr auto si5351_ms_rffc5072 = si5351_ms_40m;
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constexpr auto si5351_ms_max2837 = si5351_ms_40m;
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constexpr auto si5351_ms_max283x = si5351_ms_40m;
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constexpr auto si5351_ms_4_reg = si5351_ms_rffc5072.reg(clock_generator_output_first_if);
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constexpr auto si5351_ms_5_reg = si5351_ms_max2837.reg(clock_generator_output_second_if);
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constexpr auto si5351c_ms_4_reg = si5351_ms_rffc5072.reg(clock_generator_output_og_first_if);
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constexpr auto si5351c_ms_5_reg = si5351_ms_max283x.reg(clock_generator_output_og_second_if);
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constexpr auto si5351a_ms_0_if_40m_reg = si5351_ms_40m.reg(clock_generator_output_r9_if);
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static_assert(si5351_ms_10m.f_out() == 10000000, "MS 10MHz f_out wrong");
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static_assert(si5351_ms_10m.p1() == 9728, "MS 10MHz p1 wrong");
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@ -139,14 +157,8 @@ static_assert(si5351_ms_10m.p2() == 0, "MS 10MHz p2 wrong");
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static_assert(si5351_ms_10m.p3() == 1, "MS 10MHz p3 wrong");
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static_assert(si5351_ms_rffc5072.f_out() == rffc5072_reference_f, "RFFC5072 reference f_out wrong");
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// static_assert(si5351_ms_50m.p1() == 2048, "MS 50MHz P1 wrong");
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// static_assert(si5351_ms_50m.p2() == 0, "MS 50MHz P2 wrong");
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// static_assert(si5351_ms_50m.p3() == 1, "MS 50MHz P3 wrong");
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static_assert(si5351_ms_max2837.f_out() == max2837_reference_f, "MAX2837 reference f_out wrong");
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// static_assert(si5351_ms_50m.p1() == 2048, "MS 40MHz P1 wrong");
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// static_assert(si5351_ms_50m.p2() == 0, "MS 40MHz P2 wrong");
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// static_assert(si5351_ms_50m.p3() == 1, "MS 40MHz P3 wrong");
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static_assert(si5351_ms_max283x.f_out() == max283x_reference_f, "MAX283x reference f_out wrong");
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constexpr si5351::MultisynthInteger si5351_ms_int_off {
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.f_src = si5351_vco_f,
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@ -154,40 +166,60 @@ constexpr si5351::MultisynthInteger si5351_ms_int_off {
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.r_div = 0,
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};
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constexpr si5351::MultisynthInteger si5351_ms_int_mcu_clkin {
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constexpr si5351::MultisynthInteger si5351_ms_int_40m {
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.f_src = si5351_vco_f,
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.a = 20,
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.r_div = 0,
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};
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constexpr auto si5351_ms6_7_off_mcu_clkin_reg = si5351::ms6_7_reg(si5351_ms_int_off, si5351_ms_int_mcu_clkin);
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constexpr si5351::MultisynthInteger si5351_ms_int_10m {
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.f_src = si5351_vco_f,
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.a = 80,
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.r_div = 0,
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};
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constexpr auto si5351c_ms_int_mcu_clkin = si5351_ms_int_40m;
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constexpr auto si5351a_ms_int_mcu_clkin = si5351_ms_int_10m;
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constexpr auto si5351c_ms6_7_off_mcu_clkin_reg = si5351::ms6_7_reg(si5351_ms_int_off, si5351c_ms_int_mcu_clkin);
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constexpr auto si5351a_ms6_7_off_reg = si5351::ms6_7_reg(si5351_ms_int_off, si5351_ms_int_off);
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static_assert(si5351_ms_int_off.f_out() == 3137254, "MS int off f_out wrong");
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static_assert(si5351_ms_int_off.p1() == 255, "MS int off P1 wrong");
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static_assert(si5351_ms_int_mcu_clkin.f_out() == mcu_clkin_f, "MS int MCU CLKIN f_out wrong");
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// static_assert(si5351_ms_int_mcu_clkin.p1() == 20, "MS int MCU CLKIN P1 wrong");
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static_assert(si5351c_ms_int_mcu_clkin.f_out() == mcu_clkin_og_f, "MS int MCU CLKIN OG f_out wrong");
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static_assert(si5351a_ms_int_mcu_clkin.f_out() == mcu_clkin_r9_f, "MS int MCU CLKIN r9 f_out wrong");
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using namespace si5351;
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static constexpr ClockControl::MultiSynthSource get_reference_clock_generator_pll(const ClockManager::ReferenceSource reference_source) {
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static constexpr ClockControl::MultiSynthSource get_si5351c_reference_clock_generator_pll(const ClockManager::ReferenceSource reference_source) {
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return (reference_source == ClockManager::ReferenceSource::Xtal)
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? ClockControl::MultiSynthSource::PLLA
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: ClockControl::MultiSynthSource::PLLB
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;
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}
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constexpr ClockControls si5351_clock_control_common { {
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{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Invert, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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constexpr ClockControls si5351c_clock_control_common { {
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{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Invert, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Group, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Invert, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, get_si5351c_reference_clock_generator_pll(ClockManager::ReferenceSource::Xtal), ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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} };
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constexpr ClockControls si5351a_clock_control_common { {
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{ ClockControl::ClockCurrentDrive::_6mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_4mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Fractional, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_8mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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{ ClockControl::ClockCurrentDrive::_2mA, ClockControl::ClockSource::MS_Self, ClockControl::ClockInvert::Normal, ClockControl::MultiSynthSource::PLLA, ClockControl::MultiSynthMode::Integer, ClockControl::ClockPowerDown::Power_Off },
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} };
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ClockManager::Reference ClockManager::get_reference() const {
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return reference;
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}
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@ -212,11 +244,25 @@ void ClockManager::init_clock_generator() {
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clock_generator.reset();
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clock_generator.set_crystal_internal_load_capacitance(CrystalInternalLoadCapacitance::XTAL_CL_8pF);
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clock_generator.enable_fanout();
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clock_generator.set_pll_input_sources(si5351_pll_input_sources);
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clock_generator.set_pll_input_sources(hackrf_r9
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? si5351a_pll_input_sources
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: si5351c_pll_input_sources);
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auto si5351_clock_control_common = hackrf_r9
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? si5351a_clock_control_common
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: si5351c_clock_control_common;
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auto clock_generator_output_mcu_clkin = hackrf_r9
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? clock_generator_output_r9_mcu_clkin
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: clock_generator_output_og_mcu_clkin;
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clock_generator.set_clock_control(
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clock_generator_output_mcu_clkin,
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si5351_clock_control_common[clock_generator_output_mcu_clkin].clk_src(ClockControl::ClockSource::CLKIN).clk_pdn(ClockControl::ClockPowerDown::Power_On)
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si5351_clock_control_common[clock_generator_output_mcu_clkin]
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.clk_src(hackrf_r9
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? ClockControl::ClockSource::Xtal
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: ClockControl::ClockSource::CLKIN)
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.clk_pdn(ClockControl::ClockPowerDown::Power_On)
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);
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clock_generator.enable_output(clock_generator_output_mcu_clkin);
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@ -224,7 +270,10 @@ void ClockManager::init_clock_generator() {
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clock_generator.disable_output(clock_generator_output_mcu_clkin);
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const auto ref_pll = get_reference_clock_generator_pll(reference.source);
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const auto ref_pll = hackrf_r9
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? ClockControl::MultiSynthSource::PLLA
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: get_si5351c_reference_clock_generator_pll(reference.source);
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const ClockControls si5351_clock_control = ClockControls { {
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si5351_clock_control_common[0].ms_src(ref_pll),
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si5351_clock_control_common[1].ms_src(ref_pll),
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@ -237,21 +286,35 @@ void ClockManager::init_clock_generator() {
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} };
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clock_generator.set_clock_control(si5351_clock_control);
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clock_generator.write(si5351_pll_a_xtal_reg);
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clock_generator.write(si5351_pll_b_clkin_reg);
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clock_generator.write(si5351_ms_0_8m_reg);
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clock_generator.write(si5351_ms_1_group_reg);
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clock_generator.write(si5351_ms_2_group_reg);
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clock_generator.write(si5351_ms_3_10m_reg);
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clock_generator.write(si5351_ms_4_reg);
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clock_generator.write(si5351_ms_5_reg);
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clock_generator.write(si5351_ms6_7_off_mcu_clkin_reg);
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if (hackrf_r9) {
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const PLLReg pll_reg = (reference.source == ReferenceSource::Xtal)
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? si5351_pll_a_xtal_reg
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: si5351a_pll_a_clkin_reg;
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clock_generator.write(pll_reg);
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clock_generator.write(si5351a_ms_0_if_40m_reg);
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clock_generator.write(si5351a_ms_1_sgpio_16m_reg);
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clock_generator.write(si5351a_ms_2_mcu_10m_reg);
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clock_generator.write(si5351a_ms6_7_off_reg);
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} else {
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clock_generator.write(si5351_pll_a_xtal_reg);
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clock_generator.write(si5351c_pll_b_clkin_reg);
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clock_generator.write(si5351c_ms_0_8m_reg);
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clock_generator.write(si5351c_ms_1_group_reg);
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clock_generator.write(si5351c_ms_2_group_reg);
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clock_generator.write(si5351c_ms_3_10m_reg);
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clock_generator.write(si5351c_ms_4_reg);
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clock_generator.write(si5351c_ms_5_reg);
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clock_generator.write(si5351c_ms6_7_off_mcu_clkin_reg);
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}
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clock_generator.reset_plls();
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// Wait for both PLLs to lock.
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// TODO: Disable the unused PLL?
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const uint8_t device_status_mask = (ref_pll == ClockControl::MultiSynthSource::PLLB) ? 0x40 : 0x20;
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// Wait for PLL(s) to lock.
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uint8_t device_status_mask = hackrf_r9
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? 0x20
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: (ref_pll == ClockControl::MultiSynthSource::PLLB)
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? 0x40
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: 0x20;
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while((clock_generator.device_status() & device_status_mask) != 0);
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clock_generator.set_clock_control(
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@ -268,12 +331,18 @@ uint32_t ClockManager::measure_gp_clkin_frequency() {
|
|||
return get_frequency_monitor_measurement_in_hertz();
|
||||
}
|
||||
|
||||
bool ClockManager::loss_of_signal() {
|
||||
return hackrf_r9
|
||||
? clock_generator.plla_loss_of_signal()
|
||||
: clock_generator.clkin_loss_of_signal();
|
||||
}
|
||||
|
||||
ClockManager::ReferenceSource ClockManager::detect_reference_source() {
|
||||
if( clock_generator.clkin_loss_of_signal() ) {
|
||||
if(loss_of_signal()) {
|
||||
// No external reference. Turn on PortaPack reference (if present).
|
||||
portapack_tcxo_enable();
|
||||
|
||||
if( clock_generator.clkin_loss_of_signal() ) {
|
||||
if(loss_of_signal()) {
|
||||
// No PortaPack reference was detected. Choose the HackRF crystal as the reference.
|
||||
return ReferenceSource::Xtal;
|
||||
} else {
|
||||
|
|
@ -285,6 +354,11 @@ ClockManager::ReferenceSource ClockManager::detect_reference_source() {
|
|||
}
|
||||
|
||||
ClockManager::Reference ClockManager::choose_reference() {
|
||||
if (hackrf_r9) {
|
||||
gpio_r9_clkin_en.write(1);
|
||||
volatile uint32_t delay = 240000 + 24000;
|
||||
while(delay--);
|
||||
}
|
||||
const auto detected_reference = detect_reference_source();
|
||||
|
||||
if( (detected_reference == ReferenceSource::External) ||
|
||||
|
|
@ -296,8 +370,12 @@ ClockManager::Reference ClockManager::choose_reference() {
|
|||
}
|
||||
}
|
||||
|
||||
if (hackrf_r9) {
|
||||
gpio_r9_clkin_en.write(0);
|
||||
}
|
||||
|
||||
portapack_tcxo_disable();
|
||||
return { ReferenceSource::Xtal, 10000000 };
|
||||
return { ReferenceSource::Xtal, 25000000 };
|
||||
}
|
||||
|
||||
void ClockManager::shutdown() {
|
||||
|
|
@ -305,18 +383,26 @@ void ClockManager::shutdown() {
|
|||
}
|
||||
|
||||
void ClockManager::enable_codec_clocks() {
|
||||
clock_generator.enable_clock(clock_generator_output_codec);
|
||||
clock_generator.enable_clock(clock_generator_output_cpld);
|
||||
clock_generator.enable_clock(clock_generator_output_sgpio);
|
||||
if (hackrf_r9) {
|
||||
clock_generator.enable_clock(clock_generator_output_r9_sgpio);
|
||||
} else {
|
||||
clock_generator.enable_clock(clock_generator_output_og_codec);
|
||||
clock_generator.enable_clock(clock_generator_output_og_cpld);
|
||||
clock_generator.enable_clock(clock_generator_output_og_sgpio);
|
||||
}
|
||||
/* Turn on all outputs at the same time. This probably doesn't ensure
|
||||
* their phase relationships. For example, clocks that output frequencies
|
||||
* in a 2:1 relationship may start with the slower clock high or low?
|
||||
*/
|
||||
clock_generator.enable_output_mask(
|
||||
(1U << clock_generator_output_codec)
|
||||
| (1U << clock_generator_output_cpld)
|
||||
| (1U << clock_generator_output_sgpio)
|
||||
);
|
||||
if (hackrf_r9) {
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_r9_sgpio);
|
||||
} else {
|
||||
clock_generator.enable_output_mask(
|
||||
(1U << clock_generator_output_og_codec)
|
||||
| (1U << clock_generator_output_og_cpld)
|
||||
| (1U << clock_generator_output_og_sgpio)
|
||||
);
|
||||
}
|
||||
}
|
||||
|
||||
void ClockManager::disable_codec_clocks() {
|
||||
|
|
@ -324,34 +410,45 @@ void ClockManager::disable_codec_clocks() {
|
|||
* be enabled for the output to come to rest at the state specified by
|
||||
* CLKx_DISABLE_STATE.
|
||||
*/
|
||||
clock_generator.disable_output_mask(
|
||||
(1U << clock_generator_output_codec)
|
||||
| (1U << clock_generator_output_cpld)
|
||||
| (1U << clock_generator_output_sgpio)
|
||||
);
|
||||
clock_generator.disable_clock(clock_generator_output_codec);
|
||||
clock_generator.disable_clock(clock_generator_output_cpld);
|
||||
clock_generator.disable_clock(clock_generator_output_sgpio);
|
||||
if (hackrf_r9) {
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_r9_sgpio);
|
||||
clock_generator.disable_clock(clock_generator_output_r9_sgpio);
|
||||
} else {
|
||||
clock_generator.disable_output_mask(
|
||||
(1U << clock_generator_output_og_codec)
|
||||
| (1U << clock_generator_output_og_cpld)
|
||||
| (1U << clock_generator_output_og_sgpio)
|
||||
);
|
||||
clock_generator.disable_clock(clock_generator_output_og_codec);
|
||||
clock_generator.disable_clock(clock_generator_output_og_cpld);
|
||||
clock_generator.disable_clock(clock_generator_output_og_sgpio);
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
void ClockManager::enable_first_if_clock() {
|
||||
clock_generator.enable_clock(clock_generator_output_first_if);
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_first_if);
|
||||
void ClockManager::enable_if_clocks() {
|
||||
if (hackrf_r9) {
|
||||
clock_generator.enable_clock(clock_generator_output_r9_if);
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_r9_if);
|
||||
} else {
|
||||
clock_generator.enable_clock(clock_generator_output_og_first_if);
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_og_first_if);
|
||||
clock_generator.enable_clock(clock_generator_output_og_second_if);
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_og_second_if);
|
||||
|
||||
}
|
||||
}
|
||||
|
||||
void ClockManager::disable_first_if_clock() {
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_first_if);
|
||||
clock_generator.disable_clock(clock_generator_output_first_if);
|
||||
}
|
||||
|
||||
void ClockManager::enable_second_if_clock() {
|
||||
clock_generator.enable_clock(clock_generator_output_second_if);
|
||||
clock_generator.enable_output_mask(1U << clock_generator_output_second_if);
|
||||
}
|
||||
|
||||
void ClockManager::disable_second_if_clock() {
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_second_if);
|
||||
clock_generator.disable_clock(clock_generator_output_second_if);
|
||||
void ClockManager::disable_if_clocks() {
|
||||
if (hackrf_r9) {
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_r9_if);
|
||||
clock_generator.disable_clock(clock_generator_output_r9_if);
|
||||
} else {
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_og_first_if);
|
||||
clock_generator.disable_clock(clock_generator_output_og_first_if);
|
||||
clock_generator.disable_output_mask(1U << clock_generator_output_og_second_if);
|
||||
clock_generator.disable_clock(clock_generator_output_og_second_if);
|
||||
}
|
||||
}
|
||||
|
||||
void ClockManager::set_sampling_frequency(const uint32_t frequency) {
|
||||
|
|
@ -360,14 +457,21 @@ void ClockManager::set_sampling_frequency(const uint32_t frequency) {
|
|||
* necessary to change the MS0 synth frequency, and ensure the output
|
||||
* is divided by two.
|
||||
*/
|
||||
clock_generator.set_ms_frequency(clock_generator_output_codec, frequency * 2, si5351_vco_f, 1);
|
||||
if (hackrf_r9) {
|
||||
clock_generator.set_ms_frequency(clock_generator_output_r9_sgpio, frequency * 2, si5351_vco_f, 0);
|
||||
} else {
|
||||
clock_generator.set_ms_frequency(clock_generator_output_og_codec, frequency * 2, si5351_vco_f, 1);
|
||||
}
|
||||
}
|
||||
|
||||
void ClockManager::set_reference_ppb(const int32_t ppb) {
|
||||
/* NOTE: This adjustment only affects PLLA, which is derived from the 25MHz crystal.
|
||||
* It is assumed an external clock coming in to PLLB is sufficiently accurate as to not need adjustment.
|
||||
/* NOTE: This adjustment only affects PLLA when it is derived from the 25MHz crystal.
|
||||
* It is assumed an external clock coming in to CLKIN/PLLB is sufficiently accurate as to not need adjustment.
|
||||
* TODO: Revisit the above policy. It may be good to allow adjustment of the external reference too.
|
||||
*/
|
||||
if (hackrf_r9 && reference.source != ReferenceSource::Xtal) {
|
||||
return;
|
||||
}
|
||||
constexpr uint32_t pll_multiplier = si5351_pll_xtal_25m.a;
|
||||
constexpr uint32_t denominator = 1000000 / pll_multiplier;
|
||||
const uint32_t new_a = (ppb >= 0) ? pll_multiplier : (pll_multiplier - 1);
|
||||
|
|
@ -425,11 +529,13 @@ void ClockManager::start_audio_pll() {
|
|||
|
||||
/* For 40MHz clock source, 48kHz audio rate, 256Fs MCLK:
|
||||
* Fout=12.288MHz, Fcco=491.52MHz
|
||||
* PSEL=20, NSEL=125, MSEL=768
|
||||
* OG: PSEL=20, NSEL=125, MSEL=768
|
||||
* PDEC=31, NDEC=45, MDEC=30542
|
||||
* r9: PSEL=20, NSEL=125, MSEL=3072
|
||||
* PDEC=31, NDEC=45, MDEC=8308
|
||||
*/
|
||||
cgu::pll0audio::mdiv({
|
||||
.mdec = 30542,
|
||||
.mdec = hackrf_r9 ? 8308UL : 30542UL,
|
||||
});
|
||||
cgu::pll0audio::np_div({
|
||||
.pdec = 31,
|
||||
|
|
@ -467,18 +573,25 @@ void ClockManager::stop_audio_pll() {
|
|||
|
||||
void ClockManager::enable_clock_output(bool enable) {
|
||||
if(enable) {
|
||||
clock_generator.enable_output(clock_generator_output_clkout);
|
||||
clock_generator.enable_output(clock_generator_output_og_clkout);
|
||||
if(portapack::persistent_memory::clkout_freq() < 1000) {
|
||||
clock_generator.set_ms_frequency(clock_generator_output_clkout, portapack::persistent_memory::clkout_freq() * 128000, si5351_vco_f, 7);
|
||||
clock_generator.set_ms_frequency(clock_generator_output_og_clkout, portapack::persistent_memory::clkout_freq() * 128000, si5351_vco_f, 7);
|
||||
} else {
|
||||
clock_generator.set_ms_frequency(clock_generator_output_clkout, portapack::persistent_memory::clkout_freq() * 1000, si5351_vco_f, 0);
|
||||
clock_generator.set_ms_frequency(clock_generator_output_og_clkout, portapack::persistent_memory::clkout_freq() * 1000, si5351_vco_f, 0);
|
||||
}
|
||||
} else {
|
||||
clock_generator.disable_output(clock_generator_output_clkout);
|
||||
clock_generator.disable_output(clock_generator_output_og_clkout);
|
||||
}
|
||||
|
||||
auto si5351_clock_control_common = hackrf_r9
|
||||
? si5351a_clock_control_common
|
||||
: si5351c_clock_control_common;
|
||||
const auto ref_pll = hackrf_r9
|
||||
? ClockControl::MultiSynthSource::PLLA
|
||||
: get_si5351c_reference_clock_generator_pll(reference.source);
|
||||
|
||||
if(enable)
|
||||
clock_generator.set_clock_control(clock_generator_output_clkout, si5351_clock_control_common[clock_generator_output_clkout].ms_src(get_reference_clock_generator_pll(reference.source)).clk_pdn(ClockControl::ClockPowerDown::Power_On));
|
||||
clock_generator.set_clock_control(clock_generator_output_og_clkout, si5351_clock_control_common[clock_generator_output_og_clkout].ms_src(ref_pll).clk_pdn(ClockControl::ClockPowerDown::Power_On));
|
||||
else
|
||||
clock_generator.set_clock_control(clock_generator_output_clkout, ClockControl::power_off());
|
||||
clock_generator.set_clock_control(clock_generator_output_og_clkout, ClockControl::power_off());
|
||||
}
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue