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POCSAG Processor Rewrite (#1437)

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* WIP Refactoring
* WordExtractor building
* Fix buffer sizes and squelch execute
* Move impls to cpp file
* Baud indicator
* WIP new bit extractor
* New approach for bit extraction.
* Code fit and finish
* Fix case on button
* Cleanup
* Adjust rate miss threshold
* Fix count bits error calculation.
This commit is contained in:
Kyle Reed 2023-09-08 10:41:09 -07:00 • committed by GitHub
parent 9525738118
commit 31e8019642
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GPG key ID: 4AEE18F83AFDEB23
13 changed files with 648 additions and 534 deletions
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46
firmware/test/baseband/dsp_fft_test.cpp
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@ -50,8 +50,46 @@ TEST_CASE("ifft successfully calculates dc on zero frequency") {
for (uint32_t i = 0; i < fft_width; i++)
CHECK(v[i].imag() == 0);
free(v);
free(tmp);
delete[] v;
delete[] tmp;
}
TEST_CASE("ifft successfully calculates sine of quarter the sample rate") {
uint32_t fft_width = 8;
complex16_t* v = new complex16_t[fft_width];
complex16_t* tmp = new complex16_t[fft_width];
v[0] = {0, 0};
v[1] = {0, 0};
v[2] = {1024, 0}; // sample rate /4 bin
v[3] = {0, 0};
v[4] = {0, 0};
v[5] = {0, 0};
v[6] = {0, 0};
v[7] = {0, 0};
ifft<complex16_t>(v, fft_width, tmp);
CHECK(v[0].real() == 1024);
CHECK(v[1].real() == 0);
CHECK(v[2].real() == -1024);
CHECK(v[3].real() == 0);
CHECK(v[4].real() == 1024);
CHECK(v[5].real() == 0);
CHECK(v[6].real() == -1024);
CHECK(v[7].real() == 0);
CHECK(v[0].imag() == 0);
CHECK(v[1].imag() == 1024);
CHECK(v[2].imag() == 0);
CHECK(v[3].imag() == -1024);
CHECK(v[4].imag() == 0);
CHECK(v[5].imag() == 1024);
CHECK(v[6].imag() == 0);
CHECK(v[7].imag() == -1024);
delete[] v;
delete[] tmp;
}
TEST_CASE("ifft successfully calculates pure sine of half the sample rate") {
@ -82,6 +120,6 @@ TEST_CASE("ifft successfully calculates pure sine of half the sample rate") {
for (uint32_t i = 0; i < fft_width; i++)
CHECK(v[i].imag() == 0);
free(v);
free(tmp);
delete[] v;
delete[] tmp;
}