mirror of
https://github.com/eried/portapack-mayhem.git
synced 2025-08-13 17:05:37 -04:00
Formatted code (#1007)
* Updated style * Updated files * fixed new line * Updated spacing * File fix WIP * Updated to clang 13 * updated comment style * Removed old comment code
This commit is contained in:
jLynx
GitHub
parent
7aca7ce74d
commit
033c4e9a5b
599 changed files with 70746 additions and 66896 deletions
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@ -29,7 +29,6 @@
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#include "hackrf_gpio.hpp"
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using namespace hackrf::one;
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#include "clock_manager.hpp"
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#include "event_m0.hpp"
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@ -48,313 +47,309 @@ using asahi_kasei::ak4951::AK4951;
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#include "optional.hpp"
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#include "irq_controls.hpp"
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#include "file.hpp"
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#include "file.hpp"
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#include "sd_card.hpp"
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#include "string_format.hpp"
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namespace portapack {
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portapack::IO io {
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portapack::gpio_dir,
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portapack::gpio_lcd_rdx,
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portapack::gpio_lcd_wrx,
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portapack::gpio_io_stbx,
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portapack::gpio_addr,
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portapack::gpio_lcd_te,
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portapack::gpio_dfu,
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portapack::IO io{
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portapack::gpio_dir,
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portapack::gpio_lcd_rdx,
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portapack::gpio_lcd_wrx,
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portapack::gpio_io_stbx,
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portapack::gpio_addr,
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portapack::gpio_lcd_te,
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portapack::gpio_dfu,
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};
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portapack::BacklightCAT4004 backlight_cat4004;
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portapack::BacklightOnOff backlight_on_off;
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portapack::BacklightOnOff backlight_on_off;
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lcd::ILI9341 display;
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I2C i2c0(&I2CD0);
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SPI ssp1(&SPID2);
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si5351::Si5351 clock_generator {
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i2c0, hackrf::one::si5351_i2c_address
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};
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si5351::Si5351 clock_generator{
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i2c0, hackrf::one::si5351_i2c_address};
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ClockManager clock_manager {
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i2c0, clock_generator
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};
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ClockManager clock_manager{
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i2c0, clock_generator};
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WM8731 audio_codec_wm8731 { i2c0, 0x1a };
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AK4951 audio_codec_ak4951 { i2c0, 0x12 };
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WM8731 audio_codec_wm8731{i2c0, 0x1a};
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AK4951 audio_codec_ak4951{i2c0, 0x12};
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ReceiverModel receiver_model;
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TransmitterModel transmitter_model;
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TemperatureLogger temperature_logger;
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bool antenna_bias { false };
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uint32_t bl_tick_counter { 0 };
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bool antenna_bias{false};
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uint32_t bl_tick_counter{0};
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void set_antenna_bias(const bool v) {
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antenna_bias = v;
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antenna_bias = v;
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}
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bool get_antenna_bias() {
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return antenna_bias;
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return antenna_bias;
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}
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bool speaker_mode { false };
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void set_speaker_mode(const bool v) {
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speaker_mode = v;
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if (speaker_mode)
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audio::output::speaker_unmute();
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else
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audio::output::speaker_mute();
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}
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bool speaker_mode{false};
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void set_speaker_mode(const bool v) {
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speaker_mode = v;
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if (speaker_mode)
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audio::output::speaker_unmute();
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else
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audio::output::speaker_mute();
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}
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static constexpr uint32_t systick_count(const uint32_t clock_source_f) {
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return clock_source_f / CH_FREQUENCY;
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return clock_source_f / CH_FREQUENCY;
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}
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static constexpr uint32_t systick_load(const uint32_t clock_source_f) {
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return systick_count(clock_source_f) - 1;
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return systick_count(clock_source_f) - 1;
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}
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constexpr uint32_t i2c0_bus_f = 400000;
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constexpr uint32_t i2c0_high_period_ns = 900;
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constexpr uint32_t i2c0_bus_f = 400000;
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constexpr uint32_t i2c0_high_period_ns = 900;
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typedef struct {
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uint32_t clock_f;
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uint32_t systick_count;
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uint32_t idivb;
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uint32_t idivc;
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uint32_t clock_f;
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uint32_t systick_count;
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uint32_t idivb;
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uint32_t idivc;
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} clock_config_t;
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static constexpr uint32_t idiv_config(const cgu::CLK_SEL clk_sel, const uint32_t idiv) {
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return cgu::IDIV_CTRL { 0, idiv-1, 1, clk_sel };
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return cgu::IDIV_CTRL{0, idiv - 1, 1, clk_sel};
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}
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constexpr clock_config_t clock_config_irc {
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12000000, systick_load(12000000),
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idiv_config(cgu::CLK_SEL::IRC, 1),
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idiv_config(cgu::CLK_SEL::IRC, 1),
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constexpr clock_config_t clock_config_irc{
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12000000,
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systick_load(12000000),
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idiv_config(cgu::CLK_SEL::IRC, 1),
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idiv_config(cgu::CLK_SEL::IRC, 1),
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};
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constexpr clock_config_t clock_config_pll1_boot {
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96000000, systick_load(96000000),
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idiv_config(cgu::CLK_SEL::PLL1, 9),
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idiv_config(cgu::CLK_SEL::PLL1, 3),
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constexpr clock_config_t clock_config_pll1_boot{
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96000000,
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systick_load(96000000),
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idiv_config(cgu::CLK_SEL::PLL1, 9),
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idiv_config(cgu::CLK_SEL::PLL1, 3),
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};
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constexpr clock_config_t clock_config_pll1_step {
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100000000, systick_load(100000000),
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idiv_config(cgu::CLK_SEL::PLL1, 1),
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idiv_config(cgu::CLK_SEL::PLL1, 1),
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constexpr clock_config_t clock_config_pll1_step{
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100000000,
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systick_load(100000000),
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idiv_config(cgu::CLK_SEL::PLL1, 1),
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idiv_config(cgu::CLK_SEL::PLL1, 1),
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};
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constexpr clock_config_t clock_config_pll1 {
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200000000, systick_load(200000000),
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idiv_config(cgu::CLK_SEL::PLL1, 2),
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idiv_config(cgu::CLK_SEL::PLL1, 1),
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constexpr clock_config_t clock_config_pll1{
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200000000,
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systick_load(200000000),
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idiv_config(cgu::CLK_SEL::PLL1, 2),
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idiv_config(cgu::CLK_SEL::PLL1, 1),
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};
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constexpr I2CClockConfig i2c_clock_config_400k_boot_clock {
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.clock_source_f = clock_config_pll1_boot.clock_f,
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.bus_f = i2c0_bus_f,
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.high_period_ns = i2c0_high_period_ns,
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constexpr I2CClockConfig i2c_clock_config_400k_boot_clock{
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.clock_source_f = clock_config_pll1_boot.clock_f,
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.bus_f = i2c0_bus_f,
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.high_period_ns = i2c0_high_period_ns,
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};
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constexpr I2CClockConfig i2c_clock_config_400k_fast_clock {
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.clock_source_f = clock_config_pll1.clock_f,
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.bus_f = i2c0_bus_f,
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.high_period_ns = i2c0_high_period_ns,
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constexpr I2CClockConfig i2c_clock_config_400k_fast_clock{
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.clock_source_f = clock_config_pll1.clock_f,
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.bus_f = i2c0_bus_f,
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.high_period_ns = i2c0_high_period_ns,
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};
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constexpr I2CConfig i2c_config_boot_clock {
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.high_count = i2c_clock_config_400k_boot_clock.i2c_high_count(),
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.low_count = i2c_clock_config_400k_boot_clock.i2c_low_count(),
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constexpr I2CConfig i2c_config_boot_clock{
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.high_count = i2c_clock_config_400k_boot_clock.i2c_high_count(),
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.low_count = i2c_clock_config_400k_boot_clock.i2c_low_count(),
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};
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constexpr I2CConfig i2c_config_fast_clock {
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.high_count = i2c_clock_config_400k_fast_clock.i2c_high_count(),
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.low_count = i2c_clock_config_400k_fast_clock.i2c_low_count(),
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constexpr I2CConfig i2c_config_fast_clock{
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.high_count = i2c_clock_config_400k_fast_clock.i2c_high_count(),
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.low_count = i2c_clock_config_400k_fast_clock.i2c_low_count(),
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};
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enum class PortaPackModel {
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R1_20150901,
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R2_20170522,
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R1_20150901,
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R2_20170522,
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};
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static bool save_config(int8_t value){
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persistent_memory::set_config_cpld(value);
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if(sd_card::status() == sd_card::Status::Mounted){
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make_new_directory("/hardware");
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File file;
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auto sucess = file.create("/hardware/settings.txt");
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if(!sucess.is_valid()) {
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file.write_line(to_string_dec_uint(value));
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}
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}
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return true;
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static bool save_config(int8_t value) {
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persistent_memory::set_config_cpld(value);
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if (sd_card::status() == sd_card::Status::Mounted) {
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make_new_directory("/hardware");
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File file;
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auto sucess = file.create("/hardware/settings.txt");
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if (!sucess.is_valid()) {
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file.write_line(to_string_dec_uint(value));
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}
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}
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return true;
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}
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int read_file(std::string name) {
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std::string return_string = "";
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File file;
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auto success = file.open(name);
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std::string return_string = "";
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File file;
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auto success = file.open(name);
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if(!success.is_valid()) {
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char one_char[1];
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for(size_t pointer = 0; pointer < file.size() ; pointer++) {
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file.seek(pointer);
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file.read(one_char, 1);
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return_string += one_char[0];
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}
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return std::stoi(return_string);
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}
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return -1;
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if (!success.is_valid()) {
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char one_char[1];
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for (size_t pointer = 0; pointer < file.size(); pointer++) {
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file.seek(pointer);
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file.read(one_char, 1);
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return_string += one_char[0];
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}
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return std::stoi(return_string);
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}
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return -1;
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}
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static int load_config(){
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static Optional<int> config_value;
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if(!config_value.is_valid()){
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int8_t value = portapack::persistent_memory::config_cpld();
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if((value <= 0 || value >= 5) && sd_card::status() == sd_card::Status::Mounted){
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int data = read_file("/hardware/settings.txt");
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if(data != -1) {
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config_value = data;
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}
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} else {
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config_value = value;
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}
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}
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return config_value.value();
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static int load_config() {
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static Optional<int> config_value;
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if (!config_value.is_valid()) {
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int8_t value = portapack::persistent_memory::config_cpld();
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if ((value <= 0 || value >= 5) && sd_card::status() == sd_card::Status::Mounted) {
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int data = read_file("/hardware/settings.txt");
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if (data != -1) {
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config_value = data;
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}
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} else {
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config_value = value;
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}
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}
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return config_value.value();
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}
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static PortaPackModel portapack_model() {
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static Optional<PortaPackModel> model;
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static Optional<PortaPackModel> model;
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if( !model.is_valid() ) {
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const auto switches_state = get_switches_state();
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if (switches_state[(size_t)ui::KeyEvent::Up]){
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save_config(1);
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// model = PortaPackModel::R2_20170522; // Commented these out as they should be set down below anyway
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}
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else if (switches_state[(size_t)ui::KeyEvent::Down]){
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save_config(2);
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// model = PortaPackModel::R1_20150901;
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}
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else if (switches_state[(size_t)ui::KeyEvent::Left]){
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save_config(3);
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// model = PortaPackModel::R1_20150901;
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}
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else if (switches_state[(size_t)ui::KeyEvent::Right]){
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save_config(4);
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// model = PortaPackModel::R2_20170522;
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}
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else if (switches_state[(size_t)ui::KeyEvent::Select]){
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save_config(0);
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}
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if (!model.is_valid()) {
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const auto switches_state = get_switches_state();
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if (switches_state[(size_t)ui::KeyEvent::Up]) {
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save_config(1);
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// model = PortaPackModel::R2_20170522; // Commented these out as they should be set down below anyway
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} else if (switches_state[(size_t)ui::KeyEvent::Down]) {
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save_config(2);
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// model = PortaPackModel::R1_20150901;
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} else if (switches_state[(size_t)ui::KeyEvent::Left]) {
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save_config(3);
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// model = PortaPackModel::R1_20150901;
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} else if (switches_state[(size_t)ui::KeyEvent::Right]) {
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save_config(4);
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// model = PortaPackModel::R2_20170522;
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} else if (switches_state[(size_t)ui::KeyEvent::Select]) {
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save_config(0);
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}
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if (load_config() == 1) {
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model = PortaPackModel::R2_20170522;
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} else if (load_config() == 2) {
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model = PortaPackModel::R1_20150901;
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} else if (load_config() == 3) {
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model = PortaPackModel::R1_20150901;
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} else if (load_config() == 4) {
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model = PortaPackModel::R2_20170522;
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} else {
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if( audio_codec_wm8731.detected() ) {
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model = PortaPackModel::R1_20150901; // H1R1
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} else {
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model = PortaPackModel::R2_20170522; // H1R2, H2, H2+
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}
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}
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}
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if (load_config() == 1) {
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model = PortaPackModel::R2_20170522;
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} else if (load_config() == 2) {
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model = PortaPackModel::R1_20150901;
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} else if (load_config() == 3) {
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model = PortaPackModel::R1_20150901;
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} else if (load_config() == 4) {
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model = PortaPackModel::R2_20170522;
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} else {
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if (audio_codec_wm8731.detected()) {
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model = PortaPackModel::R1_20150901; // H1R1
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} else {
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model = PortaPackModel::R2_20170522; // H1R2, H2, H2+
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}
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}
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}
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return model.value();
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return model.value();
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}
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//audio_codec_wm8731 = H1R1 & H2+
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//audio_codec_ak4951 = H1R2
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// audio_codec_wm8731 = H1R1 & H2+
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// audio_codec_ak4951 = H1R2
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static audio::Codec* portapack_audio_codec() {
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/* I2C ready OK, Automatic recognition of audio chip */
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return (audio_codec_wm8731.detected())
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? static_cast<audio::Codec*>(&audio_codec_wm8731)
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: static_cast<audio::Codec*>(&audio_codec_ak4951)
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;
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/* I2C ready OK, Automatic recognition of audio chip */
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return (audio_codec_wm8731.detected())
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? static_cast<audio::Codec*>(&audio_codec_wm8731)
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: static_cast<audio::Codec*>(&audio_codec_ak4951);
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}
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static const portapack::cpld::Config& portapack_cpld_config() {
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return (portapack_model() == PortaPackModel::R2_20170522)
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? portapack::cpld::rev_20170522::config
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: portapack::cpld::rev_20150901::config;
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return (portapack_model() == PortaPackModel::R2_20170522)
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? portapack::cpld::rev_20170522::config
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: portapack::cpld::rev_20150901::config;
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}
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Backlight* backlight() {
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return (portapack_model() == PortaPackModel::R2_20170522)
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? static_cast<portapack::Backlight*>(&backlight_cat4004) // R2_20170522
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: static_cast<portapack::Backlight*>(&backlight_on_off); // R1_20150901
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return (portapack_model() == PortaPackModel::R2_20170522)
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? static_cast<portapack::Backlight*>(&backlight_cat4004) // R2_20170522
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: static_cast<portapack::Backlight*>(&backlight_on_off); // R1_20150901
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}
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#define ARRAY_SIZE(a) (sizeof(a)/sizeof(a[0]))
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#define ARRAY_SIZE(a) (sizeof(a) / sizeof(a[0]))
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static LPC_CGU_BASE_CLK_Type* const base_clocks_idivc[] = {
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&LPC_CGU->BASE_PERIPH_CLK,
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&LPC_CGU->BASE_M4_CLK,
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&LPC_CGU->BASE_APB1_CLK,
|
||||
&LPC_CGU->BASE_APB3_CLK,
|
||||
&LPC_CGU->BASE_SDIO_CLK,
|
||||
&LPC_CGU->BASE_SSP1_CLK,
|
||||
&LPC_CGU->BASE_PERIPH_CLK,
|
||||
&LPC_CGU->BASE_M4_CLK,
|
||||
&LPC_CGU->BASE_APB1_CLK,
|
||||
&LPC_CGU->BASE_APB3_CLK,
|
||||
&LPC_CGU->BASE_SDIO_CLK,
|
||||
&LPC_CGU->BASE_SSP1_CLK,
|
||||
};
|
||||
|
||||
static void set_idivc_base_clocks(const cgu::CLK_SEL clock_source) {
|
||||
for(uint32_t i=0; i<ARRAY_SIZE(base_clocks_idivc); i++) {
|
||||
base_clocks_idivc[i]->AUTOBLOCK = 1;
|
||||
base_clocks_idivc[i]->CLK_SEL = toUType(clock_source);
|
||||
}
|
||||
for (uint32_t i = 0; i < ARRAY_SIZE(base_clocks_idivc); i++) {
|
||||
base_clocks_idivc[i]->AUTOBLOCK = 1;
|
||||
base_clocks_idivc[i]->CLK_SEL = toUType(clock_source);
|
||||
}
|
||||
}
|
||||
|
||||
static void set_clock_config(const clock_config_t& config) {
|
||||
LPC_CGU->IDIVB_CTRL.word = config.idivb;
|
||||
LPC_CGU->IDIVC_CTRL.word = config.idivc;
|
||||
systick_adjust_period(config.systick_count);
|
||||
halLPCSetSystemClock(config.clock_f);
|
||||
LPC_CGU->IDIVB_CTRL.word = config.idivb;
|
||||
LPC_CGU->IDIVC_CTRL.word = config.idivc;
|
||||
systick_adjust_period(config.systick_count);
|
||||
halLPCSetSystemClock(config.clock_f);
|
||||
}
|
||||
|
||||
static void shutdown_base() {
|
||||
i2c0.stop();
|
||||
i2c0.stop();
|
||||
|
||||
set_clock_config(clock_config_irc);
|
||||
set_clock_config(clock_config_irc);
|
||||
|
||||
cgu::pll1::disable();
|
||||
cgu::pll1::disable();
|
||||
|
||||
set_idivc_base_clocks(cgu::CLK_SEL::IRC);
|
||||
set_idivc_base_clocks(cgu::CLK_SEL::IRC);
|
||||
|
||||
cgu::pll1::ctrl({
|
||||
.pd = 1,
|
||||
.bypass = 0,
|
||||
.fbsel = 0,
|
||||
.direct = 1,
|
||||
.psel = 0,
|
||||
.autoblock = 1,
|
||||
.nsel = 0,
|
||||
.msel = 23,
|
||||
.clk_sel = cgu::CLK_SEL::IRC,
|
||||
});
|
||||
cgu::pll1::ctrl({
|
||||
.pd = 1,
|
||||
.bypass = 0,
|
||||
.fbsel = 0,
|
||||
.direct = 1,
|
||||
.psel = 0,
|
||||
.autoblock = 1,
|
||||
.nsel = 0,
|
||||
.msel = 23,
|
||||
.clk_sel = cgu::CLK_SEL::IRC,
|
||||
});
|
||||
|
||||
cgu::pll1::enable();
|
||||
while( !cgu::pll1::is_locked() );
|
||||
cgu::pll1::enable();
|
||||
while (!cgu::pll1::is_locked())
|
||||
;
|
||||
|
||||
set_clock_config(clock_config_pll1_boot);
|
||||
set_clock_config(clock_config_pll1_boot);
|
||||
|
||||
i2c0.start(i2c_config_boot_clock);
|
||||
i2c0.start(i2c_config_boot_clock);
|
||||
|
||||
clock_manager.shutdown();
|
||||
clock_manager.shutdown();
|
||||
}
|
||||
|
||||
/* Clock scheme after exiting bootloader in SPIFI mode:
|
||||
*
|
||||
*
|
||||
* XTAL_OSC = powered down
|
||||
*
|
||||
* PLL0USB = powered down
|
||||
|
|
@ -376,7 +371,7 @@ static void shutdown_base() {
|
|||
*/
|
||||
|
||||
/* Clock scheme during PortaPack operation:
|
||||
*
|
||||
*
|
||||
* XTAL_OSC = powered down
|
||||
*
|
||||
* PLL0USB = powered down
|
||||
|
|
@ -400,138 +395,138 @@ static void shutdown_base() {
|
|||
*/
|
||||
|
||||
bool init() {
|
||||
set_idivc_base_clocks(cgu::CLK_SEL::IDIVC);
|
||||
set_idivc_base_clocks(cgu::CLK_SEL::IDIVC);
|
||||
|
||||
i2c0.start(i2c_config_boot_clock);
|
||||
i2c0.start(i2c_config_boot_clock);
|
||||
|
||||
// Keeping this here for now incase we need to revert
|
||||
// if( !portapack::cpld::update_if_necessary(portapack_cpld_config()) ) {
|
||||
// shutdown_base();
|
||||
// return false;
|
||||
// }
|
||||
// Keeping this here for now incase we need to revert
|
||||
// if( !portapack::cpld::update_if_necessary(portapack_cpld_config()) ) {
|
||||
// shutdown_base();
|
||||
// return false;
|
||||
// }
|
||||
|
||||
// if( !hackrf::cpld::load_sram() ) {
|
||||
// chSysHalt();
|
||||
// }
|
||||
chThdSleepMilliseconds(100);
|
||||
// if( !hackrf::cpld::load_sram() ) {
|
||||
// chSysHalt();
|
||||
// }
|
||||
chThdSleepMilliseconds(100);
|
||||
|
||||
configure_pins_portapack();
|
||||
|
||||
portapack::io.init();
|
||||
configure_pins_portapack();
|
||||
|
||||
clock_manager.init_clock_generator();
|
||||
portapack::io.init();
|
||||
|
||||
i2c0.stop();
|
||||
clock_manager.init_clock_generator();
|
||||
|
||||
chThdSleepMilliseconds(10);
|
||||
i2c0.stop();
|
||||
|
||||
set_clock_config(clock_config_irc);
|
||||
cgu::pll1::disable();
|
||||
chThdSleepMilliseconds(10);
|
||||
|
||||
/* Incantation from LPC43xx UM10503 section 12.2.1.1, to bring the M4
|
||||
* core clock speed to the 110 - 204MHz range.
|
||||
*/
|
||||
set_clock_config(clock_config_irc);
|
||||
cgu::pll1::disable();
|
||||
|
||||
/* Step into the 90-110MHz M4 clock range */
|
||||
/* OG:
|
||||
* Fclkin = 40M
|
||||
* /N=2 = 20M = PFDin
|
||||
* Fcco = PFDin * (M=10) = 200M
|
||||
* r9:
|
||||
* Fclkin = 10M
|
||||
* /N=1 = 10M = PFDin
|
||||
* Fcco = PFDin * (M=20) = 200M
|
||||
* Fclk = Fcco / (2*(P=1)) = 100M
|
||||
*/
|
||||
cgu::pll1::ctrl({
|
||||
.pd = 1,
|
||||
.bypass = 0,
|
||||
.fbsel = 0,
|
||||
.direct = 0,
|
||||
.psel = 0,
|
||||
.autoblock = 1,
|
||||
.nsel = hackrf_r9 ? 0UL : 1UL,
|
||||
.msel = hackrf_r9 ? 19UL : 9UL,
|
||||
.clk_sel = cgu::CLK_SEL::GP_CLKIN,
|
||||
});
|
||||
/* Incantation from LPC43xx UM10503 section 12.2.1.1, to bring the M4
|
||||
* core clock speed to the 110 - 204MHz range.
|
||||
*/
|
||||
|
||||
cgu::pll1::enable();
|
||||
while( !cgu::pll1::is_locked() );
|
||||
/* Step into the 90-110MHz M4 clock range */
|
||||
/* OG:
|
||||
* Fclkin = 40M
|
||||
* /N=2 = 20M = PFDin
|
||||
* Fcco = PFDin * (M=10) = 200M
|
||||
* r9:
|
||||
* Fclkin = 10M
|
||||
* /N=1 = 10M = PFDin
|
||||
* Fcco = PFDin * (M=20) = 200M
|
||||
* Fclk = Fcco / (2*(P=1)) = 100M
|
||||
*/
|
||||
cgu::pll1::ctrl({
|
||||
.pd = 1,
|
||||
.bypass = 0,
|
||||
.fbsel = 0,
|
||||
.direct = 0,
|
||||
.psel = 0,
|
||||
.autoblock = 1,
|
||||
.nsel = hackrf_r9 ? 0UL : 1UL,
|
||||
.msel = hackrf_r9 ? 19UL : 9UL,
|
||||
.clk_sel = cgu::CLK_SEL::GP_CLKIN,
|
||||
});
|
||||
|
||||
set_clock_config(clock_config_pll1_step);
|
||||
cgu::pll1::enable();
|
||||
while (!cgu::pll1::is_locked())
|
||||
;
|
||||
|
||||
/* Delay >50us at 90-110MHz clock speed */
|
||||
volatile uint32_t delay = 1400;
|
||||
while(delay--);
|
||||
set_clock_config(clock_config_pll1_step);
|
||||
|
||||
set_clock_config(clock_config_pll1);
|
||||
/* Delay >50us at 90-110MHz clock speed */
|
||||
volatile uint32_t delay = 1400;
|
||||
while (delay--)
|
||||
;
|
||||
|
||||
/* Remove /2P divider from PLL1 output to achieve full speed */
|
||||
cgu::pll1::direct();
|
||||
set_clock_config(clock_config_pll1);
|
||||
|
||||
i2c0.start(i2c_config_fast_clock);
|
||||
chThdSleepMilliseconds(10);
|
||||
/* Remove /2P divider from PLL1 output to achieve full speed */
|
||||
cgu::pll1::direct();
|
||||
|
||||
/* Cache some configuration data from persistent memory. */
|
||||
persistent_memory::cache::init();
|
||||
i2c0.start(i2c_config_fast_clock);
|
||||
chThdSleepMilliseconds(10);
|
||||
|
||||
touch::adc::init();
|
||||
controls_init();
|
||||
chThdSleepMilliseconds(10);
|
||||
/* Cache some configuration data from persistent memory. */
|
||||
persistent_memory::cache::init();
|
||||
|
||||
clock_manager.set_reference_ppb(persistent_memory::correction_ppb());
|
||||
clock_manager.enable_if_clocks();
|
||||
clock_manager.enable_codec_clocks();
|
||||
radio::init();
|
||||
touch::adc::init();
|
||||
controls_init();
|
||||
chThdSleepMilliseconds(10);
|
||||
|
||||
sdcStart(&SDCD1, nullptr);
|
||||
sd_card::poll_inserted();
|
||||
|
||||
chThdSleepMilliseconds(10);
|
||||
clock_manager.set_reference_ppb(persistent_memory::correction_ppb());
|
||||
clock_manager.enable_if_clocks();
|
||||
clock_manager.enable_codec_clocks();
|
||||
radio::init();
|
||||
|
||||
portapack::cpld::CpldUpdateStatus result = portapack::cpld::update_if_necessary(portapack_cpld_config());
|
||||
if ( result == portapack::cpld::CpldUpdateStatus::Program_failed ) {
|
||||
sdcStart(&SDCD1, nullptr);
|
||||
sd_card::poll_inserted();
|
||||
|
||||
chThdSleepMilliseconds(10);
|
||||
// Mode left (R1) and right (R2,H2,H2+) bypass going into hackrf mode after failing CPLD update
|
||||
// Mode center (autodetect), up (R1) and down (R2,H2,H2+) will go into hackrf mode after failing CPLD update
|
||||
if (load_config() != 3 /* left */ && load_config() != 4 /* right */){
|
||||
shutdown_base();
|
||||
return false;
|
||||
}
|
||||
}
|
||||
chThdSleepMilliseconds(10);
|
||||
|
||||
if( !hackrf::cpld::load_sram() ) {
|
||||
chSysHalt();
|
||||
}
|
||||
portapack::cpld::CpldUpdateStatus result = portapack::cpld::update_if_necessary(portapack_cpld_config());
|
||||
if (result == portapack::cpld::CpldUpdateStatus::Program_failed) {
|
||||
chThdSleepMilliseconds(10);
|
||||
// Mode left (R1) and right (R2,H2,H2+) bypass going into hackrf mode after failing CPLD update
|
||||
// Mode center (autodetect), up (R1) and down (R2,H2,H2+) will go into hackrf mode after failing CPLD update
|
||||
if (load_config() != 3 /* left */ && load_config() != 4 /* right */) {
|
||||
shutdown_base();
|
||||
return false;
|
||||
}
|
||||
}
|
||||
|
||||
chThdSleepMilliseconds(10); // This delay seems to solve white noise audio issues
|
||||
if (!hackrf::cpld::load_sram()) {
|
||||
chSysHalt();
|
||||
}
|
||||
|
||||
LPC_CREG->DMAMUX = portapack::gpdma_mux;
|
||||
gpdma::controller.enable();
|
||||
chThdSleepMilliseconds(10); // This delay seems to solve white noise audio issues
|
||||
|
||||
chThdSleepMilliseconds(10);
|
||||
LPC_CREG->DMAMUX = portapack::gpdma_mux;
|
||||
gpdma::controller.enable();
|
||||
|
||||
audio::init(portapack_audio_codec());
|
||||
|
||||
chThdSleepMilliseconds(10);
|
||||
|
||||
return true;
|
||||
audio::init(portapack_audio_codec());
|
||||
|
||||
return true;
|
||||
}
|
||||
|
||||
void shutdown(const bool leave_screen_on) {
|
||||
gpdma::controller.disable();
|
||||
gpdma::controller.disable();
|
||||
|
||||
if (!leave_screen_on) {
|
||||
backlight()->off();
|
||||
display.shutdown();
|
||||
}
|
||||
|
||||
radio::disable();
|
||||
audio::shutdown();
|
||||
if (!leave_screen_on) {
|
||||
backlight()->off();
|
||||
display.shutdown();
|
||||
}
|
||||
|
||||
hackrf::cpld::init_from_eeprom();
|
||||
radio::disable();
|
||||
audio::shutdown();
|
||||
|
||||
shutdown_base();
|
||||
hackrf::cpld::init_from_eeprom();
|
||||
|
||||
shutdown_base();
|
||||
}
|
||||
|
||||
} /* namespace portapack */
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue