mirror of
https://github.com/eried/portapack-mayhem.git
synced 2025-08-02 11:36:38 -04:00
Formatted code (#1007)
* Updated style * Updated files * fixed new line * Updated spacing * File fix WIP * Updated to clang 13 * updated comment style * Removed old comment code
This commit is contained in:
jLynx
GitHub
parent
7aca7ce74d
commit
033c4e9a5b
599 changed files with 70746 additions and 66896 deletions
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@ -36,158 +36,157 @@ namespace si5351 {
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using reg_t = uint8_t;
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namespace Register {
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enum {
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DeviceStatus = 0,
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InterruptStatusSticky = 1,
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InterruptStatusMask = 2,
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OutputEnableControl = 3,
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OEBPinEnableControlMask = 9,
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PLLInputSource = 15,
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CLKControl_Base = 16,
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CLKControl0 = 16,
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CLKControl1 = 17,
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CLKControl2 = 18,
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CLKControl3 = 19,
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CLKControl4 = 20,
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CLKControl5 = 21,
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CLKControl6 = 22,
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CLKControl7 = 23,
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CLK3_0DisableState = 24,
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CLK7_4DisableState = 25,
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MultisynthNAParameters_Base = 26,
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MultisynthNBParameters_Base = 34,
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Multisynth0Parameters_Base = 42,
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Multisynth1Parameters_Base = 50,
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Multisynth2Parameters_Base = 58,
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Multisynth3Parameters_Base = 66,
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Multisynth4Parameters_Base = 74,
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Multisynth5Parameters_Base = 82,
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Multisynth6Parameters = 90,
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Multisynth7Parameters = 91,
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Clock6And7OutputDivider = 92,
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SpreadSpectrumParameters_Base = 149,
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VCXOParameters_Base = 162,
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CLKInitialPhaseOffset_Base = 165,
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PLLReset = 177,
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CrystalInternalLoadCapacitance = 183,
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FanoutEnable = 187,
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};
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enum {
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DeviceStatus = 0,
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InterruptStatusSticky = 1,
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InterruptStatusMask = 2,
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OutputEnableControl = 3,
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OEBPinEnableControlMask = 9,
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PLLInputSource = 15,
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CLKControl_Base = 16,
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CLKControl0 = 16,
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CLKControl1 = 17,
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CLKControl2 = 18,
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CLKControl3 = 19,
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CLKControl4 = 20,
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CLKControl5 = 21,
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CLKControl6 = 22,
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CLKControl7 = 23,
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CLK3_0DisableState = 24,
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CLK7_4DisableState = 25,
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MultisynthNAParameters_Base = 26,
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MultisynthNBParameters_Base = 34,
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Multisynth0Parameters_Base = 42,
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Multisynth1Parameters_Base = 50,
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Multisynth2Parameters_Base = 58,
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Multisynth3Parameters_Base = 66,
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Multisynth4Parameters_Base = 74,
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Multisynth5Parameters_Base = 82,
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Multisynth6Parameters = 90,
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Multisynth7Parameters = 91,
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Clock6And7OutputDivider = 92,
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SpreadSpectrumParameters_Base = 149,
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VCXOParameters_Base = 162,
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CLKInitialPhaseOffset_Base = 165,
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PLLReset = 177,
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CrystalInternalLoadCapacitance = 183,
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FanoutEnable = 187,
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};
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}
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namespace DeviceStatus {
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using Type = uint8_t;
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using Type = uint8_t;
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enum {
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REVID_Mask = (0b11 << 0),
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enum {
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REVID_Mask = (0b11 << 0),
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LOS_Mask = (1 << 4),
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LOS_ValidClockAtCLKIN = (0 << 4),
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LOS_LossOfSignalAtCLKIN = (1 << 4),
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LOS_Mask = (1 << 4),
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LOS_ValidClockAtCLKIN = (0 << 4),
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LOS_LossOfSignalAtCLKIN = (1 << 4),
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LOL_A_Mask = (1 << 5),
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LOL_A_PLLALocked = (0 << 5),
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LOL_A_PLLAUnlocked = (1 << 5),
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LOL_A_Mask = (1 << 5),
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LOL_A_PLLALocked = (0 << 5),
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LOL_A_PLLAUnlocked = (1 << 5),
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LOL_B_Mask = (1 << 6),
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LOL_B_PLLBLocked = (0 << 6),
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LOL_B_PLLBUnlocked = (1 << 6),
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LOL_B_Mask = (1 << 6),
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LOL_B_PLLBLocked = (0 << 6),
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LOL_B_PLLBUnlocked = (1 << 6),
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SYS_INIT_Mask = (1 << 7),
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SYS_INIT_Complete = (0 << 7),
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SYS_INIT_Initializing = (1 << 7),
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};
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}
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SYS_INIT_Mask = (1 << 7),
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SYS_INIT_Complete = (0 << 7),
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SYS_INIT_Initializing = (1 << 7),
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};
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} // namespace DeviceStatus
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struct ClockControl {
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enum ClockCurrentDrive {
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_2mA = 0b00,
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_4mA = 0b01,
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_6mA = 0b10,
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_8mA = 0b11,
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};
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enum ClockCurrentDrive {
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_2mA = 0b00,
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_4mA = 0b01,
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_6mA = 0b10,
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_8mA = 0b11,
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};
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enum ClockSource {
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Xtal = 0b00,
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CLKIN = 0b01,
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MS_Group = 0b10,
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MS_Self = 0b11,
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};
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enum ClockSource {
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Xtal = 0b00,
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CLKIN = 0b01,
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MS_Group = 0b10,
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MS_Self = 0b11,
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};
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enum ClockInvert {
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Normal = 0,
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Invert = 1,
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};
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enum ClockInvert {
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Normal = 0,
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Invert = 1,
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};
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enum MultiSynthSource {
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PLLA = 0,
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PLLB = 1,
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};
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enum MultiSynthSource {
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PLLA = 0,
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PLLB = 1,
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};
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enum MultiSynthMode {
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Fractional = 0,
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Integer = 1,
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};
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enum MultiSynthMode {
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Fractional = 0,
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Integer = 1,
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};
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enum ClockPowerDown {
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Power_On = 0,
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Power_Off = 1,
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};
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enum ClockPowerDown {
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Power_On = 0,
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Power_Off = 1,
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};
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reg_t CLK_IDRV : 2;
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reg_t CLK_SRC : 2;
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reg_t CLK_INV : 1;
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reg_t MS_SRC : 1;
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reg_t MS_INT : 1;
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reg_t CLK_PDN : 1;
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reg_t CLK_IDRV : 2;
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reg_t CLK_SRC : 2;
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reg_t CLK_INV : 1;
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reg_t MS_SRC : 1;
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reg_t MS_INT : 1;
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reg_t CLK_PDN : 1;
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constexpr ClockControl(
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ClockCurrentDrive clk_idrv,
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ClockSource clk_src,
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ClockInvert clk_inv,
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MultiSynthSource ms_src,
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MultiSynthMode ms_int,
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ClockPowerDown clk_pdn
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) : CLK_IDRV(clk_idrv),
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CLK_SRC(clk_src),
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CLK_INV(clk_inv),
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MS_SRC(ms_src),
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MS_INT(ms_int),
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CLK_PDN(clk_pdn)
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{
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}
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constexpr ClockControl(
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ClockCurrentDrive clk_idrv,
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ClockSource clk_src,
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ClockInvert clk_inv,
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MultiSynthSource ms_src,
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MultiSynthMode ms_int,
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ClockPowerDown clk_pdn)
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: CLK_IDRV(clk_idrv),
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CLK_SRC(clk_src),
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CLK_INV(clk_inv),
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MS_SRC(ms_src),
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MS_INT(ms_int),
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CLK_PDN(clk_pdn) {
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}
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ClockControl clk_src(const ClockSource value) const {
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auto result = *this;
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result.CLK_SRC = value;
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return result;
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}
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ClockControl ms_src(const MultiSynthSource value) const {
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auto result = *this;
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result.MS_SRC = value;
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return result;
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}
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ClockControl clk_src(const ClockSource value) const {
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auto result = *this;
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result.CLK_SRC = value;
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return result;
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}
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ClockControl clk_pdn(const ClockPowerDown value) const {
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auto result = *this;
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result.CLK_PDN = value;
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return result;
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}
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ClockControl ms_src(const MultiSynthSource value) const {
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auto result = *this;
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result.MS_SRC = value;
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return result;
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}
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constexpr operator reg_t() {
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return *reinterpret_cast<reg_t*>(this);
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}
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ClockControl clk_pdn(const ClockPowerDown value) const {
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auto result = *this;
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result.CLK_PDN = value;
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return result;
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}
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static constexpr ClockControl power_off() {
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return {
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ClockCurrentDrive::_2mA,
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ClockSource::Xtal,
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ClockInvert::Normal,
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MultiSynthSource::PLLA,
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MultiSynthMode::Fractional,
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ClockPowerDown::Power_Off,
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};
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}
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constexpr operator reg_t() {
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return *reinterpret_cast<reg_t*>(this);
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}
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static constexpr ClockControl power_off() {
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return {
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ClockCurrentDrive::_2mA,
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ClockSource::Xtal,
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ClockInvert::Normal,
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MultiSynthSource::PLLA,
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MultiSynthMode::Fractional,
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ClockPowerDown::Power_Off,
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};
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}
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};
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static_assert(sizeof(ClockControl) == 1, "ClockControl size is not eight bits");
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@ -195,302 +194,294 @@ static_assert(sizeof(ClockControl) == 1, "ClockControl size is not eight bits");
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using ClockControls = std::array<ClockControl, 8>;
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namespace CrystalInternalLoadCapacitance {
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using Type = uint8_t;
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using Type = uint8_t;
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enum {
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XTAL_CL_Mask = (0b11 << 6),
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XTAL_CL_6pF = (0b01 << 6),
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XTAL_CL_8pF = (0b10 << 6),
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XTAL_CL_10pF = (0b11 << 6),
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};
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}
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enum {
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XTAL_CL_Mask = (0b11 << 6),
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XTAL_CL_6pF = (0b01 << 6),
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XTAL_CL_8pF = (0b10 << 6),
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XTAL_CL_10pF = (0b11 << 6),
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};
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} // namespace CrystalInternalLoadCapacitance
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namespace PLLInputSource {
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using Type = uint8_t;
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using Type = uint8_t;
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enum {
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PLLA_Source_Mask = (1 << 2),
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PLLA_Source_XTAL = (0 << 2),
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PLLA_Source_CLKIN = (1 << 2),
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enum {
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PLLA_Source_Mask = (1 << 2),
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PLLA_Source_XTAL = (0 << 2),
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PLLA_Source_CLKIN = (1 << 2),
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PLLB_Source_Mask = (1 << 3),
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PLLB_Source_XTAL = (0 << 3),
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PLLB_Source_CLKIN = (1 << 3),
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PLLB_Source_Mask = (1 << 3),
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PLLB_Source_XTAL = (0 << 3),
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PLLB_Source_CLKIN = (1 << 3),
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CLKIN_Div_Mask = (0b11 << 6),
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CLKIN_Div1 = (0b00 << 6),
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CLKIN_Div2 = (0b01 << 6),
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CLKIN_Div4 = (0b10 << 6),
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CLKIN_Div8 = (0b11 << 6),
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};
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}
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CLKIN_Div_Mask = (0b11 << 6),
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CLKIN_Div1 = (0b00 << 6),
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CLKIN_Div2 = (0b01 << 6),
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CLKIN_Div4 = (0b10 << 6),
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CLKIN_Div8 = (0b11 << 6),
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};
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} // namespace PLLInputSource
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struct Inputs {
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const uint32_t f_xtal;
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const uint32_t f_clkin;
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const uint32_t clkin_div;
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const uint32_t f_xtal;
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const uint32_t f_clkin;
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const uint32_t clkin_div;
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constexpr uint32_t f_clkin_out() const {
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return f_clkin / clkin_div;
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}
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constexpr uint32_t f_clkin_out() const {
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return f_clkin / clkin_div;
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}
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};
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using PLLReg = std::array<uint8_t, 9>;
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struct PLL {
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const uint32_t f_in;
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const uint32_t a;
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const uint32_t b;
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const uint32_t c;
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const uint32_t f_in;
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const uint32_t a;
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const uint32_t b;
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const uint32_t c;
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constexpr uint32_t f_vco() const {
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return f_in * (a + (float)b / (float)c);
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}
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constexpr uint32_t f_vco() const {
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return f_in * (a + (float)b / (float)c);
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}
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constexpr uint32_t p1() const {
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return 128 * a + (uint32_t)(128 * (float)b / (float)c) - 512;
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}
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constexpr uint32_t p1() const {
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return 128 * a + (uint32_t)(128 * (float)b / (float)c) - 512;
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}
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constexpr uint32_t p2() const {
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return 128 * b - c * (uint32_t)(128 * (float)b / (float)c);
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}
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constexpr uint32_t p2() const {
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return 128 * b - c * (uint32_t)(128 * (float)b / (float)c);
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}
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constexpr uint32_t p3() const {
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return c;
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}
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constexpr uint32_t p3() const {
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return c;
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}
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constexpr PLLReg reg(const uint8_t pll_n) const {
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return {
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uint8_t(26 + (pll_n * 8)),
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uint8_t((p3() >> 8) & 0xff),
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uint8_t((p3() >> 0) & 0xff),
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uint8_t((p1() >> 16) & 0x03),
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uint8_t((p1() >> 8) & 0xff),
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uint8_t((p1() >> 0) & 0xff),
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uint8_t(
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(((p3() >> 16) & 0x0f) << 4)
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| ((p2() >> 16) & 0x0f)
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),
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uint8_t((p2() >> 8) & 0xff),
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uint8_t((p2() >> 0) & 0xff),
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};
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}
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constexpr PLLReg reg(const uint8_t pll_n) const {
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return {
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uint8_t(26 + (pll_n * 8)),
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uint8_t((p3() >> 8) & 0xff),
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uint8_t((p3() >> 0) & 0xff),
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uint8_t((p1() >> 16) & 0x03),
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uint8_t((p1() >> 8) & 0xff),
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uint8_t((p1() >> 0) & 0xff),
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uint8_t(
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(((p3() >> 16) & 0x0f) << 4) | ((p2() >> 16) & 0x0f)),
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uint8_t((p2() >> 8) & 0xff),
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uint8_t((p2() >> 0) & 0xff),
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};
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}
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};
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using MultisynthFractionalReg = std::array<uint8_t, 9>;
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struct MultisynthFractional {
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const uint32_t f_src;
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const uint32_t a;
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const uint32_t b;
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const uint32_t c;
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const uint32_t r_div;
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const uint32_t f_src;
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const uint32_t a;
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const uint32_t b;
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const uint32_t c;
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const uint32_t r_div;
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constexpr uint32_t p1() const {
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return 128 * a + (uint32_t)(128 * (float)b / (float)c) - 512;
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}
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constexpr uint32_t p1() const {
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return 128 * a + (uint32_t)(128 * (float)b / (float)c) - 512;
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}
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constexpr uint32_t p2() const {
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return 128 * b - c * (uint32_t)(128 * (float)b / (float)c);
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}
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constexpr uint32_t p2() const {
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return 128 * b - c * (uint32_t)(128 * (float)b / (float)c);
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}
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constexpr uint32_t p3() const {
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return c;
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}
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constexpr uint32_t p3() const {
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return c;
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}
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constexpr uint32_t f_out() const {
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return f_src / (a + (float)b / (float)c) / (1 << r_div);
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}
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constexpr uint32_t f_out() const {
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return f_src / (a + (float)b / (float)c) / (1 << r_div);
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}
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constexpr MultisynthFractionalReg reg(const uint8_t multisynth_n) const {
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return {
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uint8_t(42 + (multisynth_n * 8)),
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uint8_t((p3() >> 8) & 0xFF),
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uint8_t((p3() >> 0) & 0xFF),
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uint8_t((r_div << 4) | (0 << 2) | ((p1() >> 16) & 0x3)),
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||||
uint8_t((p1() >> 8) & 0xFF),
|
||||
uint8_t((p1() >> 0) & 0xFF),
|
||||
uint8_t((((p3() >> 16) & 0xF) << 4) | (((p2() >> 16) & 0xF) << 0)),
|
||||
uint8_t((p2() >> 8) & 0xFF),
|
||||
uint8_t((p2() >> 0) & 0xFF)
|
||||
};
|
||||
}
|
||||
constexpr MultisynthFractionalReg reg(const uint8_t multisynth_n) const {
|
||||
return {
|
||||
uint8_t(42 + (multisynth_n * 8)),
|
||||
uint8_t((p3() >> 8) & 0xFF),
|
||||
uint8_t((p3() >> 0) & 0xFF),
|
||||
uint8_t((r_div << 4) | (0 << 2) | ((p1() >> 16) & 0x3)),
|
||||
uint8_t((p1() >> 8) & 0xFF),
|
||||
uint8_t((p1() >> 0) & 0xFF),
|
||||
uint8_t((((p3() >> 16) & 0xF) << 4) | (((p2() >> 16) & 0xF) << 0)),
|
||||
uint8_t((p2() >> 8) & 0xFF),
|
||||
uint8_t((p2() >> 0) & 0xFF)};
|
||||
}
|
||||
};
|
||||
|
||||
struct MultisynthInteger {
|
||||
const uint32_t f_src;
|
||||
const uint32_t a;
|
||||
const uint32_t r_div;
|
||||
const uint32_t f_src;
|
||||
const uint32_t a;
|
||||
const uint32_t r_div;
|
||||
|
||||
constexpr uint8_t p1() const {
|
||||
return a;
|
||||
}
|
||||
constexpr uint8_t p1() const {
|
||||
return a;
|
||||
}
|
||||
|
||||
constexpr uint32_t f_out() const {
|
||||
return f_src / a / (1 << r_div);
|
||||
}
|
||||
constexpr uint32_t f_out() const {
|
||||
return f_src / a / (1 << r_div);
|
||||
}
|
||||
};
|
||||
|
||||
using Multisynth6And7Reg = std::array<uint8_t, 4>;
|
||||
|
||||
constexpr Multisynth6And7Reg ms6_7_reg(
|
||||
const MultisynthInteger& ms6,
|
||||
const MultisynthInteger& ms7
|
||||
) {
|
||||
return {
|
||||
Register::Multisynth6Parameters,
|
||||
uint8_t(ms6.p1() & 0xff),
|
||||
uint8_t(ms7.p1() & 0xff),
|
||||
uint8_t(((ms7.r_div & 7) << 4) | ((ms6.r_div & 7) << 0)),
|
||||
};
|
||||
const MultisynthInteger& ms6,
|
||||
const MultisynthInteger& ms7) {
|
||||
return {
|
||||
Register::Multisynth6Parameters,
|
||||
uint8_t(ms6.p1() & 0xff),
|
||||
uint8_t(ms7.p1() & 0xff),
|
||||
uint8_t(((ms7.r_div & 7) << 4) | ((ms6.r_div & 7) << 0)),
|
||||
};
|
||||
}
|
||||
|
||||
class Si5351 {
|
||||
public:
|
||||
using regvalue_t = uint8_t;
|
||||
public:
|
||||
using regvalue_t = uint8_t;
|
||||
|
||||
constexpr Si5351(I2C& bus, I2C::address_t address) :
|
||||
_clock_control({
|
||||
ClockControl::power_off(), ClockControl::power_off(),
|
||||
ClockControl::power_off(), ClockControl::power_off(),
|
||||
ClockControl::power_off(), ClockControl::power_off(),
|
||||
ClockControl::power_off(), ClockControl::power_off()
|
||||
}),
|
||||
_bus(bus),
|
||||
_address(address),
|
||||
_output_enable(0x00)
|
||||
{
|
||||
}
|
||||
constexpr Si5351(I2C& bus, I2C::address_t address)
|
||||
: _clock_control({ClockControl::power_off(), ClockControl::power_off(),
|
||||
ClockControl::power_off(), ClockControl::power_off(),
|
||||
ClockControl::power_off(), ClockControl::power_off(),
|
||||
ClockControl::power_off(), ClockControl::power_off()}),
|
||||
_bus(bus),
|
||||
_address(address),
|
||||
_output_enable(0x00) {
|
||||
}
|
||||
|
||||
void reset();
|
||||
void reset();
|
||||
|
||||
uint8_t device_status() {
|
||||
return read_register(Register::DeviceStatus);
|
||||
}
|
||||
uint8_t device_status() {
|
||||
return read_register(Register::DeviceStatus);
|
||||
}
|
||||
|
||||
void wait_for_device_ready() {
|
||||
while(device_status() & 0x80);
|
||||
}
|
||||
void wait_for_device_ready() {
|
||||
while (device_status() & 0x80)
|
||||
;
|
||||
}
|
||||
|
||||
bool plla_loss_of_signal() {
|
||||
return (device_status() >> 5) & 1;
|
||||
}
|
||||
bool plla_loss_of_signal() {
|
||||
return (device_status() >> 5) & 1;
|
||||
}
|
||||
|
||||
bool clkin_loss_of_signal() {
|
||||
return (device_status() >> 4) & 1;
|
||||
}
|
||||
|
||||
void enable_fanout() {
|
||||
write_register(Register::FanoutEnable, 0b11010000);
|
||||
}
|
||||
bool clkin_loss_of_signal() {
|
||||
return (device_status() >> 4) & 1;
|
||||
}
|
||||
|
||||
void reset_plls() {
|
||||
// Datasheet recommends value 0xac, though the low nibble bits are not defined in AN619.
|
||||
write_register(Register::PLLReset, 0xac);
|
||||
}
|
||||
void enable_fanout() {
|
||||
write_register(Register::FanoutEnable, 0b11010000);
|
||||
}
|
||||
|
||||
regvalue_t read_register(const uint8_t reg);
|
||||
void reset_plls() {
|
||||
// Datasheet recommends value 0xac, though the low nibble bits are not defined in AN619.
|
||||
write_register(Register::PLLReset, 0xac);
|
||||
}
|
||||
|
||||
template<size_t N>
|
||||
void write(const std::array<uint8_t, N>& values) {
|
||||
_bus.transmit(_address, values.data(), values.size());
|
||||
}
|
||||
regvalue_t read_register(const uint8_t reg);
|
||||
|
||||
void write_register(const uint8_t reg, const regvalue_t value) {
|
||||
write(std::array<uint8_t, 2>{
|
||||
reg, value
|
||||
});
|
||||
}
|
||||
template <size_t N>
|
||||
void write(const std::array<uint8_t, N>& values) {
|
||||
_bus.transmit(_address, values.data(), values.size());
|
||||
}
|
||||
|
||||
void write(const size_t ms_number, const MultisynthFractional& config) {
|
||||
write(config.reg(ms_number));
|
||||
}
|
||||
void write_register(const uint8_t reg, const regvalue_t value) {
|
||||
write(std::array<uint8_t, 2>{
|
||||
reg, value});
|
||||
}
|
||||
|
||||
void set_ms_frequency(
|
||||
const size_t ms_number,
|
||||
const uint32_t frequency,
|
||||
const uint32_t vco_frequency,
|
||||
const size_t r_div
|
||||
);
|
||||
void write(const size_t ms_number, const MultisynthFractional& config) {
|
||||
write(config.reg(ms_number));
|
||||
}
|
||||
|
||||
void set_crystal_internal_load_capacitance(const CrystalInternalLoadCapacitance::Type xtal_cl) {
|
||||
write_register(Register::CrystalInternalLoadCapacitance, xtal_cl);
|
||||
}
|
||||
void set_ms_frequency(
|
||||
const size_t ms_number,
|
||||
const uint32_t frequency,
|
||||
const uint32_t vco_frequency,
|
||||
const size_t r_div);
|
||||
|
||||
void set_pll_input_sources(const PLLInputSource::Type value) {
|
||||
write_register(Register::PLLInputSource, value);
|
||||
}
|
||||
void set_crystal_internal_load_capacitance(const CrystalInternalLoadCapacitance::Type xtal_cl) {
|
||||
write_register(Register::CrystalInternalLoadCapacitance, xtal_cl);
|
||||
}
|
||||
|
||||
void enable_output_mask(const uint8_t mask) {
|
||||
_output_enable |= mask;
|
||||
update_output_enable_control();
|
||||
}
|
||||
void set_pll_input_sources(const PLLInputSource::Type value) {
|
||||
write_register(Register::PLLInputSource, value);
|
||||
}
|
||||
|
||||
void enable_output(const size_t n) {
|
||||
enable_output_mask(1 << n);
|
||||
}
|
||||
void enable_output_mask(const uint8_t mask) {
|
||||
_output_enable |= mask;
|
||||
update_output_enable_control();
|
||||
}
|
||||
|
||||
void disable_output_mask(const uint8_t mask) {
|
||||
_output_enable &= ~mask;
|
||||
update_output_enable_control();
|
||||
}
|
||||
void enable_output(const size_t n) {
|
||||
enable_output_mask(1 << n);
|
||||
}
|
||||
|
||||
void disable_output(const size_t n) {
|
||||
disable_output_mask(1 << n);
|
||||
}
|
||||
void disable_output_mask(const uint8_t mask) {
|
||||
_output_enable &= ~mask;
|
||||
update_output_enable_control();
|
||||
}
|
||||
|
||||
void set_clock_control(const ClockControls& clock_control) {
|
||||
_clock_control = clock_control;
|
||||
update_all_clock_control();
|
||||
}
|
||||
void disable_output(const size_t n) {
|
||||
disable_output_mask(1 << n);
|
||||
}
|
||||
|
||||
void set_clock_control(const size_t n, const ClockControl clock_control) {
|
||||
_clock_control[n] = clock_control;
|
||||
write_register(Register::CLKControl_Base + n, _clock_control[n]);
|
||||
}
|
||||
void set_clock_control(const ClockControls& clock_control) {
|
||||
_clock_control = clock_control;
|
||||
update_all_clock_control();
|
||||
}
|
||||
|
||||
void enable_clock(const size_t n) {
|
||||
_clock_control[n].CLK_PDN = ClockControl::ClockPowerDown::Power_On;
|
||||
write_register(Register::CLKControl_Base + n, _clock_control[n]);
|
||||
}
|
||||
void set_clock_control(const size_t n, const ClockControl clock_control) {
|
||||
_clock_control[n] = clock_control;
|
||||
write_register(Register::CLKControl_Base + n, _clock_control[n]);
|
||||
}
|
||||
|
||||
void disable_clock(const size_t n) {
|
||||
_clock_control[n].CLK_PDN = ClockControl::ClockPowerDown::Power_Off;
|
||||
write_register(Register::CLKControl_Base + n, _clock_control[n]);
|
||||
}
|
||||
void enable_clock(const size_t n) {
|
||||
_clock_control[n].CLK_PDN = ClockControl::ClockPowerDown::Power_On;
|
||||
write_register(Register::CLKControl_Base + n, _clock_control[n]);
|
||||
}
|
||||
|
||||
template<size_t N>
|
||||
void write_registers(const uint8_t reg, const std::array<uint8_t, N>& values) {
|
||||
std::array<uint8_t, N + 1> data;
|
||||
data[0] = reg;
|
||||
std::copy(values.cbegin(), values.cend(), data.begin() + 1);
|
||||
write(data);
|
||||
}
|
||||
void disable_clock(const size_t n) {
|
||||
_clock_control[n].CLK_PDN = ClockControl::ClockPowerDown::Power_Off;
|
||||
write_register(Register::CLKControl_Base + n, _clock_control[n]);
|
||||
}
|
||||
|
||||
private:
|
||||
ClockControls _clock_control;
|
||||
I2C& _bus;
|
||||
const I2C::address_t _address;
|
||||
uint8_t _output_enable;
|
||||
template <size_t N>
|
||||
void write_registers(const uint8_t reg, const std::array<uint8_t, N>& values) {
|
||||
std::array<uint8_t, N + 1> data;
|
||||
data[0] = reg;
|
||||
std::copy(values.cbegin(), values.cend(), data.begin() + 1);
|
||||
write(data);
|
||||
}
|
||||
|
||||
void update_output_enable_control() {
|
||||
write_register(Register::OutputEnableControl, ~_output_enable);
|
||||
}
|
||||
private:
|
||||
ClockControls _clock_control;
|
||||
I2C& _bus;
|
||||
const I2C::address_t _address;
|
||||
uint8_t _output_enable;
|
||||
|
||||
void update_all_clock_control() {
|
||||
write_registers(Register::CLKControl_Base, std::array<reg_t, 8> { {
|
||||
_clock_control[0],
|
||||
_clock_control[1],
|
||||
_clock_control[2],
|
||||
_clock_control[3],
|
||||
_clock_control[4],
|
||||
_clock_control[5],
|
||||
_clock_control[6],
|
||||
_clock_control[7],
|
||||
} });
|
||||
}
|
||||
void update_output_enable_control() {
|
||||
write_register(Register::OutputEnableControl, ~_output_enable);
|
||||
}
|
||||
|
||||
void update_all_clock_control() {
|
||||
write_registers(Register::CLKControl_Base, std::array<reg_t, 8>{{
|
||||
_clock_control[0],
|
||||
_clock_control[1],
|
||||
_clock_control[2],
|
||||
_clock_control[3],
|
||||
_clock_control[4],
|
||||
_clock_control[5],
|
||||
_clock_control[6],
|
||||
_clock_control[7],
|
||||
}});
|
||||
}
|
||||
};
|
||||
|
||||
}
|
||||
} // namespace si5351
|
||||
|
||||
#endif/*__SI5351_H__*/
|
||||
#endif /*__SI5351_H__*/
|
||||
|
|
|
|||
Loading…
Add table
Add a link
Reference in a new issue