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https://github.com/eried/portapack-mayhem.git
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Formatted code (#1007)
* Updated style * Updated files * fixed new line * Updated spacing * File fix WIP * Updated to clang 13 * updated comment style * Removed old comment code
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599 changed files with 70746 additions and 66896 deletions
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@ -51,7 +51,7 @@ constexpr auto reference_frequency = rffc5072_reference_f;
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namespace vco {
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constexpr rf::FrequencyRange range { 2700000000, 5400000000 };
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constexpr rf::FrequencyRange range{2700000000, 5400000000};
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} /* namespace vco */
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@ -63,24 +63,24 @@ constexpr size_t divider_log2_max = 5;
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constexpr size_t divider_min = 1U << divider_log2_min;
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constexpr size_t divider_max = 1U << divider_log2_max;
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constexpr rf::FrequencyRange range { vco::range.minimum / divider_max, vco::range.maximum / divider_min };
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constexpr rf::FrequencyRange range{vco::range.minimum / divider_max, vco::range.maximum / divider_min};
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size_t divider_log2(const rf::Frequency lo_frequency) {
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/* TODO: Error */
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/*
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if( lo::range.out_of_range(lo_frequency) ) {
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return;
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}
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*/
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/* Compute LO divider. */
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auto lo_divider_log2 = lo::divider_log2_min;
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auto vco_frequency = lo_frequency;
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while( vco::range.below_range(vco_frequency) ) {
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vco_frequency <<= 1;
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lo_divider_log2 += 1;
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}
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/* TODO: Error */
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/*
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if( lo::range.out_of_range(lo_frequency) ) {
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return;
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}
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*/
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/* Compute LO divider. */
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auto lo_divider_log2 = lo::divider_log2_min;
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auto vco_frequency = lo_frequency;
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while (vco::range.below_range(vco_frequency)) {
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vco_frequency <<= 1;
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lo_divider_log2 += 1;
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}
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return lo_divider_log2;
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return lo_divider_log2;
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}
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} /* namespace lo */
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@ -96,42 +96,40 @@ constexpr size_t divider_min = 1U << divider_log2_min;
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constexpr size_t divider_max = 1U << divider_log2_max;
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constexpr size_t divider_log2(const rf::Frequency vco_frequency) {
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return (vco_frequency > (prescaler::divider_min * prescaler::max_frequency))
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? prescaler::divider_log2_max
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: prescaler::divider_log2_min
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;
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return (vco_frequency > (prescaler::divider_min * prescaler::max_frequency))
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? prescaler::divider_log2_max
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: prescaler::divider_log2_min;
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}
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} /* namespace prescaler */
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struct SynthConfig {
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const size_t lo_divider_log2;
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const size_t prescaler_divider_log2;
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const uint64_t n_divider_q24;
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const size_t lo_divider_log2;
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const size_t prescaler_divider_log2;
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const uint64_t n_divider_q24;
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static SynthConfig calculate(
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const rf::Frequency lo_frequency
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) {
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/* RFFC507x frequency synthesizer is is accurate to about 2ppb (two parts
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* per BILLION). There's not much point to worrying about rounding and
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* tuning error, when it amounts to 8Hz at 5GHz!
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*/
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const size_t lo_divider_log2 = lo::divider_log2(lo_frequency);
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const size_t lo_divider = 1U << lo_divider_log2;
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static SynthConfig calculate(
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const rf::Frequency lo_frequency) {
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/* RFFC507x frequency synthesizer is is accurate to about 2ppb (two parts
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* per BILLION). There's not much point to worrying about rounding and
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* tuning error, when it amounts to 8Hz at 5GHz!
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*/
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const size_t lo_divider_log2 = lo::divider_log2(lo_frequency);
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const size_t lo_divider = 1U << lo_divider_log2;
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const rf::Frequency vco_frequency = lo_frequency * lo_divider;
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const rf::Frequency vco_frequency = lo_frequency * lo_divider;
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const size_t prescaler_divider_log2 = prescaler::divider_log2(vco_frequency);
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const size_t prescaler_divider_log2 = prescaler::divider_log2(vco_frequency);
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const uint64_t prescaled_lo_q24 = vco_frequency << (24 - prescaler_divider_log2);
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const uint64_t n_divider_q24 = prescaled_lo_q24 / reference_frequency;
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const uint64_t prescaled_lo_q24 = vco_frequency << (24 - prescaler_divider_log2);
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const uint64_t n_divider_q24 = prescaled_lo_q24 / reference_frequency;
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return {
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lo_divider_log2,
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prescaler_divider_log2,
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n_divider_q24,
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};
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}
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return {
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lo_divider_log2,
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prescaler_divider_log2,
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n_divider_q24,
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};
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}
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};
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/* Readback values, RFFC5072 rev A:
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@ -146,136 +144,136 @@ struct SynthConfig {
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*/
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void RFFC507x::init() {
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gpio_rffc5072_resetx.set();
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gpio_rffc5072_resetx.output();
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reset();
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gpio_rffc5072_resetx.set();
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gpio_rffc5072_resetx.output();
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reset();
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_bus.init();
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_bus.init();
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_dirty.set();
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flush();
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_dirty.set();
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flush();
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}
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void RFFC507x::reset() {
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/* TODO: Is RESETB pin ignored if sdi_ctrl.sipin=1? Programming guide
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* description of sdi_ctrl.sipin suggests the pin is not ignored.
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*/
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gpio_rffc5072_resetx.clear();
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halPolledDelay(ticks_during_reset);
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gpio_rffc5072_resetx.set();
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halPolledDelay(ticks_after_reset);
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/* TODO: Is RESETB pin ignored if sdi_ctrl.sipin=1? Programming guide
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* description of sdi_ctrl.sipin suggests the pin is not ignored.
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*/
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gpio_rffc5072_resetx.clear();
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halPolledDelay(ticks_during_reset);
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gpio_rffc5072_resetx.set();
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halPolledDelay(ticks_after_reset);
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}
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void RFFC507x::flush() {
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if( _dirty ) {
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for(size_t i=0; i<_map.w.size(); i++) {
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if( _dirty[i] ) {
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write(i, _map.w[i]);
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}
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}
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_dirty.clear();
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}
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if (_dirty) {
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for (size_t i = 0; i < _map.w.size(); i++) {
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if (_dirty[i]) {
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write(i, _map.w[i]);
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}
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}
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_dirty.clear();
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}
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}
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void RFFC507x::write(const address_t reg_num, const spi::reg_t value) {
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_bus.write(reg_num, value);
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_bus.write(reg_num, value);
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}
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spi::reg_t RFFC507x::read(const address_t reg_num) {
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return _bus.read(reg_num);
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return _bus.read(reg_num);
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}
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void RFFC507x::write(const Register reg, const spi::reg_t value) {
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write(toUType(reg), value);
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write(toUType(reg), value);
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}
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spi::reg_t RFFC507x::read(const Register reg) {
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return read(toUType(reg));
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return read(toUType(reg));
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}
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void RFFC507x::flush_one(const Register reg) {
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const auto reg_num = toUType(reg);
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write(reg_num, _map.w[reg_num]);
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_dirty.clear(reg_num);
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const auto reg_num = toUType(reg);
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write(reg_num, _map.w[reg_num]);
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_dirty.clear(reg_num);
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}
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void RFFC507x::enable() {
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_map.r.sdi_ctrl.enbl = 1;
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flush_one(Register::SDI_CTRL);
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_map.r.sdi_ctrl.enbl = 1;
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flush_one(Register::SDI_CTRL);
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/* TODO: Reset PLLCPL after CT_CAL? */
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/* TODO: Reset PLLCPL after CT_CAL? */
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/* TODO: After device is enabled and CT_cal is complete and VCO > 3.2GHz,
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* change prescaler divider to 2, update synthesizer ratio, change
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* lf.pllcpl from 3 to 2.
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*/
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/* TODO: After device is enabled and CT_cal is complete and VCO > 3.2GHz,
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* change prescaler divider to 2, update synthesizer ratio, change
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* lf.pllcpl from 3 to 2.
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*/
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}
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void RFFC507x::disable() {
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_map.r.sdi_ctrl.enbl = 0;
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flush_one(Register::SDI_CTRL);
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_map.r.sdi_ctrl.enbl = 0;
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flush_one(Register::SDI_CTRL);
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}
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void RFFC507x::set_mixer_current(const uint8_t value) {
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/* MIX IDD = 0b000 appears to turn the mixer completely off */
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/* TODO: Adjust mixer current. Graphs in datasheet suggest:
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* MIX_IDD=1 has lowest noise figure (10.1dB vs 13dB @ MIX_IDD=7).
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* MIX_IDD=5 has highest IP3 (24dBm vs 10.3dBm @ MIX_IDD=1).
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* MIX_IDD=5 has highest P1dB (11.8dBm vs 1.5dBm @ MIX_IDD=1).
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* Mixer input impedance ~85 Ohms at MIX_IDD=4.
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* Mixer input impedance inversely proportional to MIX_IDD.
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* Balun balanced (mixer) side is 100 Ohms. Perhaps reduce MIX_IDD
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* a bit to get 100 Ohms from mixer.
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*/
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_map.r.mix_cont.p1mixidd = value;
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_map.r.mix_cont.p2mixidd = value;
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flush_one(Register::MIX_CONT);
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/* MIX IDD = 0b000 appears to turn the mixer completely off */
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/* TODO: Adjust mixer current. Graphs in datasheet suggest:
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* MIX_IDD=1 has lowest noise figure (10.1dB vs 13dB @ MIX_IDD=7).
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* MIX_IDD=5 has highest IP3 (24dBm vs 10.3dBm @ MIX_IDD=1).
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* MIX_IDD=5 has highest P1dB (11.8dBm vs 1.5dBm @ MIX_IDD=1).
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* Mixer input impedance ~85 Ohms at MIX_IDD=4.
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* Mixer input impedance inversely proportional to MIX_IDD.
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* Balun balanced (mixer) side is 100 Ohms. Perhaps reduce MIX_IDD
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* a bit to get 100 Ohms from mixer.
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*/
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_map.r.mix_cont.p1mixidd = value;
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_map.r.mix_cont.p2mixidd = value;
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flush_one(Register::MIX_CONT);
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}
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void RFFC507x::set_frequency(const rf::Frequency lo_frequency) {
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const SynthConfig synth_config = SynthConfig::calculate(lo_frequency);
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const SynthConfig synth_config = SynthConfig::calculate(lo_frequency);
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/* Boost charge pump leakage if VCO frequency > 3.2GHz, indicated by
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* prescaler divider set to 4 (log2=2) instead of 2 (log2=1).
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*/
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if( synth_config.prescaler_divider_log2 == 2 ) {
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_map.r.lf.pllcpl = 3;
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} else {
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_map.r.lf.pllcpl = 2;
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}
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flush_one(Register::LF);
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/* Boost charge pump leakage if VCO frequency > 3.2GHz, indicated by
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* prescaler divider set to 4 (log2=2) instead of 2 (log2=1).
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*/
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if (synth_config.prescaler_divider_log2 == 2) {
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_map.r.lf.pllcpl = 3;
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} else {
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_map.r.lf.pllcpl = 2;
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}
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flush_one(Register::LF);
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_map.r.p2_freq1.p2n = synth_config.n_divider_q24 >> 24;
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_map.r.p2_freq1.p2lodiv = synth_config.lo_divider_log2;
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_map.r.p2_freq1.p2presc = synth_config.prescaler_divider_log2;
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_map.r.p2_freq2.p2nmsb = (synth_config.n_divider_q24 >> 8) & 0xffff;
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_map.r.p2_freq3.p2nlsb = synth_config.n_divider_q24 & 0xff;
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_dirty[Register::P2_FREQ1] = 1;
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_dirty[Register::P2_FREQ2] = 1;
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_dirty[Register::P2_FREQ3] = 1;
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flush();
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_map.r.p2_freq1.p2n = synth_config.n_divider_q24 >> 24;
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_map.r.p2_freq1.p2lodiv = synth_config.lo_divider_log2;
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_map.r.p2_freq1.p2presc = synth_config.prescaler_divider_log2;
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_map.r.p2_freq2.p2nmsb = (synth_config.n_divider_q24 >> 8) & 0xffff;
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_map.r.p2_freq3.p2nlsb = synth_config.n_divider_q24 & 0xff;
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_dirty[Register::P2_FREQ1] = 1;
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_dirty[Register::P2_FREQ2] = 1;
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_dirty[Register::P2_FREQ3] = 1;
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flush();
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}
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void RFFC507x::set_gpo1(const bool new_value) {
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if( new_value ) {
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_map.r.gpo.p2gpo |= 1;
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_map.r.gpo.p1gpo |= 1;
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} else {
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_map.r.gpo.p2gpo &= ~1;
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_map.r.gpo.p1gpo &= ~1;
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}
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if (new_value) {
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_map.r.gpo.p2gpo |= 1;
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_map.r.gpo.p1gpo |= 1;
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} else {
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_map.r.gpo.p2gpo &= ~1;
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_map.r.gpo.p1gpo &= ~1;
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}
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flush_one(Register::GPO);
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flush_one(Register::GPO);
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}
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spi::reg_t RFFC507x::readback(const Readback readback) {
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/* TODO: This clobbers the rest of the DEV_CTRL register
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* Time to implement bitfields for registers.
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*/
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_map.r.dev_ctrl.readsel = toUType(readback);
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flush_one(Register::DEV_CTRL);
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/* TODO: This clobbers the rest of the DEV_CTRL register
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* Time to implement bitfields for registers.
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*/
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_map.r.dev_ctrl.readsel = toUType(readback);
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flush_one(Register::DEV_CTRL);
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return read(Register::READBACK);
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return read(Register::READBACK);
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}
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} /* namespace rffc507x */
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