portapack-mayhem/firmware/common/cpld_max5.hpp

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/*
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
*
* This file is part of PortaPack.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef __CPLD_MAX5_H__
#define __CPLD_MAX5_H__
#include "jtag.hpp"
#include "crc.hpp"
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#include <cstdint>
#include <cstddef>
#include <array>
#include <bitset>
namespace cpld {
namespace max5 {
struct Config {
const std::array<uint16_t, 3328>& block_0;
const std::array<uint16_t, 512>& block_1;
};
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class CPLD {
public:
constexpr CPLD(
jtag::JTAG& jtag)
: jtag(jtag) {
}
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void bypass();
void sample();
void sample(std::bitset<240>& value);
void extest(std::bitset<240>& value);
void clamp();
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void reset() {
jtag.reset();
}
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void run_test_idle() {
jtag.run_test_idle();
}
bool idcode_ok();
uint32_t get_idcode();
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void enable();
/* Check ID:
* The silicon ID is checked before any Program or Verify process. The
* time required to read this silicon ID is relatively small compared to
* the overall programming time.
*/
bool silicon_id_ok();
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uint32_t usercode();
void disable();
void bulk_erase();
bool program(
const std::array<uint16_t, 3328>& block_0,
const std::array<uint16_t, 512>& block_1);
bool verify(
const std::array<uint16_t, 3328>& block_0,
const std::array<uint16_t, 512>& block_1);
bool is_blank();
uint32_t crc();
std::pair<bool, uint8_t> boundary_scan();
void prepare_read(uint16_t block);
uint32_t read();
bool AGM_enter_maintenance_mode();
void AGM_exit_maintenance_mode();
void AGM_enter_read_mode();
uint32_t AGM_encode_address(uint32_t address, uint32_t trailer);
uint32_t AGM_read(uint32_t address);
private:
using idcode_t = uint32_t;
static constexpr size_t idcode_length = 32;
static constexpr idcode_t idcode = 0b00000010000010100101000011011101;
static constexpr idcode_t idcode_mask = 0b11111111111111111111111111111111;
static constexpr size_t ir_length = 10;
using ir_t = uint16_t;
enum class instruction_t : ir_t {
BYPASS = 0b1111111111, // 0x3ff
EXTEST = 0b0000001111, // 0x00f
SAMPLE = 0b0000000101, // 0x005
IDCODE = 0b0000000110, // 0x006
USERCODE = 0b0000000111, // 0x007
CLAMP = 0b0000001010, // 0x00a
HIGHZ = 0b0000001011, // 0x00b
ISC_ENABLE = 0b1011001100, // 0x2cc
ISC_DISABLE = 0b1000000001, // 0x201
ISC_PROGRAM = 0b1011110100, // 0x2f4
ISC_ERASE = 0b1011110010, // 0x2f2
ISC_ADDRESS_SHIFT = 0b1000000011, // 0x203
ISC_READ = 0b1000000101, // 0x205
ISC_NOOP = 0b1000010000, // 0x210
AGM_RESET = 0x3f7,
AGM_STAGE_1 = 0x3f8,
AGM_STAGE_2 = 0x3f9,
AGM_PROGRAM = 0x3fa,
AGM_SET_REGISTER = 0x3fc,
AGM_READ = 0x3fd,
AGM_ERASE = 0x3fe,
};
void shift_ir(const instruction_t instruction) {
shift_ir(static_cast<ir_t>(instruction));
}
void shift_ir(const uint32_t value) {
jtag.shift_ir(ir_length, value);
}
void shift_dr(std::bitset<240>& value) {
for (size_t i = 0; i < value.size(); i++) {
value[i] = shift_dr(1, value[i]);
}
}
uint32_t shift_dr(const size_t count, const uint32_t value) {
return jtag.shift_dr(count, value);
}
jtag::JTAG& jtag;
std::array<uint16_t, 5> read_silicon_id();
void sector_select(const uint16_t id);
Upstream merge to make new revision of PortaPack work (#206) * Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
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void erase_sector(const uint16_t id);
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void program_block(
const uint16_t id,
const uint16_t* const data,
const size_t count);
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template <size_t N>
void program_block(
const uint16_t id,
const std::array<uint16_t, N>& data) {
program_block(id, data.data(), data.size());
}
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bool verify_block(
const uint16_t id,
const uint16_t* const data,
const size_t count);
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template <size_t N>
bool verify_block(
const uint16_t id,
const std::array<uint16_t, N>& data) {
return verify_block(id, data.data(), data.size());
}
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bool is_blank_block(const uint16_t id, const size_t count);
using crc_t = CRC<32, true, true>;
void block_crc(const uint16_t id, const size_t count, crc_t& crc);
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};
/*
class ModeISP {
public:
ModeISP(
CPLD& cpld
) : cpld(cpld)
{
cpld.enter_isp();
}
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~ModeISP() {
cpld.exit_isp();
}
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private:
CPLD& cpld;
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};
*/
} /* namespace max5 */
} /* namespace cpld */
#endif /*__CPLD_MAX5_H__*/