portapack-mayhem/firmware/common/gpio.hpp

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2015-07-08 15:39:24 +00:00
/*
* Copyright (C) 2014 Jared Boone, ShareBrained Technology, Inc.
*
* This file is part of PortaPack.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; see the file COPYING. If not, write to
* the Free Software Foundation, Inc., 51 Franklin Street,
* Boston, MA 02110-1301, USA.
*/
#ifndef __GPIO_H__
#define __GPIO_H__
#include <cstdint>
#include "ch.h"
#include "hal.h"
struct PinConfig {
const uint32_t mode;
const uint32_t pd;
const uint32_t pu;
const uint32_t fast;
const uint32_t input;
const uint32_t ifilt;
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constexpr operator uint16_t() const {
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return
(((~ifilt) & 1) << 7)
| ((input & 1) << 6)
| ((fast & 1) << 5)
| (((~pu) & 1) << 4)
| ((pd & 1) << 3)
| ((mode & 7) << 0);
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}
/*
constexpr operator uint32_t() {
return scu::sfs::mode::value(mode)
<< scu::sfs::epd::value(pd)
<< scu::sfs::epun::value(~pu)
<< scu::sfs::ehs::value(fast)
<< scu::sfs::ezi::value(input)
<< scu::sfs::zif::value(~ifilt)
;
}
*/
static constexpr PinConfig reset() {
return { .mode = 0, .pd = 0, .pu = 1, .fast = 0, .input = 0, .ifilt = 1 };
}
static constexpr PinConfig floating(
const uint32_t mode
) {
return {
.mode = mode,
.pd = 0,
.pu = 0,
.fast = 0,
.input = 0,
.ifilt = 1
};
}
static constexpr PinConfig floating_input(
const uint32_t mode
) {
return {
.mode = mode,
.pd = 0,
.pu = 0,
.fast = 0,
.input = 1,
.ifilt = 1
};
}
static constexpr PinConfig floating_input_with_pull(
const uint32_t pull_direction,
const uint32_t mode
) {
return {
.mode = mode,
.pd = (pull_direction == 0) ? 1U : 0U,
.pu = (pull_direction == 1) ? 1U : 0U,
.fast = 0,
.input = 1,
.ifilt = 1
};
}
static constexpr PinConfig gpio_led(const uint32_t mode) {
return { .mode = mode, .pd = 0, .pu = 0, .fast = 0, .input = 0, .ifilt = 1 };
}
static constexpr PinConfig gpio_inout_with_pull(
const uint32_t mode,
const uint32_t pull_direction
) {
return {
.mode = mode,
.pd = (pull_direction == 0) ? 1U : 0U,
.pu = (pull_direction == 1) ? 1U : 0U,
.fast = 0,
.input = 1,
.ifilt = 1
};
}
static constexpr PinConfig gpio_inout_with_pullup(const uint32_t mode) {
return gpio_inout_with_pull(mode, 1);
}
static constexpr PinConfig gpio_inout_with_pulldown(const uint32_t mode) {
return gpio_inout_with_pull(mode, 0);
}
static constexpr PinConfig gpio_out_with_pull(
const uint32_t mode,
const uint32_t pull_direction
) {
return {
.mode = mode,
.pd = (pull_direction == 0) ? 1U : 0U,
.pu = (pull_direction == 1) ? 1U : 0U,
.fast = 0,
.input = 0,
.ifilt = 1
};
}
static constexpr PinConfig gpio_out_with_pulldown(const uint32_t mode) {
return gpio_out_with_pull(mode, 0);
}
static constexpr PinConfig gpio_out_with_pullup(const uint32_t mode) {
return gpio_out_with_pull(mode, 1);
}
static constexpr PinConfig sgpio_in_fast(const uint32_t mode) {
return { .mode = mode, .pd = 0, .pu = 0, .fast = 0, .input = 1, .ifilt = 0 };
}
static constexpr PinConfig sgpio_out_fast_with_pull(
const uint32_t mode,
const uint32_t pull_direction
) {
return {
.mode = mode,
.pd = (pull_direction == 0) ? 1U : 0U,
.pu = (pull_direction == 1) ? 1U : 0U,
.fast = 1,
.input = 0,
.ifilt = 1
};
}
static constexpr PinConfig sgpio_out_fast_with_pullup(const uint32_t mode) {
return sgpio_out_fast_with_pull(mode, 1);
}
static constexpr PinConfig sgpio_inout_fast(const uint32_t mode) {
return { .mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 1, .ifilt = 0 };
}
static constexpr PinConfig i2c(const uint32_t mode) {
return { .mode = mode, .pd = 0, .pu = 0, .fast = 0, .input = 1, .ifilt = 1 };
}
Upstream merge to make new revision of PortaPack work (#206) * Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
2019-01-11 06:56:21 +00:00
static constexpr PinConfig spifi_sck(const uint32_t mode ) {
return { .mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 1, .ifilt = 0 };
}
static constexpr PinConfig spifi_inout(const uint32_t mode) {
return { .mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 1, .ifilt = 0 };
}
static constexpr PinConfig spifi_cs(const uint32_t mode) {
return { .mode = mode, .pd = 0, .pu = 0, .fast = 1, .input = 0, .ifilt = 0 };
}
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};
struct Pin {
// Pin() = delete;
// Pin(const Pin&) = delete;
// Pin(Pin&&) = delete;
constexpr Pin(
const uint8_t port,
const uint8_t pad,
const PinConfig initial_config
) : _pin_port { port },
_pin_pad { pad },
_initial_config { initial_config }
{
}
/*
constexpr Pin(
const Pin& pin
) : _pin_port { pin._pin_port },
_pin_pad { pin._pin_pad },
_initial_config { pin._initial_config }
{
}
*/
void init() const {
LPC_SCU->SFSP[_pin_port][_pin_pad] = _initial_config;
}
void mode(const uint_fast16_t mode) const {
LPC_SCU->SFSP[_pin_port][_pin_pad] =
Upstream merge to make new revision of PortaPack work (#206) * Power: Turn off additional peripheral clock branches. * Update schematic with new symbol table and KiCad standard symbols. Fix up wires. * Schematic: Update power net labels. * Schematic: Update footprint names to match library changes. * Schematic: Update header vendor and part numbers. * Schematic: Specify (arbitrary) value for PDN# net. * Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space. * Schematic: Add reference oscillator -- options for clipped sine or HCMOS output. * Schematic: Update copyright year. * Schematic: Remove CLKOUT to CPLD. It was a half-baked idea. * Schematic: Add (experimental) GPS circuit. Add note about charging circuit. Update date and revision to match PCB. * PCB: Update from schematic change: now revision 20180819. Diff was extensive due to net renumbering... * PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual. PCB: Address DRC clearance violation between via and oscillator pad. * PCB: Update copyright on drawing. * Update schematic and PCB date and revision. * gitignore: Sublime Text editor project/workspace files * Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze... * Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field. * LPC43xx: Add CGU IDIVx struct/union type. * Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use. * HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02) * MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class. * MAX V CPLD: Add BYPASS, SAMPLE support. Rename enter_isp -> enable, exit_isp -> disable. Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing. * MAX V CPLD: Reverse verify data checking logic to make it a little faster. * CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream. * Si5351: Refactor code, make one of the registers more type-safe. Clock Manager: Track selected reference clock source for later use in user interface. * Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal. It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise... * PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external. * CPLD: Add pins and logic for new PortaPack hardware feature(s). * CPLD: Bitstream to support new hardware features. * Clock Generator: Add a couple more setter methods for ClockControl registers. * Clock Manager: Use shared MCU CLKIN clock control configuration constant. * Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty. * Clock Manager: Remove redundant clock generator output enable. * Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM. * Bootstrap: Get CPU operating at max frequency as soon as possible. Update SPIFI speed comment. Make some more LPC43xx types into unions with uint32_t. * Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it. * Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream. * Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated. * Bootstrap: Consolidate clock configuration, update SPIFI rate comment. * Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward. Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out... * ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution. * PortaPack IO: Expose method to set reference oscillator enable pin. * Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader. * Pin configuration: Disable input buffers on pins that are never read. * Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution." This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03. * Remove unused board files. * Add LPC43xx functions. * chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits. * LPC43xx: Add MCPWM peripheral struct. * clock generator: Use recommended PLL reset register value. Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000. * GPIO: Tweak masking of SCU function. I don't remember why I thought this was necessary... * HAL: Explicitly turn on timer peripheral clocks used as systicks, during init. * SCU: Add struct to hold pin configuration. * PAL: Add functions to address The Glitch. https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/ * PAL/board: New IO initialization code Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch. * Merge M0 and M4 to eliminate need for bootstrap firmware During _early_init, detect if we're running on the M4 or M0. If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep. If M0: do all the other things. * Pins: Miscellaneous SCU configuration tweaks. * Little code clarity improvement. * bootstrap: Remove, not necessary. * Clock Manager: Large re-working to support external references. * Fix merge conflicts
2019-01-11 06:56:21 +00:00
(LPC_SCU->SFSP[_pin_port][_pin_pad] & 0xfffffff8) | mode;
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}
void configure(const PinConfig config) const {
LPC_SCU->SFSP[_pin_port][_pin_pad] = config;
}
uint8_t _pin_port;
uint8_t _pin_pad;
uint16_t _initial_config;
};
struct GPIO {
// GPIO() = delete;
// GPIO(const GPIO& gpio) = delete;
// GPIO(GPIO&&) = delete;
constexpr GPIO(
const Pin& pin,
const ioportid_t gpio_port,
const iopadid_t gpio_pad,
const uint16_t gpio_mode
) : _pin { pin },
_gpio_port { gpio_port },
_gpio_pad { gpio_pad },
_gpio_mode { gpio_mode }
{
}
/*
constexpr GPIO(
const GPIO& gpio
) : _pin { gpio._pin },
_gpio_port { gpio._gpio_port },
_gpio_pad { gpio._gpio_pad },
_gpio_mode { gpio._gpio_mode }
{
}
*/
constexpr ioportid_t port() const {
return _gpio_port;
}
constexpr iopadid_t pad() const {
return _gpio_pad;
}
constexpr Pin pin() const {
return _pin;
}
void configure() const {
_pin.mode(_gpio_mode);
}
uint_fast16_t mode() const {
return _gpio_mode;
}
void set() const {
palSetPad(_gpio_port, _gpio_pad);
}
void clear() const {
palClearPad(_gpio_port, _gpio_pad);
}
void toggle() const {
palTogglePad(_gpio_port, _gpio_pad);
}
void output() const {
palSetPadMode(_gpio_port, _gpio_pad, PAL_MODE_OUTPUT_PUSHPULL);
}
void input() const {
palSetPadMode(_gpio_port, _gpio_pad, PAL_MODE_INPUT);
}
void write(const bool value) const {
palWritePad(_gpio_port, _gpio_pad, value);
}
bool read() const {
return palReadPad(_gpio_port, _gpio_pad);
}
bool operator!=(const GPIO& other) const {
return (port() != other.port()) || (pad() != other.pad());
}
const Pin _pin;
const ioportid_t _gpio_port;
const iopadid_t _gpio_pad;
const uint16_t _gpio_mode;
};
#endif/*__GPIO_H__*/