Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 01:56:21 -05:00
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EESchema Schematic File Version 4
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LIBS:portapack_h1-cache
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EELAYER 26 0
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EELAYER END
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$Descr A4 11693 8268
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encoding utf-8
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Sheet 6 6
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Title "PortaPack H1"
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PortaPack Sync, take 2 (#215)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* PCB: Change PCB stackup, Tg, clarify solder mask color, use more metric.
* PCB: Move HackRF header P9 to B.CrtYd layer.
* PCB: Change a Tg reference I missed.
* PCB: Update footprints for parts with mismatched CAD->tape rotation.
Adjust a few layer choice and line thickness bits.
* PCB: Got cold feet, switched back to rectangular pads.
* PCB: Add Eco layers to be visible and Gerber output.
* PCB: Use aux origin for plotting, for tidier coordinates.
* PCB: Output Gerber job file, because why not?
* Schematic: Correct footprints for two reference-related components.
* Schematic: Remove manfuacturer and part number for DNP component.
* Schematic: Specify resistor value, manufacturer, part number for reference oscillator series termination.
* PCB: Update netlist and footprints from schematic.
* Netlist: Updated component values, footprints.
* PCB: Nudge some components and traces to address DRC clearance violations.
* PCB: Allow KiCad to update zone timestamps (again?!).
* PCB: Generate *all* Gerber layers.
* Schematic, PCB: Update revision to 20181025.
* PCB: Adjust fab layer annotations orientation and font size.
* PCB: Hide mounting hole reference designators on silk layer.
* PCB: Shrink U1, U3 pads to get 0.2mm space between pads.
* PCB: Set pad-to-mask clearance to zero, leave up to fab. Set minimum mask web to 0.2mm for non-black options.
* PCB: Revise U1 pad shape, mask, paste, thermal drills.
Clearance is improved at corner pads.
* PCB: Tweak U3 for better thermal pad/drill/mask/paste design.
* PCB: Change solder mask color to blue.
* Schematic, PCB: Update revision to 20181029.
* PCB: Bump minimum mask web down a tiny bit because KiCad is having trouble with math.
* Update schematic
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Clock Manager: Actually store chosen clock reference
Similarly-named local was covering a member and discarding the value.
* Clock Manager: Reference type which contains source, frequency.
* Setup: Display reference source, frequency in frequency correction screen.
* LPC43xx API: Add extern "C" for use from C++.
* Use LPC43xx API for SGPIO, GPDMA, I2S initialization.
* I2S: Add BASE_AUDIO_CLK management.
* Add MOTOCON_PWM clock/reset structure.
* Serial: Fix dumb typos.
* Serial: Remove extra reference operator.
* Serial: Cut-and-paste error in structure type name.
* Move SCU structure from PAL to LPC43xx API.
It'd be nice if I gave some thought to where code should live before I commit it.
* VAA power: Move code to HackRF board file
It doesn't belong in PAL.
* MAX5 CPLD: Add SAMPLE and EXTEST methods.
* Flash image: Change packing scheme to use flash more efficiently.
Application is now a single image for both M4 bootstrap and M0.
Baseband images come immediately after application binary. No need to align to large blocks (and waste lots of flash).
* Clock Manager: Remove PLL1 power down function.
* Move and rename peripherals reset function to board module.
* Remove unused peripheral/clock management.
* Clock Manager: Extract switch to IRC into separate function.
* Clock Manager: More explicit shutdown of clocks, clock generator.
* Move initialization to board module.
* ChibiOS: Rename "application" board, add "baseband" board.
There are now two ChibiOS "boards", one which runs the application and does the hardware setup. The other board, "baseband", does very little setup.
* Clock Manager: Remove unused crystal enable/disable code.
* Clock Manager: Restore clock configuration to SPIFI bootloader state before app shutdown.
* Reset peripherals on app shutdown.
Be careful not to reset M0APP (the core we're running on) or GPIO (which is holding the hardware in a stable state).
* M4/baseband hal_lld_init: use IDIVA, which is configured earlier by M0.
This was causing problems during restart into HackRF mode. Baseband hal_lld_init changed M4 clock from IDIVA (set by M0) to PLL1, which was unceremoniously turned off during shutdown.
* Audio app: Stop audio PLL on shutdown.
* M4 HAL: Make LPC43XX_M4_CLK_SRC optional.
This was changing the BASE_M4_CLK when a baseband was run.
* LPC43xx C++ layer: Fix IDIVx constructor IDIV narrow field width.
* Application board: hide the peripherals_reset function, as it isn't useful except during hardware init.
* Consolidate hardware init code to some degree.
ClockManager is super-overloaded and murky in its purpose.
Migrate audio from IDIVC to IDIVD, to more closely resemble initial clock scheme, so it's simpler to get back to it during shutdown.
* Migrate some startup code to application board.
* Si5351: Use correct methods for reset().
update_output_enable_control() doesn't reset the enabled outputs to the reset state, unless the object is freshly initialized, which it isn't when performing firmware shutdown.
For similar reasons, use set_clock_control() instead of setting internal state and then using the update function.
* GPIO: Set SPIFI CS pin to match input buffer state coming out of bootloader.
* Change application board.c to .cpp, with required dependent changes
* Board: Clean up SCU configuration code/data.
* I2S: Add shutdown code and use it.
* LPC43xx: Consolidate a bunch of structures that had been scattered all over.
...because I'm an undisciplined coder.
* I2S: Fix ordering of branch and base clock disable.
Core was hanging, presumably because the register interface on the branch/peripheral was unresponsive after the base clock was disabled.
* Controls: Save and expose raw navigation wheel switch state
I need to do some work on debouncing and ignoring simultaneous key presses.
* Controls: Add debug view for switches state.
* Controls: Ignore all key presses until all keys are released.
This should address some mechanical quirks of the navigation wheel used on the PortaPack.
* Clock Manager: Wait for only the necessary PLL to lock.
Wasn't working on PortaPacks without a built-in clock reference, as that uses the other PLL.
TODO: Switching PLLs may be kind of pointless now...
* CMake: Pull HackRF project from GitHub and build.
* CMake: Remove commented code.
* CMake: Clone HackRF via HTTPS, not SSH.
* CMake: Extra pause for slow post-DFU firmware boot-up.
* CMake: TODO to fix SVF/XSVF file source.
* CMake: Ask HackRF hackrf_usb to make DFU binary.
* Travis-CI: Add dfu-util, now that HackRF firmware is being built for inclusion.
* Travis-CI: Update build environment to Ubuntu xenial
Previously Trusty.
* Travis-CI: Incorrectly structured my request for dfu-util package.
I'm soooo talented.
* ldscript: Mark flash, ram with correct R/W/X flags.
* ldscript: Enlarge M0 flash region to 1Mbyte, the size of the HackRF SPI flash.
* Receiver: Hide PPM adjustment if clock source is not HackRF crystal.
* Documentation: Update product photos and README.
* Documentation: Add TCXO feature to README description.
* Application: Rearrange files to match HAVOC directory structure.
* Map view in AIS (#213)
* Added GeoMapView to AISRecentEntryDetailView
* Added autoupdate in AIS map
* Revert "Map view in AIS (#213)"
This reverts commit 262c030224b9ea3e56ff1c8a66246e7ecf30e41f.
This commit will be cherry-picked onto a clean branch, then re-committed after a troublesome pull request is reverted.
* Revert "Upstream merge to make new revision of PortaPack work (#206)"
This reverts commit 920b98f7c9a30371b643c42949066fb7d2441daf.
This pull request was missing some changes and was preventing firmware from functioning on older PortaPacks.
* CPLD: Pull bitstream from HackRF project.
* SGPIO: Identify pins on CPLD by their new functions. Pull down HOST_SYNC_EN.
* CPLD: Don't load HackRF CPLD bitstream into RAM.
Trying to converge CPLD implementations, so this shouldn't be necesssary. HOWEVER, it would be good to *check* the CPLD contents and provide a way to update, if necessary.
* CPLD: Tweak clock generator config to match CPLD timing changes in HackRF.
* PinConfig: Drive CPLD pins correctly.
* CMake: Use jboone/hackrf master branch, now that CPLD fixes are there.
* CMake: Fix HackRF CPLD SVF dependency.
Build would break on the first pass, but work if you restarted make.
* CMake: Fix my misuse of the HackRF CMake configuration -- was building from too deep in the directory tree
* CMake: Work-around for CMake 3.5 not supporting ExternalProject_Add SOURCE_SUBDIR.
* CMake: Choose a CMP0005 policy to quiet CMake warnings.
* Settings: Show active clock reference. Only show PPM adjustment for HackRF source.
* Radio Settings: Change reference clock text color.
Make consistent color with other un-editable text.
TODO: This is a bit of a hack to get ui::Text objects to support custom colors, like the Label structures used elsewhere.
2019-02-03 13:25:11 -05:00
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Date "2018-10-29"
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Rev "20181029"
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Upstream merge to make new revision of PortaPack work (#206)
* Power: Turn off additional peripheral clock branches.
* Update schematic with new symbol table and KiCad standard symbols.
Fix up wires.
* Schematic: Update power net labels.
* Schematic: Update footprint names to match library changes.
* Schematic: Update header vendor and part numbers.
* Schematic: Specify (arbitrary) value for PDN# net.
* Schematic: Remove fourth fiducial. Not standard practice, and was taking up valuable board space.
* Schematic: Add reference oscillator -- options for clipped sine or HCMOS output.
* Schematic: Update copyright year.
* Schematic: Remove CLKOUT to CPLD. It was a half-baked idea.
* Schematic: Add (experimental) GPS circuit.
Add note about charging circuit.
Update date and revision to match PCB.
* PCB: Update from schematic change: now revision 20180819.
Diff was extensive due to net renumbering...
* PCB: Fix GPS courtyard to accommodate crazy solder paste recommendation in integration manual.
PCB: Address DRC clearance violation between via and oscillator pad.
* PCB: Update copyright on drawing.
* Update schematic and PCB date and revision.
* gitignore: Sublime Text editor project/workspace files
* Power: Power up or power down peripheral clock at appropriate times, so firmware doesn't freeze...
* Clocking: Fix incorrect shift for CGU IDIVx_CTRL.PD field.
* LPC43xx: Add CGU IDIVx struct/union type.
* Power: Switch off unused IDIV dividers. Make note of active IDIVs and their use.
* HackRF Mode: Upgrade firmware to 2018.01.1 (API 1.02)
* MAX V CPLD: Refactor class to look more like Xilinx CoolRunner II CPLD class.
* MAX V CPLD: Add BYPASS, SAMPLE support.
Rename enter_isp -> enable, exit_isp -> disable.
Use SAMPLE at start of flash process, which somehow addresses the problem where CFM wouldn't load into SRAM (and become the active bitstream) after flashing.
* MAX V CPLD: Reverse verify data checking logic to make it a little faster.
* CPLD: After reprogramming flash, immediately clamp I/O signals, load to SRAM, and "execute" the new bitstream.
* Si5351: Refactor code, make one of the registers more type-safe.
Clock Manager: Track selected reference clock source for later use in user interface.
* Clock Manager: Add note about PPM only affecting Si5351C PLLA, which always runs from the HackRF 25MHz crystal.
It is assumed an external clock does not need adjustment, though I am open to being convinced otherwise...
* PPM UI: Show "EXT" when showing PPM adjustment and reference clock is external.
* CPLD: Add pins and logic for new PortaPack hardware feature(s).
* CPLD: Bitstream to support new hardware features.
* Clock Generator: Add a couple more setter methods for ClockControl registers.
* Clock Manager: Use shared MCU CLKIN clock control configuration constant.
* Clock Manager: Reduce MCU CLKIN driver current. 2mA should be plenty.
* Clock Manager: Remove redundant clock generator output enable.
* Bootstrap: Remove unnecessary ldscript hack to locate SPIFI mode change code in RAM.
* Bootstrap: Get CPU operating at max frequency as soon as possible.
Update SPIFI speed comment.
Make some more LPC43xx types into unions with uint32_t.
* Bootstrap: Explicitly configure IDIVB for SPIFI, despite LPC43xx bootloader setting it.
* Clock Manager: Init peripherals before CPLD reconfig. Do the clock generator setup after, so we can check presence of PortaPack reference clock with the help of the latest CPLD bitstream.
* Clock Manager: Reverse sense of conditional that determines crystal or non-crystal reference source. This is for an expected upcoming change where multiple external options can be differentiated.
* Bootstrap: Consolidate clock configuration, update SPIFI rate comment.
* Clock Manager: Use IDIVA for clock source for all peripherals, instead of PLL1. Should make switching easier going forward.
Don't use IRC as clock during initial clock manager configuration. Until we switch to GP_CLKIN, we should go flat out...
* ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution.
* PortaPack IO: Expose method to set reference oscillator enable pin.
* Pin configuration: Do SPIFI pin config with other pins, in preparation for eliminating separate bootloader.
* Pin configuration: Disable input buffers on pins that are never read.
* Revert "ChibiOS M0: Change default clock speed to 204MHz, since bootstrap now maxes out clock speed before starting M0 execution."
This reverts commit c0e2bb6cc4cc656769323bdbb8ee5a16d2d5bb03.
* Remove unused board files.
* Add LPC43xx functions.
* chibios: Replace code with per-peripheral structs defining clocks, interrupts, and reset bits.
* LPC43xx: Add MCPWM peripheral struct.
* clock generator: Use recommended PLL reset register value.
Datasheet recommends a value. AN619 is quiet on the topic, claims the low nibble is default 0b0000.
* GPIO: Tweak masking of SCU function.
I don't remember why I thought this was necessary...
* HAL: Explicitly turn on timer peripheral clocks used as systicks, during init.
* SCU: Add struct to hold pin configuration.
* PAL: Add functions to address The Glitch.
https://greatscottgadgets.com/2018/02-28-we-fixed-the-glitch/
* PAL/board: New IO initialization code
Declare initial state for SCU pin config, GPIOs. Apply initial state during PAL init. Perform VAA slow turn-on to address The Glitch.
* Merge M0 and M4 to eliminate need for bootstrap firmware
During _early_init, detect if we're running on the M4 or M0.
If M4: do M4-specific core initialization, reset peripherals, speed up SPIFI clock, start M0, go to sleep.
If M0: do all the other things.
* Pins: Miscellaneous SCU configuration tweaks.
* Little code clarity improvement.
* bootstrap: Remove, not necessary.
* Clock Manager: Large re-working to support external references.
* Fix merge conflicts
2019-01-11 01:56:21 -05:00
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Comp "ShareBrained Technology, Inc."
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Comment1 "Copyright © 2014-2018 Jared Boone"
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Comment2 "License: GNU General Public License, version 2"
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Comment3 ""
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Comment4 ""
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$EndDescr
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$Comp
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L ublox:MAX-M8 U8
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F 4 "DNP" H 5800 3450 50 0000 C CNN "DNP"
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1 0 0 -1
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$EndComp
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$Comp
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L Device:C C19
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U 1 1 5B7E0D14
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P 4600 3450
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F 0 "C19" V 4250 3450 50 0000 C CNN
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F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 4638 3300 50 0001 C CNN
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F 4 "DNP" V 4450 3450 50 0000 C CNN "DNP"
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|
|
1 4600 3450
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L Device:L L1
|
|
|
|
|
U 1 1 5B7E0E02
|
|
|
|
|
P 4350 2900
|
|
|
|
|
F 0 "L1" H 4403 2946 50 0000 L CNN
|
|
|
|
|
F 1 "27N" H 4403 2855 50 0000 L CNN
|
|
|
|
|
F 2 "ipc_indc:IPC_INDC100X50X60L20N" H 4350 2900 50 0001 C CNN
|
|
|
|
|
F 3 "~" H 4350 2900 50 0001 C CNN
|
|
|
|
|
F 4 "DNP" H 4450 2750 50 0000 C CNN "DNP"
|
|
|
|
|
1 4350 2900
|
|
|
|
|
0 -1 -1 0
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L power:GND #PWR0108
|
|
|
|
|
U 1 1 5B7E0F42
|
|
|
|
|
P 4600 3700
|
|
|
|
|
F 0 "#PWR0108" H 4600 3450 50 0001 C CNN
|
|
|
|
|
F 1 "GND" H 4605 3527 50 0000 C CNN
|
|
|
|
|
F 2 "" H 4600 3700 50 0001 C CNN
|
|
|
|
|
F 3 "" H 4600 3700 50 0001 C CNN
|
|
|
|
|
1 4600 3700
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L power:GND #PWR0109
|
|
|
|
|
U 1 1 5B7E0F5A
|
|
|
|
|
P 5100 3400
|
|
|
|
|
F 0 "#PWR0109" H 5100 3150 50 0001 C CNN
|
|
|
|
|
F 1 "GND" H 5105 3227 50 0000 C CNN
|
|
|
|
|
F 2 "" H 5100 3400 50 0001 C CNN
|
|
|
|
|
F 3 "" H 5100 3400 50 0001 C CNN
|
|
|
|
|
1 5100 3400
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5200 2500 5100 2500
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5100 2500 5100 2700
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5200 2700 5100 2700
|
|
|
|
|
Connection ~ 5100 2700
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5100 2700 5100 3000
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5200 2600 4100 2600
|
|
|
|
|
Text HLabel 3200 3100 0 60 BiDi ~ 0
|
|
|
|
|
SDA
|
|
|
|
|
Text HLabel 3200 3500 0 60 BiDi ~ 0
|
|
|
|
|
SCL
|
|
|
|
|
$Comp
|
|
|
|
|
L power:GND #PWR0110
|
|
|
|
|
U 1 1 5B7E1247
|
|
|
|
|
P 6500 3400
|
|
|
|
|
F 0 "#PWR0110" H 6500 3150 50 0001 C CNN
|
|
|
|
|
F 1 "GND" H 6505 3227 50 0000 C CNN
|
|
|
|
|
F 2 "" H 6500 3400 50 0001 C CNN
|
|
|
|
|
F 3 "" H 6500 3400 50 0001 C CNN
|
|
|
|
|
1 6500 3400
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 3300 6500 3300
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6500 3300 6500 3400
|
|
|
|
|
Text HLabel 7800 1800 2 60 Input ~ 0
|
|
|
|
|
V_BACKUP
|
|
|
|
|
Text HLabel 6650 1800 0 60 Input ~ 0
|
|
|
|
|
VCC
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 2600 6800 2600
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 2700 6800 2700
|
|
|
|
|
$Comp
|
|
|
|
|
L tp:TP TP7
|
|
|
|
|
U 1 1 5B7E1777
|
|
|
|
|
P 4900 3300
|
|
|
|
|
F 0 "TP7" H 4750 3300 50 0000 C CNN
|
|
|
|
|
F 1 "TP" H 4900 3300 50 0001 C CNN
|
|
|
|
|
F 2 "tp:TP_1MM" H 4900 3300 60 0001 C CNN
|
|
|
|
|
F 3 "" H 4900 3300 60 0001 C CNN
|
|
|
|
|
1 4900 3300
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5000 3300 5200 3300
|
|
|
|
|
Text HLabel 6900 3000 2 60 Output ~ 0
|
|
|
|
|
TIMEPULSE
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 3000 6900 3000
|
|
|
|
|
$Comp
|
|
|
|
|
L tp:TP TP8
|
|
|
|
|
U 1 1 5B7E20D6
|
|
|
|
|
P 7000 2900
|
|
|
|
|
F 0 "TP8" H 6850 2900 50 0000 C CNN
|
|
|
|
|
F 1 "TP" H 7000 2900 50 0001 C CNN
|
|
|
|
|
F 2 "tp:TP_1MM" H 7000 2900 60 0001 C CNN
|
|
|
|
|
F 3 "" H 7000 2900 60 0001 C CNN
|
|
|
|
|
1 7000 2900
|
|
|
|
|
-1 0 0 1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 2900 6900 2900
|
|
|
|
|
$Comp
|
|
|
|
|
L tp:TP TP9
|
|
|
|
|
U 1 1 5B7E27BE
|
|
|
|
|
P 7000 3100
|
|
|
|
|
F 0 "TP9" H 6850 3100 50 0000 C CNN
|
|
|
|
|
F 1 "TP" H 7000 3100 50 0001 C CNN
|
|
|
|
|
F 2 "tp:TP_1MM" H 7000 3100 60 0001 C CNN
|
|
|
|
|
F 3 "" H 7000 3100 60 0001 C CNN
|
|
|
|
|
1 7000 3100
|
|
|
|
|
-1 0 0 1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 3100 6900 3100
|
|
|
|
|
Text HLabel 7800 2500 2 60 Input ~ 0
|
|
|
|
|
RESET#
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 2500 7700 2500
|
|
|
|
|
$Comp
|
|
|
|
|
L Device:C C20
|
|
|
|
|
U 1 1 5B7E512B
|
|
|
|
|
P 6800 3450
|
|
|
|
|
F 0 "C20" H 6915 3496 50 0000 L CNN
|
|
|
|
|
F 1 "100N" H 6915 3405 50 0000 L CNN
|
|
|
|
|
F 2 "ipc_capc:IPC_CAPC100X50X55L25N" H 6838 3300 50 0001 C CNN
|
|
|
|
|
F 3 "~" H 6800 3450 50 0001 C CNN
|
|
|
|
|
F 4 "DNP" H 7000 3300 50 0000 C CNN "DNP"
|
|
|
|
|
1 6800 3450
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L power:GND #PWR0111
|
|
|
|
|
U 1 1 5B7E5197
|
|
|
|
|
P 6800 3700
|
|
|
|
|
F 0 "#PWR0111" H 6800 3450 50 0001 C CNN
|
|
|
|
|
F 1 "GND" H 6805 3527 50 0000 C CNN
|
|
|
|
|
F 2 "" H 6800 3700 50 0001 C CNN
|
|
|
|
|
F 3 "" H 6800 3700 50 0001 C CNN
|
|
|
|
|
1 6800 3700
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6800 3600 6800 3700
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6800 2700 6800 2600
|
|
|
|
|
$Comp
|
|
|
|
|
L Device:R R25
|
|
|
|
|
U 1 1 5B7E62C8
|
|
|
|
|
P 7700 2750
|
|
|
|
|
F 0 "R25" H 7770 2796 50 0000 L CNN
|
|
|
|
|
F 1 "100K" V 7700 2650 50 0000 L CNN
|
|
|
|
|
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 7630 2750 50 0001 C CNN
|
|
|
|
|
F 3 "~" H 7700 2750 50 0001 C CNN
|
|
|
|
|
F 4 "DNP" H 7850 2700 50 0000 C CNN "DNP"
|
|
|
|
|
1 7700 2750
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L power:GND #PWR0112
|
|
|
|
|
U 1 1 5B7E633A
|
|
|
|
|
P 7700 3000
|
|
|
|
|
F 0 "#PWR0112" H 7700 2750 50 0001 C CNN
|
|
|
|
|
F 1 "GND" H 7705 2827 50 0000 C CNN
|
|
|
|
|
F 2 "" H 7700 3000 50 0001 C CNN
|
|
|
|
|
F 3 "" H 7700 3000 50 0001 C CNN
|
|
|
|
|
1 7700 3000
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
7700 2600 7700 2500
|
|
|
|
|
Connection ~ 7700 2500
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
7700 2500 7800 2500
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
7700 2900 7700 3000
|
|
|
|
|
$Comp
|
|
|
|
|
L passive:FBEAD FB1
|
|
|
|
|
U 1 1 5B7E9718
|
|
|
|
|
P 3550 3100
|
|
|
|
|
F 0 "FB1" H 3550 3300 50 0000 C CNN
|
|
|
|
|
F 1 "FBEAD" H 3544 3227 50 0001 C CNN
|
|
|
|
|
F 2 "ipc_beadc:IPC_BEADC160X80X95L40N" H 3544 3234 60 0001 C CNN
|
|
|
|
|
F 3 "" H 3550 3100 60 0000 C CNN
|
|
|
|
|
F 4 "DNP" H 3550 3200 50 0000 C CNN "DNP"
|
|
|
|
|
F 5 "Murata" H 0 0 50 0001 C CNN "Mfr"
|
|
|
|
|
F 6 "BLM18HE152SN1D" H 0 0 50 0001 C CNN "Part"
|
|
|
|
|
1 3550 3100
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L passive:FBEAD FB3
|
|
|
|
|
U 1 1 5B7E9798
|
|
|
|
|
P 3550 3500
|
|
|
|
|
F 0 "FB3" H 3550 3700 50 0000 C CNN
|
|
|
|
|
F 1 "FBEAD" H 3544 3627 50 0001 C CNN
|
|
|
|
|
F 2 "ipc_beadc:IPC_BEADC160X80X95L40N" H 3550 3500 60 0001 C CNN
|
|
|
|
|
F 3 "" H 3550 3500 60 0000 C CNN
|
|
|
|
|
F 4 "DNP" H 3550 3600 50 0000 C CNN "DNP"
|
|
|
|
|
F 5 "Murata" H 0 0 50 0001 C CNN "Mfr"
|
|
|
|
|
F 6 "BLM18HE152SN1D" H 0 0 50 0001 C CNN "Part"
|
|
|
|
|
1 3550 3500
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
3200 3100 3300 3100
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
3200 3500 3300 3500
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
3800 3500 3900 3500
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
3900 3500 3900 3200
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
3900 3200 5200 3200
|
|
|
|
|
$Comp
|
|
|
|
|
L Device:R R24
|
|
|
|
|
U 1 1 5B7EC300
|
|
|
|
|
P 7550 1800
|
|
|
|
|
F 0 "R24" V 7450 1800 50 0000 C CNN
|
|
|
|
|
F 1 "0R" V 7550 1800 50 0000 C CNN
|
|
|
|
|
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 7480 1800 50 0001 C CNN
|
|
|
|
|
F 3 "~" H 7550 1800 50 0001 C CNN
|
|
|
|
|
F 4 "DNP" V 7650 1800 50 0000 C CNN "DNP"
|
|
|
|
|
1 7550 1800
|
|
|
|
|
0 1 1 0
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L Device:R R23
|
|
|
|
|
U 1 1 5B7ED5AD
|
|
|
|
|
P 7050 1800
|
|
|
|
|
F 0 "R23" V 6950 1800 50 0000 C CNN
|
|
|
|
|
F 1 "0R" V 7050 1800 50 0000 C CNN
|
|
|
|
|
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 6980 1800 50 0001 C CNN
|
|
|
|
|
F 3 "~" H 7050 1800 50 0001 C CNN
|
|
|
|
|
F 4 "DNP" V 7150 1800 50 0000 C CNN "DNP"
|
|
|
|
|
1 7050 1800
|
|
|
|
|
0 1 1 0
|
|
|
|
|
$EndComp
|
|
|
|
|
NoConn ~ 5200 2800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5200 3000 5100 3000
|
|
|
|
|
Connection ~ 5100 3000
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5100 3000 5100 3400
|
|
|
|
|
Text HLabel 6900 3200 2 60 Output ~ 0
|
|
|
|
|
TX_READY
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 3200 6900 3200
|
|
|
|
|
$Comp
|
|
|
|
|
L conn_rf:CONN_COAX P1
|
|
|
|
|
U 1 1 5B78522B
|
|
|
|
|
P 2550 2600
|
|
|
|
|
F 0 "P1" H 2505 2844 60 0000 C CNN
|
|
|
|
|
F 1 "CONN_COAX" H 2505 2829 40 0001 C CNN
|
|
|
|
|
F 2 "amp_te:1909763-1" H 2505 2754 60 0001 C CNN
|
|
|
|
|
F 3 "" H 2550 2600 60 0000 C CNN
|
|
|
|
|
F 4 "DNP" H 2505 2746 50 0000 C CNN "DNP"
|
|
|
|
|
F 5 "AMP/TE" H 0 0 50 0001 C CNN "Mfr"
|
|
|
|
|
F 6 "1909763-1" H 0 0 50 0001 C CNN "Part"
|
|
|
|
|
1 2550 2600
|
|
|
|
|
-1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
$Comp
|
|
|
|
|
L power:GND #PWR0113
|
|
|
|
|
U 1 1 5B7852CC
|
|
|
|
|
P 2550 2900
|
|
|
|
|
F 0 "#PWR0113" H 2550 2650 50 0001 C CNN
|
|
|
|
|
F 1 "GND" H 2555 2727 50 0000 C CNN
|
|
|
|
|
F 2 "" H 2550 2900 50 0001 C CNN
|
|
|
|
|
F 3 "" H 2550 2900 50 0001 C CNN
|
|
|
|
|
1 2550 2900
|
|
|
|
|
1 0 0 -1
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
2550 2800 2550 2900
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
3800 3100 5200 3100
|
|
|
|
|
$Comp
|
|
|
|
|
L Device:R R26
|
|
|
|
|
U 1 1 5B78A3E5
|
|
|
|
|
P 4850 2900
|
|
|
|
|
F 0 "R26" V 4750 2900 50 0000 C CNN
|
|
|
|
|
F 1 "10R" V 4850 2900 50 0000 C CNN
|
|
|
|
|
F 2 "ipc_resc:IPC_RESC100X50X40L25N" V 4780 2900 50 0001 C CNN
|
|
|
|
|
F 3 "~" H 4850 2900 50 0001 C CNN
|
|
|
|
|
F 4 "DNP" V 4950 2900 50 0000 C CNN "DNP"
|
|
|
|
|
1 4850 2900
|
|
|
|
|
0 1 1 0
|
|
|
|
|
$EndComp
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
5200 2900 5000 2900
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
4700 2900 4600 2900
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
4600 2900 4600 3300
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
4600 3600 4600 3700
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
4600 2900 4500 2900
|
|
|
|
|
Connection ~ 4600 2900
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
4200 2900 4100 2900
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
4100 2900 4100 2600
|
|
|
|
|
Connection ~ 4100 2600
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
2700 2600 4100 2600
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
7800 1800 7700 1800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
7400 1800 7300 1800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6650 1800 6800 1800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6800 2600 6800 1800
|
|
|
|
|
Connection ~ 6800 2600
|
|
|
|
|
Connection ~ 6800 1800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6800 1800 6900 1800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6400 2800 7300 2800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
7300 1800 7300 2800
|
|
|
|
|
Connection ~ 7300 1800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
7300 1800 7200 1800
|
|
|
|
|
Wire Wire Line
|
|
|
|
|
6800 2700 6800 3300
|
|
|
|
|
Connection ~ 6800 2700
|
|
|
|
|
$EndSCHEMATC
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