mirror of
https://github.com/liberatedsystems/RNode_Firmware_CE.git
synced 2024-12-18 04:14:21 -05:00
987 lines
22 KiB
C++
987 lines
22 KiB
C++
// Copyright (c) Sandeep Mistry. All rights reserved.
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// Licensed under the MIT license.
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// Modifications and additions copyright 2023 by Mark Qvist
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// Obviously still under the MIT license.
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#include "Boards.h"
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#if MODEM == SX1262
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#include "sx126x.h"
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#if MCU_VARIANT == MCU_ESP32
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#if MCU_VARIANT == MCU_ESP32 and !defined(CONFIG_IDF_TARGET_ESP32S3)
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#include "soc/rtc_wdt.h"
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#endif
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#define ISR_VECT IRAM_ATTR
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#else
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#define ISR_VECT
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#endif
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#define OP_RF_FREQ_6X 0x86
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#define OP_SLEEP_6X 0x84
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#define OP_STANDBY_6X 0x80
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#define OP_TX_6X 0x83
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#define OP_RX_6X 0x82
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#define OP_PA_CONFIG_6X 0x95
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#define OP_SET_IRQ_FLAGS_6X 0x08 // also provides info such as
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// preamble detection, etc for
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// knowing when it's safe to switch
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// antenna modes
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#define OP_CLEAR_IRQ_STATUS_6X 0x02
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#define OP_GET_IRQ_STATUS_6X 0x12
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#define OP_RX_BUFFER_STATUS_6X 0x13
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#define OP_PACKET_STATUS_6X 0x14 // get snr & rssi of last packet
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#define OP_CURRENT_RSSI_6X 0x15
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#define OP_MODULATION_PARAMS_6X 0x8B // bw, sf, cr, etc.
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#define OP_PACKET_PARAMS_6X 0x8C // crc, preamble, payload length, etc.
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#define OP_STATUS_6X 0xC0
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#define OP_TX_PARAMS_6X 0x8E // set dbm, etc
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#define OP_PACKET_TYPE_6X 0x8A
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#define OP_BUFFER_BASE_ADDR_6X 0x8F
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#define OP_READ_REGISTER_6X 0x1D
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#define OP_WRITE_REGISTER_6X 0x0D
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#define OP_DIO3_TCXO_CTRL_6X 0x97
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#define OP_DIO2_RF_CTRL_6X 0x9D
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#define OP_CAD_PARAMS 0x88
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#define OP_CALIBRATE_6X 0x89
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#define OP_RX_TX_FALLBACK_MODE_6X 0x93
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#define OP_REGULATOR_MODE_6X 0x96
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#define OP_CALIBRATE_IMAGE_6X 0x98
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#define MASK_CALIBRATE_ALL 0x7f
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#define IRQ_TX_DONE_MASK_6X 0x01
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#define IRQ_RX_DONE_MASK_6X 0x02
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#define IRQ_HEADER_DET_MASK_6X 0x10
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#define IRQ_PREAMBLE_DET_MASK_6X 0x04
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#define IRQ_PAYLOAD_CRC_ERROR_MASK_6X 0x40
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#define IRQ_ALL_MASK_6X 0b0100001111111111
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#define MODE_LONG_RANGE_MODE_6X 0x01
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#define OP_FIFO_WRITE_6X 0x0E
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#define OP_FIFO_READ_6X 0x1E
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#define REG_OCP_6X 0x08E7
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#define REG_LNA_6X 0x08AC // no agc in sx1262
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#define REG_SYNC_WORD_MSB_6X 0x0740
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#define REG_SYNC_WORD_LSB_6X 0x0741
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#define REG_PAYLOAD_LENGTH_6X 0x0702 // https://github.com/beegee-tokyo/SX126x-Arduino/blob/master/src/radio/sx126x/sx126x.h#L98
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#define REG_RANDOM_GEN_6X 0x0819
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#define MODE_TCXO_3_3V_6X 0x07
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#define MODE_TCXO_3_0V_6X 0x06
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#define MODE_TCXO_2_7V_6X 0x06
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#define MODE_TCXO_2_4V_6X 0x06
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#define MODE_TCXO_2_2V_6X 0x03
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#define MODE_TCXO_1_8V_6X 0x02
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#define MODE_TCXO_1_7V_6X 0x01
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#define MODE_TCXO_1_6V_6X 0x00
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#define MODE_STDBY_RC_6X 0x00
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#define MODE_STDBY_XOSC_6X 0x01
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#define MODE_FALLBACK_STDBY_RC_6X 0x20
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#define MODE_IMPLICIT_HEADER 0x01
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#define MODE_EXPLICIT_HEADER 0x00
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#define SYNC_WORD_6X 0x1424
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#define XTAL_FREQ_6X (double)32000000
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#define FREQ_DIV_6X (double)pow(2.0, 25.0)
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#define FREQ_STEP_6X (double)(XTAL_FREQ_6X / FREQ_DIV_6X)
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#if defined(NRF52840_XXAA)
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extern SPIClass spiModem;
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#define SPI spiModem
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#endif
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extern SPIClass SPI;
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#define MAX_PKT_LENGTH 255
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sx126x::sx126x() :
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_spiSettings(8E6, MSBFIRST, SPI_MODE0),
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_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN), _busy(LORA_DEFAULT_BUSY_PIN), _rxen(LORA_DEFAULT_RXEN_PIN),
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_frequency(0),
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_txp(0),
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_sf(0x07),
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_bw(0x04),
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_cr(0x01),
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_ldro(0x00),
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_packetIndex(0),
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_preambleLength(18),
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_implicitHeaderMode(0),
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_payloadLength(255),
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_crcMode(1),
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_fifo_tx_addr_ptr(0),
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_fifo_rx_addr_ptr(0),
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_packet({0}),
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_preinit_done(false),
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_onReceive(NULL)
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{
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// overide Stream timeout value
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setTimeout(0);
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}
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bool sx126x::preInit() {
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pinMode(_ss, OUTPUT);
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digitalWrite(_ss, HIGH);
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#if BOARD_MODEL == BOARD_RNODE_NG_22 || BOARD_MODEL == BOARD_HELTEC32_V3
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SPI.begin(pin_sclk, pin_miso, pin_mosi, pin_cs);
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#else
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SPI.begin();
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#endif
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// check version (retry for up to 2 seconds)
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// TODO: Actually read version registers, not syncwords
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long start = millis();
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uint8_t syncmsb;
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uint8_t synclsb;
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while (((millis() - start) < 2000) && (millis() >= start)) {
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syncmsb = readRegister(REG_SYNC_WORD_MSB_6X);
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synclsb = readRegister(REG_SYNC_WORD_LSB_6X);
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if ( uint16_t(syncmsb << 8 | synclsb) == 0x1424 || uint16_t(syncmsb << 8 | synclsb) == 0x4434) {
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break;
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}
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delay(100);
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}
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if ( uint16_t(syncmsb << 8 | synclsb) != 0x1424 && uint16_t(syncmsb << 8 | synclsb) != 0x4434) {
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return false;
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}
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_preinit_done = true;
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return true;
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}
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uint8_t ISR_VECT sx126x::readRegister(uint16_t address)
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{
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return singleTransfer(OP_READ_REGISTER_6X, address, 0x00);
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}
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void sx126x::writeRegister(uint16_t address, uint8_t value)
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{
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singleTransfer(OP_WRITE_REGISTER_6X, address, value);
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}
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uint8_t ISR_VECT sx126x::singleTransfer(uint8_t opcode, uint16_t address, uint8_t value)
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{
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waitOnBusy();
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uint8_t response;
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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SPI.transfer((address & 0xFF00) >> 8);
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SPI.transfer(address & 0x00FF);
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if (opcode == OP_READ_REGISTER_6X) {
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SPI.transfer(0x00);
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}
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response = SPI.transfer(value);
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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return response;
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}
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void sx126x::rxAntEnable()
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{
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if (_rxen != -1) {
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digitalWrite(_rxen, HIGH);
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}
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}
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void sx126x::loraMode() {
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// enable lora mode on the SX1262 chip
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uint8_t mode = MODE_LONG_RANGE_MODE_6X;
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executeOpcode(OP_PACKET_TYPE_6X, &mode, 1);
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}
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void sx126x::waitOnBusy() {
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unsigned long time = millis();
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if (_busy != -1) {
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while (digitalRead(_busy) == HIGH)
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{
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if (millis() >= (time + 100)) {
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break;
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}
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// do nothing
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}
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}
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}
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void sx126x::executeOpcode(uint8_t opcode, uint8_t *buffer, uint8_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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for (int i = 0; i < size; i++)
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{
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SPI.transfer(buffer[i]);
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::executeOpcodeRead(uint8_t opcode, uint8_t *buffer, uint8_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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SPI.transfer(0x00);
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for (int i = 0; i < size; i++)
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{
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buffer[i] = SPI.transfer(0x00);
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::writeBuffer(const uint8_t* buffer, size_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(OP_FIFO_WRITE_6X);
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SPI.transfer(_fifo_tx_addr_ptr);
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for (int i = 0; i < size; i++)
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{
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SPI.transfer(buffer[i]);
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_fifo_tx_addr_ptr++;
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::readBuffer(uint8_t* buffer, size_t size)
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{
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(OP_FIFO_READ_6X);
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SPI.transfer(_fifo_rx_addr_ptr);
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SPI.transfer(0x00);
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for (int i = 0; i < size; i++)
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{
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buffer[i] = SPI.transfer(0x00);
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}
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr, int ldro) {
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// because there is no access to these registers on the sx1262, we have
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// to set all these parameters at once or not at all.
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uint8_t buf[8];
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buf[0] = sf;
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buf[1] = bw;
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buf[2] = cr;
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// low data rate toggle
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buf[3] = ldro;
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// unused params in LoRa mode
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buf[4] = 0x00;
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buf[5] = 0x00;
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buf[6] = 0x00;
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buf[7] = 0x00;
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executeOpcode(OP_MODULATION_PARAMS_6X, buf, 8);
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}
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void sx126x::setPacketParams(long preamble, uint8_t headermode, uint8_t length, uint8_t crc) {
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// because there is no access to these registers on the sx1262, we have
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// to set all these parameters at once or not at all.
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uint8_t buf[9];
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buf[0] = uint8_t((preamble & 0xFF00) >> 8);
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buf[1] = uint8_t((preamble & 0x00FF));
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buf[2] = headermode;
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buf[3] = length;
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buf[4] = crc;
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// standard IQ setting (no inversion)
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buf[5] = 0x00;
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// unused params
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buf[6] = 0x00;
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buf[7] = 0x00;
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buf[8] = 0x00;
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executeOpcode(OP_PACKET_PARAMS_6X, buf, 9);
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}
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void sx126x::reset(void) {
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if (_reset != -1) {
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pinMode(_reset, OUTPUT);
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// perform reset
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digitalWrite(_reset, LOW);
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delay(10);
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digitalWrite(_reset, HIGH);
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delay(10);
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}
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}
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void sx126x::calibrate(void) {
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// Put in STDBY_RC mode before calibration
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uint8_t mode_byte = MODE_STDBY_RC_6X;
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executeOpcode(OP_STANDBY_6X, &mode_byte, 1);
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// calibrate RC64k, RC13M, PLL, ADC and image
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uint8_t calibrate = MASK_CALIBRATE_ALL;
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executeOpcode(OP_CALIBRATE_6X, &calibrate, 1);
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delay(5);
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waitOnBusy();
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}
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void sx126x::calibrate_image(long frequency) {
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uint8_t image_freq[2] = {0};
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if (frequency >= 430E6 && frequency <= 440E6) {
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image_freq[0] = 0x6B;
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image_freq[1] = 0x6F;
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}
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else if (frequency >= 470E6 && frequency <= 510E6) {
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image_freq[0] = 0x75;
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image_freq[1] = 0x81;
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}
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else if (frequency >= 779E6 && frequency <= 787E6) {
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image_freq[0] = 0xC1;
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image_freq[1] = 0xC5;
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}
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else if (frequency >= 863E6 && frequency <= 870E6) {
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image_freq[0] = 0xD7;
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image_freq[1] = 0xDB;
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}
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else if (frequency >= 902E6 && frequency <= 928E6) {
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image_freq[0] = 0xE1;
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image_freq[1] = 0xE9;
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}
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executeOpcode(OP_CALIBRATE_IMAGE_6X, image_freq, 2);
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waitOnBusy();
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}
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int sx126x::begin(long frequency)
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{
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reset();
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if (_busy != -1) {
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pinMode(_busy, INPUT);
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}
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if (!_preinit_done) {
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if (!preInit()) {
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return false;
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}
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}
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if (_rxen != -1) {
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pinMode(_rxen, OUTPUT);
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}
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calibrate();
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calibrate_image(frequency);
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enableTCXO();
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loraMode();
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standby();
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// Set sync word
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setSyncWord(SYNC_WORD_6X);
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#if DIO2_AS_RF_SWITCH
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// enable dio2 rf switch
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uint8_t byte = 0x01;
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executeOpcode(OP_DIO2_RF_CTRL_6X, &byte, 1);
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#endif
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rxAntEnable();
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setFrequency(frequency);
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// set output power to 2 dBm
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setTxPower(2);
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enableCrc();
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// set LNA boost
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writeRegister(REG_LNA_6X, 0x96);
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// set base addresses
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uint8_t basebuf[2] = {0};
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executeOpcode(OP_BUFFER_BASE_ADDR_6X, basebuf, 2);
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setModulationParams(_sf, _bw, _cr, _ldro);
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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return 1;
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}
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void sx126x::end()
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{
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// put in sleep mode
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sleep();
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// stop SPI
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SPI.end();
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_preinit_done = false;
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}
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int sx126x::beginPacket(int implicitHeader)
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{
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standby();
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if (implicitHeader) {
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implicitHeaderMode();
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} else {
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explicitHeaderMode();
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}
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_payloadLength = 0;
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_fifo_tx_addr_ptr = 0;
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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return 1;
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}
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int sx126x::endPacket()
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{
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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// put in single TX mode
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uint8_t timeout[3] = {0};
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executeOpcode(OP_TX_6X, timeout, 3);
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uint8_t buf[2];
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buf[0] = 0x00;
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buf[1] = 0x00;
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executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
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// wait for TX done
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while ((buf[1] & IRQ_TX_DONE_MASK_6X) == 0) {
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buf[0] = 0x00;
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buf[1] = 0x00;
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executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
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yield();
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}
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// clear IRQ's
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uint8_t mask[2];
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mask[0] = 0x00;
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mask[1] = IRQ_TX_DONE_MASK_6X;
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executeOpcode(OP_CLEAR_IRQ_STATUS_6X, mask, 2);
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return 1;
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}
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uint8_t sx126x::modemStatus() {
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// imitate the register status from the sx1276 / 78
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uint8_t buf[2] = {0};
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executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
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uint8_t clearbuf[2] = {0};
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uint8_t byte = 0x00;
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if ((buf[1] & IRQ_PREAMBLE_DET_MASK_6X) != 0) {
|
|
byte = byte | 0x01 | 0x04;
|
|
// clear register after reading
|
|
clearbuf[1] = IRQ_PREAMBLE_DET_MASK_6X;
|
|
}
|
|
|
|
if ((buf[1] & IRQ_HEADER_DET_MASK_6X) != 0) {
|
|
byte = byte | 0x02 | 0x04;
|
|
}
|
|
|
|
executeOpcode(OP_CLEAR_IRQ_STATUS_6X, clearbuf, 2);
|
|
|
|
return byte;
|
|
}
|
|
|
|
|
|
uint8_t sx126x::currentRssiRaw() {
|
|
uint8_t byte = 0;
|
|
executeOpcodeRead(OP_CURRENT_RSSI_6X, &byte, 1);
|
|
return byte;
|
|
}
|
|
|
|
int ISR_VECT sx126x::currentRssi() {
|
|
uint8_t byte = 0;
|
|
executeOpcodeRead(OP_CURRENT_RSSI_6X, &byte, 1);
|
|
int rssi = -(int(byte)) / 2;
|
|
return rssi;
|
|
}
|
|
|
|
uint8_t sx126x::packetRssiRaw() {
|
|
uint8_t buf[3] = {0};
|
|
executeOpcodeRead(OP_PACKET_STATUS_6X, buf, 3);
|
|
return buf[2];
|
|
}
|
|
|
|
int ISR_VECT sx126x::packetRssi() {
|
|
// may need more calculations here
|
|
uint8_t buf[3] = {0};
|
|
executeOpcodeRead(OP_PACKET_STATUS_6X, buf, 3);
|
|
int pkt_rssi = -buf[0] / 2;
|
|
return pkt_rssi;
|
|
}
|
|
|
|
uint8_t ISR_VECT sx126x::packetSnrRaw() {
|
|
uint8_t buf[3] = {0};
|
|
executeOpcodeRead(OP_PACKET_STATUS_6X, buf, 3);
|
|
return buf[1];
|
|
}
|
|
|
|
float ISR_VECT sx126x::packetSnr() {
|
|
uint8_t buf[3] = {0};
|
|
executeOpcodeRead(OP_PACKET_STATUS_6X, buf, 3);
|
|
return float(buf[1]) * 0.25;
|
|
}
|
|
|
|
long sx126x::packetFrequencyError()
|
|
{
|
|
// todo: implement this, no idea how to check it on the sx1262
|
|
const float fError = 0.0;
|
|
return static_cast<long>(fError);
|
|
}
|
|
|
|
size_t sx126x::write(uint8_t byte)
|
|
{
|
|
return write(&byte, sizeof(byte));
|
|
}
|
|
|
|
size_t sx126x::write(const uint8_t *buffer, size_t size)
|
|
{
|
|
if ((_payloadLength + size) > MAX_PKT_LENGTH) {
|
|
size = MAX_PKT_LENGTH - _payloadLength;
|
|
}
|
|
|
|
// write data
|
|
writeBuffer(buffer, size);
|
|
_payloadLength = _payloadLength + size;
|
|
return size;
|
|
}
|
|
|
|
int ISR_VECT sx126x::available()
|
|
{
|
|
uint8_t buf[2] = {0};
|
|
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, buf, 2);
|
|
return buf[0] - _packetIndex;
|
|
}
|
|
|
|
int ISR_VECT sx126x::read()
|
|
{
|
|
if (!available()) {
|
|
return -1;
|
|
}
|
|
|
|
// if received new packet
|
|
if (_packetIndex == 0) {
|
|
uint8_t rxbuf[2] = {0};
|
|
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
|
|
int size = rxbuf[0];
|
|
_fifo_rx_addr_ptr = rxbuf[1];
|
|
|
|
readBuffer(_packet, size);
|
|
}
|
|
|
|
uint8_t byte = _packet[_packetIndex];
|
|
_packetIndex++;
|
|
return byte;
|
|
}
|
|
|
|
int sx126x::peek()
|
|
{
|
|
if (!available()) {
|
|
return -1;
|
|
}
|
|
|
|
// if received new packet
|
|
if (_packetIndex == 0) {
|
|
uint8_t rxbuf[2] = {0};
|
|
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
|
|
int size = rxbuf[0];
|
|
_fifo_rx_addr_ptr = rxbuf[1];
|
|
|
|
readBuffer(_packet, size);
|
|
}
|
|
|
|
uint8_t b = _packet[_packetIndex];
|
|
return b;
|
|
}
|
|
|
|
void sx126x::flush()
|
|
{
|
|
}
|
|
|
|
void sx126x::onReceive(void(*callback)(int))
|
|
{
|
|
_onReceive = callback;
|
|
|
|
if (callback) {
|
|
pinMode(_dio0, INPUT);
|
|
|
|
// set preamble and header detection irqs, plus dio0 mask
|
|
uint8_t buf[8];
|
|
|
|
// set irq masks, enable all
|
|
buf[0] = 0xFF;
|
|
buf[1] = 0xFF;
|
|
|
|
// set dio0 masks
|
|
buf[2] = 0x00;
|
|
buf[3] = IRQ_RX_DONE_MASK_6X;
|
|
|
|
// set dio1 masks
|
|
buf[4] = 0x00;
|
|
buf[5] = 0x00;
|
|
|
|
// set dio2 masks
|
|
buf[6] = 0x00;
|
|
buf[7] = 0x00;
|
|
|
|
executeOpcode(OP_SET_IRQ_FLAGS_6X, buf, 8);
|
|
#ifdef SPI_HAS_NOTUSINGINTERRUPT
|
|
SPI.usingInterrupt(digitalPinToInterrupt(_dio0));
|
|
#endif
|
|
attachInterrupt(digitalPinToInterrupt(_dio0), sx126x::onDio0Rise, RISING);
|
|
} else {
|
|
detachInterrupt(digitalPinToInterrupt(_dio0));
|
|
#ifdef SPI_HAS_NOTUSINGINTERRUPT
|
|
SPI.notUsingInterrupt(digitalPinToInterrupt(_dio0));
|
|
#endif
|
|
}
|
|
}
|
|
|
|
void sx126x::receive(int size)
|
|
{
|
|
if (size > 0) {
|
|
implicitHeaderMode();
|
|
|
|
// tell radio payload length
|
|
_payloadLength = size;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
} else {
|
|
explicitHeaderMode();
|
|
}
|
|
|
|
if (_rxen != -1) {
|
|
rxAntEnable();
|
|
}
|
|
|
|
uint8_t mode[3] = {0xFF, 0xFF, 0xFF}; // continuous mode
|
|
executeOpcode(OP_RX_6X, mode, 3);
|
|
}
|
|
|
|
void sx126x::standby()
|
|
{
|
|
// STDBY_XOSC
|
|
uint8_t byte = MODE_STDBY_XOSC_6X;
|
|
// STDBY_RC
|
|
// uint8_t byte = MODE_STDBY_RC_6X;
|
|
executeOpcode(OP_STANDBY_6X, &byte, 1);
|
|
}
|
|
|
|
void sx126x::sleep()
|
|
{
|
|
uint8_t byte = 0x00;
|
|
executeOpcode(OP_SLEEP_6X, &byte, 1);
|
|
}
|
|
|
|
void sx126x::enableTCXO() {
|
|
#if HAS_TCXO
|
|
#if BOARD_MODEL == BOARD_RAK4630 || BOARD_MODEL == BOARD_HELTEC32_V3
|
|
uint8_t buf[4] = {MODE_TCXO_3_3V_6X, 0x00, 0x00, 0xFF};
|
|
#elif BOARD_MODEL == BOARD_TBEAM
|
|
uint8_t buf[4] = {MODE_TCXO_1_8V_6X, 0x00, 0x00, 0xFF};
|
|
#elif BOARD_MODEL == BOARD_RNODE_NG_22
|
|
uint8_t buf[4] = {MODE_TCXO_1_8V_6X, 0x00, 0x00, 0xFF};
|
|
#endif
|
|
executeOpcode(OP_DIO3_TCXO_CTRL_6X, buf, 4);
|
|
#endif
|
|
}
|
|
|
|
// TODO: Once enabled, SX1262 needs a complete reset to disable TCXO
|
|
void sx126x::disableTCXO() { }
|
|
|
|
void sx126x::setTxPower(int level, int outputPin) {
|
|
// currently no low power mode for SX1262 implemented, assuming PA boost
|
|
|
|
// WORKAROUND - Better Resistance of the SX1262 Tx to Antenna Mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2
|
|
// RegTxClampConfig = @address 0x08D8
|
|
writeRegister(0x08D8, readRegister(0x08D8) | (0x0F << 1));
|
|
|
|
uint8_t pa_buf[4];
|
|
|
|
pa_buf[0] = 0x04; // PADutyCycle needs to be 0x04 to achieve 22dBm output, but can be lowered for better efficiency at lower outputs
|
|
pa_buf[1] = 0x07; // HPMax at 0x07 is maximum supported for SX1262
|
|
pa_buf[2] = 0x00; // DeviceSel 0x00 for SX1262 (0x01 for SX1261)
|
|
pa_buf[3] = 0x01; // PALut always 0x01 (reserved according to datasheet)
|
|
|
|
executeOpcode(OP_PA_CONFIG_6X, pa_buf, 4); // set pa_config for high power
|
|
|
|
if (level > 22) { level = 22; }
|
|
else if (level < -9) { level = -9; }
|
|
|
|
writeRegister(REG_OCP_6X, 0x38); // 160mA limit, overcurrent protection
|
|
|
|
uint8_t tx_buf[2];
|
|
|
|
tx_buf[0] = level;
|
|
tx_buf[1] = 0x02; // PA ramping time - 40 microseconds
|
|
|
|
executeOpcode(OP_TX_PARAMS_6X, tx_buf, 2);
|
|
|
|
_txp = level;
|
|
}
|
|
|
|
uint8_t sx126x::getTxPower() {
|
|
return _txp;
|
|
}
|
|
|
|
void sx126x::setFrequency(long frequency) {
|
|
_frequency = frequency;
|
|
|
|
uint8_t buf[4];
|
|
|
|
uint32_t freq = (uint32_t)((double)frequency / (double)FREQ_STEP_6X);
|
|
|
|
buf[0] = ((freq >> 24) & 0xFF);
|
|
buf[1] = ((freq >> 16) & 0xFF);
|
|
buf[2] = ((freq >> 8) & 0xFF);
|
|
buf[3] = (freq & 0xFF);
|
|
|
|
executeOpcode(OP_RF_FREQ_6X, buf, 4);
|
|
}
|
|
|
|
uint32_t sx126x::getFrequency() {
|
|
// we can't read the frequency on the sx1262 / 80
|
|
uint32_t frequency = _frequency;
|
|
|
|
return frequency;
|
|
}
|
|
|
|
void sx126x::setSpreadingFactor(int sf)
|
|
{
|
|
if (sf < 5) {
|
|
sf = 5;
|
|
} else if (sf > 12) {
|
|
sf = 12;
|
|
}
|
|
|
|
_sf = sf;
|
|
|
|
handleLowDataRate();
|
|
setModulationParams(sf, _bw, _cr, _ldro);
|
|
}
|
|
|
|
long sx126x::getSignalBandwidth()
|
|
{
|
|
int bw = _bw;
|
|
switch (bw) {
|
|
case 0x00: return 7.8E3;
|
|
case 0x01: return 15.6E3;
|
|
case 0x02: return 31.25E3;
|
|
case 0x03: return 62.5E3;
|
|
case 0x04: return 125E3;
|
|
case 0x05: return 250E3;
|
|
case 0x06: return 500E3;
|
|
case 0x08: return 10.4E3;
|
|
case 0x09: return 20.8E3;
|
|
case 0x0A: return 41.7E3;
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
void sx126x::handleLowDataRate(){
|
|
if ( long( (1<<_sf) / (getSignalBandwidth()/1000)) > 16) {
|
|
_ldro = 0x01;
|
|
} else {
|
|
_ldro = 0x00;
|
|
}
|
|
}
|
|
|
|
void sx126x::optimizeModemSensitivity(){
|
|
// todo: check if there's anything the sx1262 can do here
|
|
}
|
|
|
|
void sx126x::setSignalBandwidth(long sbw)
|
|
{
|
|
if (sbw <= 7.8E3) {
|
|
_bw = 0x00;
|
|
} else if (sbw <= 10.4E3) {
|
|
_bw = 0x08;
|
|
} else if (sbw <= 15.6E3) {
|
|
_bw = 0x01;
|
|
} else if (sbw <= 20.8E3) {
|
|
_bw = 0x09;
|
|
} else if (sbw <= 31.25E3) {
|
|
_bw = 0x02;
|
|
} else if (sbw <= 41.7E3) {
|
|
_bw = 0x0A;
|
|
} else if (sbw <= 62.5E3) {
|
|
_bw = 0x03;
|
|
} else if (sbw <= 125E3) {
|
|
_bw = 0x04;
|
|
} else if (sbw <= 250E3) {
|
|
_bw = 0x05;
|
|
} else /*if (sbw <= 250E3)*/ {
|
|
_bw = 0x06;
|
|
}
|
|
|
|
handleLowDataRate();
|
|
setModulationParams(_sf, _bw, _cr, _ldro);
|
|
|
|
optimizeModemSensitivity();
|
|
}
|
|
|
|
void sx126x::setCodingRate4(int denominator)
|
|
{
|
|
if (denominator < 5) {
|
|
denominator = 5;
|
|
} else if (denominator > 8) {
|
|
denominator = 8;
|
|
}
|
|
|
|
int cr = denominator - 4;
|
|
|
|
_cr = cr;
|
|
|
|
setModulationParams(_sf, _bw, cr, _ldro);
|
|
}
|
|
|
|
void sx126x::setPreambleLength(long length)
|
|
{
|
|
_preambleLength = length;
|
|
setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
void sx126x::setSyncWord(uint16_t sw)
|
|
{
|
|
// TODO: Fix
|
|
// writeRegister(REG_SYNC_WORD_MSB_6X, (sw & 0xFF00) >> 8);
|
|
// writeRegister(REG_SYNC_WORD_LSB_6X, sw & 0x00FF);
|
|
writeRegister(REG_SYNC_WORD_MSB_6X, 0x14);
|
|
writeRegister(REG_SYNC_WORD_LSB_6X, 0x24);
|
|
}
|
|
|
|
void sx126x::enableCrc()
|
|
{
|
|
_crcMode = 1;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
void sx126x::disableCrc()
|
|
{
|
|
_crcMode = 0;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
byte sx126x::random()
|
|
{
|
|
return readRegister(REG_RANDOM_GEN_6X);
|
|
}
|
|
|
|
void sx126x::setPins(int ss, int reset, int dio0, int busy, int rxen)
|
|
{
|
|
_ss = ss;
|
|
_reset = reset;
|
|
_dio0 = dio0;
|
|
_busy = busy;
|
|
_rxen = rxen;
|
|
}
|
|
|
|
void sx126x::setSPIFrequency(uint32_t frequency)
|
|
{
|
|
_spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0);
|
|
}
|
|
|
|
void sx126x::dumpRegisters(Stream& out)
|
|
{
|
|
for (int i = 0; i < 128; i++) {
|
|
out.print("0x");
|
|
out.print(i, HEX);
|
|
out.print(": 0x");
|
|
out.println(readRegister(i), HEX);
|
|
}
|
|
}
|
|
|
|
void sx126x::explicitHeaderMode()
|
|
{
|
|
_implicitHeaderMode = 0;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
void sx126x::implicitHeaderMode()
|
|
{
|
|
_implicitHeaderMode = 1;
|
|
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
|
}
|
|
|
|
|
|
void ISR_VECT sx126x::handleDio0Rise()
|
|
{
|
|
uint8_t buf[2];
|
|
|
|
buf[0] = 0x00;
|
|
buf[1] = 0x00;
|
|
|
|
executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
|
|
|
|
executeOpcode(OP_CLEAR_IRQ_STATUS_6X, buf, 2);
|
|
|
|
if ((buf[1] & IRQ_PAYLOAD_CRC_ERROR_MASK_6X) == 0) {
|
|
// received a packet
|
|
_packetIndex = 0;
|
|
|
|
// read packet length
|
|
uint8_t rxbuf[2] = {0};
|
|
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
|
|
int packetLength = rxbuf[0];
|
|
|
|
if (_onReceive) {
|
|
_onReceive(packetLength);
|
|
}
|
|
}
|
|
// else {
|
|
// Serial.println("CRCE");
|
|
// Serial.println(buf[0]);
|
|
// Serial.println(buf[1]);
|
|
// }
|
|
}
|
|
|
|
void ISR_VECT sx126x::onDio0Rise()
|
|
{
|
|
sx126x_modem.handleDio0Rise();
|
|
}
|
|
|
|
sx126x sx126x_modem;
|
|
|
|
#endif |