mirror of
https://github.com/liberatedsystems/RNode_Firmware_CE.git
synced 2025-06-18 03:29:25 -04:00
Change interrupt layout and address SX1280 errata
This commit is contained in:
jacob.eva
parent
7f787d5910
commit
c3c254cd96
3 changed files with 112 additions and 96 deletions
179
Radio.cpp
179
Radio.cpp
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@ -98,7 +98,17 @@ extern RadioInterface* interface_obj[];
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void ISR_VECT onDio0Rise() {
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for (int i = 0; i < INTERFACE_COUNT; i++) {
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if (digitalRead(interface_pins[i][5]) == HIGH) {
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fifo_push(&packet_rdy_interfaces, i);
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if (interface_obj[i]->getPacketValidity()) {
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fifo_push(&packet_rdy_interfaces, i);
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}
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if (interfaces[i] == SX128X) {
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// On the SX1280, there is a bug which can cause the busy line
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// to remain high if a high amount of packets are received when
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// in continuous RX mode. This is documented as Errata 16.1 in
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// the SX1280 datasheet v3.2 (page 149)
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// Therefore, the modem is set into receive mode each time a packet is received.
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interface_obj[i]->receive();
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}
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}
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}
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}
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@ -962,33 +972,17 @@ void sx126x::implicitHeaderMode()
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void sx126x::handleDio0Rise()
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{
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uint8_t buf[2];
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// received a packet
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_packetIndex = 0;
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buf[0] = 0x00;
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buf[1] = 0x00;
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// read packet length
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uint8_t rxbuf[2] = {0};
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executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
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int packetLength = rxbuf[0];
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executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
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executeOpcode(OP_CLEAR_IRQ_STATUS_6X, buf, 2);
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if ((buf[1] & IRQ_PAYLOAD_CRC_ERROR_MASK_6X) == 0) {
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// received a packet
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_packetIndex = 0;
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// read packet length
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uint8_t rxbuf[2] = {0};
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executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
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int packetLength = rxbuf[0];
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if (_onReceive) {
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_onReceive(_index, packetLength);
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}
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if (_onReceive) {
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_onReceive(_index, packetLength);
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}
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// else {
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// Serial.println("CRCE");
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// Serial.println(buf[0]);
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// Serial.println(buf[1]);
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// }
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}
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void sx126x::updateBitrate() {
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@ -1011,7 +1005,7 @@ void sx126x::updateBitrate() {
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}
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}
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void sx126x::clearIRQStatus() {
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bool ISR_VECT sx126x::getPacketValidity() {
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uint8_t buf[2];
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buf[0] = 0x00;
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@ -1020,6 +1014,12 @@ void sx126x::clearIRQStatus() {
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executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
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executeOpcode(OP_CLEAR_IRQ_STATUS_6X, buf, 2);
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if ((buf[1] & IRQ_PAYLOAD_CRC_ERROR_MASK_6X) == 0) {
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return true;
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} else {
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return false;
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}
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}
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// SX127x registers
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#define REG_FIFO_7X 0x00
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@ -1512,11 +1512,6 @@ void sx127x::optimizeModemSensitivity() {
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}
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void sx127x::handleDio0Rise() {
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int irqFlags = readRegister(REG_IRQ_FLAGS_7X);
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// Clear IRQs
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writeRegister(REG_IRQ_FLAGS_7X, irqFlags);
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if ((irqFlags & IRQ_PAYLOAD_CRC_ERROR_MASK_7X) == 0) {
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_packetIndex = 0;
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int packetLength = _implicitHeaderMode ? readRegister(REG_PAYLOAD_LENGTH_7X) : readRegister(REG_RX_NB_BYTES_7X);
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writeRegister(REG_FIFO_ADDR_PTR_7X, readRegister(REG_FIFO_RX_CURRENT_ADDR_7X));
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@ -1524,7 +1519,6 @@ void sx127x::handleDio0Rise() {
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_onReceive(_index, packetLength);
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}
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writeRegister(REG_FIFO_ADDR_PTR_7X, 0);
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}
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}
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void sx127x::updateBitrate() {
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@ -1546,11 +1540,17 @@ void sx127x::updateBitrate() {
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}
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}
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void sx127x::clearIRQStatus() {
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bool ISR_VECT sx127x::getPacketValidity() {
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int irqFlags = readRegister(REG_IRQ_FLAGS_7X);
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// Clear IRQs
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writeRegister(REG_IRQ_FLAGS_7X, irqFlags);
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if ((irqFlags & IRQ_PAYLOAD_CRC_ERROR_MASK_7X) == 0) {
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return true;
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} else {
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return false;
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}
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}
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// SX128x registers
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@ -2040,7 +2040,7 @@ uint8_t ISR_VECT sx128x::packetSnrRaw() {
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float ISR_VECT sx128x::packetSnr() {
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uint8_t buf[5] = {0};
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executeOpcodeRead(OP_PACKET_STATUS_8X, buf, 3);
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executeOpcodeRead(OP_PACKET_STATUS_8X, buf, 5);
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return float(buf[1]) * 0.25;
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}
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@ -2076,13 +2076,34 @@ int ISR_VECT sx128x::available()
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int ISR_VECT sx128x::read()
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{
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if (!available()) {
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return -1;
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}
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if (!available()) {
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return -1;
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}
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uint8_t byte = _packet[_packetIndex];
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_packetIndex++;
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return byte;
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// if received new packet
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if (_packetIndex == 0) {
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uint8_t rxbuf[2] = {0};
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executeOpcodeRead(OP_RX_BUFFER_STATUS_8X, rxbuf, 2);
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int size;
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// If implicit header mode is enabled, read packet length as payload length instead.
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// See SX1280 datasheet v3.2, page 92
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if (_implicitHeaderMode == 0x80) {
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size = _payloadLength;
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} else {
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size = rxbuf[0];
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}
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_fifo_rx_addr_ptr = rxbuf[1];
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if (size > 255) {
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size = 255;
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}
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readBuffer(_packet, size);
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}
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uint8_t byte = _packet[_packetIndex];
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_packetIndex++;
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return byte;
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}
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int sx128x::peek()
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@ -2113,9 +2134,16 @@ void sx128x::onReceive(void(*callback)(uint8_t, int))
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buf[0] = 0xFF;
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buf[1] = 0xFF;
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// On the SX1280, no RxDone IRQ is generated if a packet is received with
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// an invalid header, but the modem will be taken out of single RX mode.
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// This can cause the modem to not receive packets until it is reset
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// again. This is documented as Errata 16.2 in the SX1280 datasheet v3.2
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// (page 150) Below, the header error IRQ is mapped to dio0 so that the
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// modem can be set into RX mode again on reception of a corrupted
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// header.
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// set dio0 masks
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buf[2] = 0x00;
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buf[3] = IRQ_RX_DONE_MASK_8X;
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buf[3] = IRQ_RX_DONE_MASK_8X | IRQ_HEADER_ERROR_MASK_8X;
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// set dio1 masks
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buf[4] = 0x00;
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@ -2126,9 +2154,9 @@ void sx128x::onReceive(void(*callback)(uint8_t, int))
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buf[7] = 0x00;
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executeOpcode(OP_SET_IRQ_FLAGS_8X, buf, 8);
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//#ifdef SPI_HAS_NOTUSINGINTERRUPT
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// _spiModem->usingInterrupt(digitalPinToInterrupt(_dio0));
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//#endif
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#ifdef SPI_HAS_NOTUSINGINTERRUPT
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_spiModem->usingInterrupt(digitalPinToInterrupt(_dio0));
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#endif
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// make function available
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extern void onDio0Rise();
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@ -2136,9 +2164,9 @@ void sx128x::onReceive(void(*callback)(uint8_t, int))
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attachInterrupt(digitalPinToInterrupt(_dio0), onDio0Rise, RISING);
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} else {
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detachInterrupt(digitalPinToInterrupt(_dio0));
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//#ifdef SPI_HAS_NOTUSINGINTERRUPT
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// _spiModem->notUsingInterrupt(digitalPinToInterrupt(_dio0));
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//#endif
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#ifdef SPI_HAS_NOTUSINGINTERRUPT
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_spiModem->notUsingInterrupt(digitalPinToInterrupt(_dio0));
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#endif
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}
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}
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@ -2157,7 +2185,12 @@ void sx128x::receive(int size)
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rxAntEnable();
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uint8_t mode[3] = {0xFF, 0xFF, 0xFF}; // continuous mode
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// On the SX1280, there is a bug which can cause the busy line
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// to remain high if a high amount of packets are received when
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// in continuous RX mode. This is documented as Errata 16.1 in
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// the SX1280 datasheet v3.2 (page 149)
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// Therefore, the modem is set to single RX mode below instead.
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uint8_t mode[3] = {0}; // single RX mode
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executeOpcode(OP_RX_8X, mode, 3);
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}
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@ -2561,38 +2594,22 @@ void sx128x::implicitHeaderMode()
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void sx128x::handleDio0Rise()
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{
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uint8_t buf[2];
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// received a packet
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_packetIndex = 0;
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buf[0] = 0x00;
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buf[1] = 0x00;
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uint8_t rxbuf[2] = {0};
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executeOpcodeRead(OP_RX_BUFFER_STATUS_8X, rxbuf, 2);
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executeOpcodeRead(OP_GET_IRQ_STATUS_8X, buf, 2);
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executeOpcode(OP_CLEAR_IRQ_STATUS_8X, buf, 2);
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if ((buf[1] & IRQ_PAYLOAD_CRC_ERROR_MASK_8X) == 0) {
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// received a packet
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_packetIndex = 0;
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uint8_t rxbuf[2] = {0};
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executeOpcodeRead(OP_RX_BUFFER_STATUS_8X, rxbuf, 2);
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// If implicit header mode is enabled, read packet length as payload length instead.
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// See SX1280 datasheet v3.2, page 92
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if (_implicitHeaderMode == 0x80) {
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_rxPacketLength = _payloadLength;
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} else {
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_rxPacketLength = rxbuf[0];
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}
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_fifo_rx_addr_ptr = rxbuf[1];
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readBuffer(_packet, _rxPacketLength);
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if (_onReceive) {
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_onReceive(_index, _rxPacketLength);
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}
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// If implicit header mode is enabled, read packet length as payload length instead.
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// See SX1280 datasheet v3.2, page 92
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if (_implicitHeaderMode == 0x80) {
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_rxPacketLength = _payloadLength;
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} else {
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_rxPacketLength = rxbuf[0];
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}
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if (_onReceive) {
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_onReceive(_index, _rxPacketLength);
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}
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}
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@ -2622,7 +2639,7 @@ void sx128x::updateBitrate() {
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}
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}
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void sx128x::clearIRQStatus() {
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bool ISR_VECT sx128x::getPacketValidity() {
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uint8_t buf[2];
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buf[0] = 0x00;
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@ -2631,4 +2648,10 @@ void sx128x::clearIRQStatus() {
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executeOpcodeRead(OP_GET_IRQ_STATUS_8X, buf, 2);
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executeOpcode(OP_CLEAR_IRQ_STATUS_8X, buf, 2);
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if ((buf[1] & IRQ_PAYLOAD_CRC_ERROR_MASK_8X) == 0) {
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return true;
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} else {
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return false;
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}
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}
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