mirror of
https://github.com/markqvist/RNode_Firmware.git
synced 2024-10-01 03:15:39 -04:00
592 lines
13 KiB
C++
592 lines
13 KiB
C++
// Copyright (c) Sandeep Mistry. All rights reserved.
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// Licensed under the MIT license.
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// Modifications and additions copyright 2018 by Mark Qvist
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// Obviously still under the MIT license.
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#include <LoRa.h>
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// Registers
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#define REG_FIFO 0x00
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#define REG_OP_MODE 0x01
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#define REG_FRF_MSB 0x06
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#define REG_FRF_MID 0x07
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#define REG_FRF_LSB 0x08
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#define REG_PA_CONFIG 0x09
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#define REG_LNA 0x0c
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#define REG_FIFO_ADDR_PTR 0x0d
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#define REG_FIFO_TX_BASE_ADDR 0x0e
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#define REG_FIFO_RX_BASE_ADDR 0x0f
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#define REG_FIFO_RX_CURRENT_ADDR 0x10
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#define REG_IRQ_FLAGS 0x12
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#define REG_RX_NB_BYTES 0x13
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#define REG_MODEM_STAT 0x18
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#define REG_PKT_SNR_VALUE 0x19
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#define REG_PKT_RSSI_VALUE 0x1a
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#define REG_MODEM_CONFIG_1 0x1d
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#define REG_MODEM_CONFIG_2 0x1e
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#define REG_PREAMBLE_MSB 0x20
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#define REG_PREAMBLE_LSB 0x21
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#define REG_PAYLOAD_LENGTH 0x22
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#define REG_MODEM_CONFIG_3 0x26
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#define REG_FREQ_ERROR_MSB 0x28
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#define REG_FREQ_ERROR_MID 0x29
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#define REG_FREQ_ERROR_LSB 0x2a
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#define REG_RSSI_WIDEBAND 0x2c
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#define REG_DETECTION_OPTIMIZE 0x31
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#define REG_DETECTION_THRESHOLD 0x37
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#define REG_SYNC_WORD 0x39
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#define REG_DIO_MAPPING_1 0x40
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#define REG_VERSION 0x42
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// Modes
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#define MODE_LONG_RANGE_MODE 0x80
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#define MODE_SLEEP 0x00
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#define MODE_STDBY 0x01
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#define MODE_TX 0x03
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#define MODE_RX_CONTINUOUS 0x05
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#define MODE_RX_SINGLE 0x06
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// PA config
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#define PA_BOOST 0x80
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// IRQ masks
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#define IRQ_TX_DONE_MASK 0x08
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#define IRQ_PAYLOAD_CRC_ERROR_MASK 0x20
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#define IRQ_RX_DONE_MASK 0x40
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#define MAX_PKT_LENGTH 255
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LoRaClass::LoRaClass() :
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_spiSettings(8E6, MSBFIRST, SPI_MODE0),
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_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN),
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_frequency(0),
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_packetIndex(0),
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_implicitHeaderMode(0),
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_onReceive(NULL)
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{
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// overide Stream timeout value
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setTimeout(0);
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}
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int LoRaClass::begin(long frequency)
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{
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// setup pins
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pinMode(_ss, OUTPUT);
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// set SS high
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digitalWrite(_ss, HIGH);
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if (_reset != -1) {
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pinMode(_reset, OUTPUT);
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// perform reset
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digitalWrite(_reset, LOW);
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delay(10);
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digitalWrite(_reset, HIGH);
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delay(10);
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}
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// start SPI
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SPI.begin();
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// check version
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uint8_t version = readRegister(REG_VERSION);
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if (version != 0x12) {
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return 0;
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}
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// put in sleep mode
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sleep();
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// set frequency
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setFrequency(frequency);
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// set base addresses
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writeRegister(REG_FIFO_TX_BASE_ADDR, 0);
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writeRegister(REG_FIFO_RX_BASE_ADDR, 0);
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// set LNA boost
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writeRegister(REG_LNA, readRegister(REG_LNA) | 0x03);
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// set auto AGC
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writeRegister(REG_MODEM_CONFIG_3, 0x04);
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// set output power to 17 dBm
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setTxPower(2);
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// put in standby mode
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idle();
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return 1;
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}
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void LoRaClass::end()
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{
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// put in sleep mode
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sleep();
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// stop SPI
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SPI.end();
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}
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int LoRaClass::beginPacket(int implicitHeader)
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{
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// put in standby mode
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idle();
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if (implicitHeader) {
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implicitHeaderMode();
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} else {
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explicitHeaderMode();
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}
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// reset FIFO address and paload length
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writeRegister(REG_FIFO_ADDR_PTR, 0);
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writeRegister(REG_PAYLOAD_LENGTH, 0);
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return 1;
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}
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int LoRaClass::endPacket()
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{
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// put in TX mode
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writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_TX);
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// wait for TX done
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while ((readRegister(REG_IRQ_FLAGS) & IRQ_TX_DONE_MASK) == 0) {
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yield();
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}
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// clear IRQ's
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writeRegister(REG_IRQ_FLAGS, IRQ_TX_DONE_MASK);
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return 1;
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}
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int LoRaClass::parsePacket(int size)
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{
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int packetLength = 0;
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int irqFlags = readRegister(REG_IRQ_FLAGS);
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if (size > 0) {
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implicitHeaderMode();
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writeRegister(REG_PAYLOAD_LENGTH, size & 0xff);
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} else {
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explicitHeaderMode();
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}
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// clear IRQ's
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writeRegister(REG_IRQ_FLAGS, irqFlags);
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if ((irqFlags & IRQ_RX_DONE_MASK) && (irqFlags & IRQ_PAYLOAD_CRC_ERROR_MASK) == 0) {
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// received a packet
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_packetIndex = 0;
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// read packet length
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if (_implicitHeaderMode) {
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packetLength = readRegister(REG_PAYLOAD_LENGTH);
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} else {
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packetLength = readRegister(REG_RX_NB_BYTES);
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}
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// set FIFO address to current RX address
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writeRegister(REG_FIFO_ADDR_PTR, readRegister(REG_FIFO_RX_CURRENT_ADDR));
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// put in standby mode
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idle();
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} else if (readRegister(REG_OP_MODE) != (MODE_LONG_RANGE_MODE | MODE_RX_SINGLE)) {
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// not currently in RX mode
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// reset FIFO address
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writeRegister(REG_FIFO_ADDR_PTR, 0);
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// put in single RX mode
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writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_SINGLE);
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}
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return packetLength;
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}
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uint8_t LoRaClass::modemStatus() {
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return readRegister(REG_MODEM_STAT);
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}
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int LoRaClass::packetRssi()
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{
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return (readRegister(REG_PKT_RSSI_VALUE) - (_frequency < 868E6 ? 164 : 157));
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}
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float LoRaClass::packetSnr()
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{
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return ((int8_t)readRegister(REG_PKT_SNR_VALUE)) * 0.25;
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}
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long LoRaClass::packetFrequencyError()
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{
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int32_t freqError = 0;
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freqError = static_cast<int32_t>(readRegister(REG_FREQ_ERROR_MSB) & B111);
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freqError <<= 8L;
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freqError += static_cast<int32_t>(readRegister(REG_FREQ_ERROR_MID));
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freqError <<= 8L;
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freqError += static_cast<int32_t>(readRegister(REG_FREQ_ERROR_LSB));
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if (readRegister(REG_FREQ_ERROR_MSB) & B1000) { // Sign bit is on
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freqError -= 524288; // B1000'0000'0000'0000'0000
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}
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const float fXtal = 32E6; // FXOSC: crystal oscillator (XTAL) frequency (2.5. Chip Specification, p. 14)
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const float fError = ((static_cast<float>(freqError) * (1L << 24)) / fXtal) * (getSignalBandwidth() / 500000.0f); // p. 37
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return static_cast<long>(fError);
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}
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size_t LoRaClass::write(uint8_t byte)
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{
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return write(&byte, sizeof(byte));
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}
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size_t LoRaClass::write(const uint8_t *buffer, size_t size)
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{
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int currentLength = readRegister(REG_PAYLOAD_LENGTH);
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// check size
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if ((currentLength + size) > MAX_PKT_LENGTH) {
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size = MAX_PKT_LENGTH - currentLength;
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}
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// write data
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for (size_t i = 0; i < size; i++) {
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writeRegister(REG_FIFO, buffer[i]);
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}
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// update length
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writeRegister(REG_PAYLOAD_LENGTH, currentLength + size);
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return size;
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}
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int LoRaClass::available()
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{
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return (readRegister(REG_RX_NB_BYTES) - _packetIndex);
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}
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int LoRaClass::read()
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{
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if (!available()) {
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return -1;
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}
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_packetIndex++;
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return readRegister(REG_FIFO);
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}
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int LoRaClass::peek()
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{
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if (!available()) {
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return -1;
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}
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// store current FIFO address
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int currentAddress = readRegister(REG_FIFO_ADDR_PTR);
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// read
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uint8_t b = readRegister(REG_FIFO);
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// restore FIFO address
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writeRegister(REG_FIFO_ADDR_PTR, currentAddress);
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return b;
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}
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void LoRaClass::flush()
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{
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}
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void LoRaClass::onReceive(void(*callback)(int))
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{
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_onReceive = callback;
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if (callback) {
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pinMode(_dio0, INPUT);
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writeRegister(REG_DIO_MAPPING_1, 0x00);
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#ifdef SPI_HAS_NOTUSINGINTERRUPT
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SPI.usingInterrupt(digitalPinToInterrupt(_dio0));
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#endif
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attachInterrupt(digitalPinToInterrupt(_dio0), LoRaClass::onDio0Rise, RISING);
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} else {
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detachInterrupt(digitalPinToInterrupt(_dio0));
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#ifdef SPI_HAS_NOTUSINGINTERRUPT
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SPI.notUsingInterrupt(digitalPinToInterrupt(_dio0));
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#endif
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}
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}
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void LoRaClass::receive(int size)
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{
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if (size > 0) {
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implicitHeaderMode();
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writeRegister(REG_PAYLOAD_LENGTH, size & 0xff);
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} else {
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explicitHeaderMode();
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}
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writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_RX_CONTINUOUS);
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}
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void LoRaClass::idle()
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{
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writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_STDBY);
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}
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void LoRaClass::sleep()
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{
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writeRegister(REG_OP_MODE, MODE_LONG_RANGE_MODE | MODE_SLEEP);
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}
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void LoRaClass::setTxPower(int level, int outputPin)
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{
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if (PA_OUTPUT_RFO_PIN == outputPin) {
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// RFO
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if (level < 0) {
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level = 0;
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} else if (level > 14) {
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level = 14;
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}
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writeRegister(REG_PA_CONFIG, 0x70 | level);
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} else {
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// PA BOOST
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if (level < 2) {
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level = 2;
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} else if (level > 17) {
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level = 17;
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}
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writeRegister(REG_PA_CONFIG, PA_BOOST | (level - 2));
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}
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}
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void LoRaClass::setFrequency(long frequency) {
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_frequency = frequency;
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uint32_t frf = ((uint64_t)frequency << 19) / 32000000;
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writeRegister(REG_FRF_MSB, (uint8_t)(frf >> 16));
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writeRegister(REG_FRF_MID, (uint8_t)(frf >> 8));
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writeRegister(REG_FRF_LSB, (uint8_t)(frf >> 0));
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}
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uint32_t LoRaClass::getFrequency() {
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uint8_t msb = readRegister(REG_FRF_MSB);
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uint8_t mid = readRegister(REG_FRF_MID);
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uint8_t lsb = readRegister(REG_FRF_LSB);
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uint32_t frf = ((uint32_t)msb << 16) | ((uint32_t)mid << 8) | (uint32_t)lsb;
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uint64_t frm = (uint64_t)frf*32000000;
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uint32_t frequency = (frm >> 19);
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return frequency;
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}
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void LoRaClass::setSpreadingFactor(int sf)
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{
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if (sf < 6) {
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sf = 6;
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} else if (sf > 12) {
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sf = 12;
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}
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if (sf == 6) {
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writeRegister(REG_DETECTION_OPTIMIZE, 0xc5);
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writeRegister(REG_DETECTION_THRESHOLD, 0x0c);
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} else {
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writeRegister(REG_DETECTION_OPTIMIZE, 0xc3);
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writeRegister(REG_DETECTION_THRESHOLD, 0x0a);
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}
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writeRegister(REG_MODEM_CONFIG_2, (readRegister(REG_MODEM_CONFIG_2) & 0x0f) | ((sf << 4) & 0xf0));
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}
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long LoRaClass::getSignalBandwidth()
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{
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byte bw = (readRegister(REG_MODEM_CONFIG_1) >> 4);
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switch (bw) {
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case 0: return 7.8E3;
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case 1: return 10.4E3;
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case 2: return 15.6E3;
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case 3: return 20.8E3;
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case 4: return 31.25E3;
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case 5: return 41.7E3;
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case 6: return 62.5E3;
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case 7: return 125E3;
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case 8: return 250E3;
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case 9: return 500E3;
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}
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}
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void LoRaClass::setSignalBandwidth(long sbw)
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{
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int bw;
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if (sbw <= 7.8E3) {
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bw = 0;
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} else if (sbw <= 10.4E3) {
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bw = 1;
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} else if (sbw <= 15.6E3) {
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bw = 2;
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} else if (sbw <= 20.8E3) {
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bw = 3;
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} else if (sbw <= 31.25E3) {
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bw = 4;
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} else if (sbw <= 41.7E3) {
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bw = 5;
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} else if (sbw <= 62.5E3) {
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bw = 6;
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} else if (sbw <= 125E3) {
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bw = 7;
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} else if (sbw <= 250E3) {
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bw = 8;
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} else /*if (sbw <= 250E3)*/ {
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bw = 9;
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}
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writeRegister(REG_MODEM_CONFIG_1, (readRegister(REG_MODEM_CONFIG_1) & 0x0f) | (bw << 4));
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}
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void LoRaClass::setCodingRate4(int denominator)
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{
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if (denominator < 5) {
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denominator = 5;
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} else if (denominator > 8) {
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denominator = 8;
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}
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int cr = denominator - 4;
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writeRegister(REG_MODEM_CONFIG_1, (readRegister(REG_MODEM_CONFIG_1) & 0xf1) | (cr << 1));
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}
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void LoRaClass::setPreambleLength(long length)
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{
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writeRegister(REG_PREAMBLE_MSB, (uint8_t)(length >> 8));
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writeRegister(REG_PREAMBLE_LSB, (uint8_t)(length >> 0));
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}
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void LoRaClass::setSyncWord(int sw)
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{
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writeRegister(REG_SYNC_WORD, sw);
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}
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void LoRaClass::enableCrc()
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{
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writeRegister(REG_MODEM_CONFIG_2, readRegister(REG_MODEM_CONFIG_2) | 0x04);
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}
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void LoRaClass::disableCrc()
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{
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writeRegister(REG_MODEM_CONFIG_2, readRegister(REG_MODEM_CONFIG_2) & 0xfb);
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}
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byte LoRaClass::random()
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{
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return readRegister(REG_RSSI_WIDEBAND);
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}
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void LoRaClass::setPins(int ss, int reset, int dio0)
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{
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_ss = ss;
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_reset = reset;
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_dio0 = dio0;
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}
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void LoRaClass::setSPIFrequency(uint32_t frequency)
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{
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_spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0);
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}
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void LoRaClass::dumpRegisters(Stream& out)
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{
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for (int i = 0; i < 128; i++) {
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out.print("0x");
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out.print(i, HEX);
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out.print(": 0x");
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out.println(readRegister(i), HEX);
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}
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}
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void LoRaClass::explicitHeaderMode()
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{
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_implicitHeaderMode = 0;
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writeRegister(REG_MODEM_CONFIG_1, readRegister(REG_MODEM_CONFIG_1) & 0xfe);
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}
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void LoRaClass::implicitHeaderMode()
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{
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_implicitHeaderMode = 1;
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writeRegister(REG_MODEM_CONFIG_1, readRegister(REG_MODEM_CONFIG_1) | 0x01);
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}
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void LoRaClass::handleDio0Rise()
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{
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int irqFlags = readRegister(REG_IRQ_FLAGS);
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// clear IRQ's
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writeRegister(REG_IRQ_FLAGS, irqFlags);
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if ((irqFlags & IRQ_PAYLOAD_CRC_ERROR_MASK) == 0) {
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// received a packet
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_packetIndex = 0;
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// read packet length
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int packetLength = _implicitHeaderMode ? readRegister(REG_PAYLOAD_LENGTH) : readRegister(REG_RX_NB_BYTES);
|
|
|
|
// set FIFO address to current RX address
|
|
writeRegister(REG_FIFO_ADDR_PTR, readRegister(REG_FIFO_RX_CURRENT_ADDR));
|
|
|
|
if (_onReceive) {
|
|
_onReceive(packetLength);
|
|
}
|
|
|
|
// reset FIFO address
|
|
writeRegister(REG_FIFO_ADDR_PTR, 0);
|
|
}
|
|
}
|
|
|
|
uint8_t LoRaClass::readRegister(uint8_t address)
|
|
{
|
|
return singleTransfer(address & 0x7f, 0x00);
|
|
}
|
|
|
|
void LoRaClass::writeRegister(uint8_t address, uint8_t value)
|
|
{
|
|
singleTransfer(address | 0x80, value);
|
|
}
|
|
|
|
uint8_t LoRaClass::singleTransfer(uint8_t address, uint8_t value)
|
|
{
|
|
uint8_t response;
|
|
|
|
digitalWrite(_ss, LOW);
|
|
|
|
SPI.beginTransaction(_spiSettings);
|
|
SPI.transfer(address);
|
|
response = SPI.transfer(value);
|
|
SPI.endTransaction();
|
|
|
|
digitalWrite(_ss, HIGH);
|
|
|
|
return response;
|
|
}
|
|
|
|
void LoRaClass::onDio0Rise()
|
|
{
|
|
LoRa.handleDio0Rise();
|
|
}
|
|
|
|
LoRaClass LoRa; |