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Cleanup
This commit is contained in:
Mark Qvist
parent
217db4bcd3
commit
eb168d4734
517
sx126x.cpp
517
sx126x.cpp
@ -1,9 +1,6 @@
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// Copyright (c) Sandeep Mistry. All rights reserved.
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// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
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// Licensed under the MIT license.
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// Modifications and additions copyright 2024 by Mark Qvist
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// Obviously still under the MIT license.
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#include "Boards.h"
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#if MODEM == SX1262
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@ -24,19 +21,19 @@
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#define OP_TX_6X 0x83
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#define OP_RX_6X 0x82
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#define OP_PA_CONFIG_6X 0x95
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#define OP_SET_IRQ_FLAGS_6X 0x08 // also provides info such as
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#define OP_SET_IRQ_FLAGS_6X 0x08 // Also provides info such as
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// preamble detection, etc for
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// knowing when it's safe to switch
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// antenna modes
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#define OP_CLEAR_IRQ_STATUS_6X 0x02
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#define OP_GET_IRQ_STATUS_6X 0x12
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#define OP_RX_BUFFER_STATUS_6X 0x13
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#define OP_PACKET_STATUS_6X 0x14 // get snr & rssi of last packet
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#define OP_PACKET_STATUS_6X 0x14 // Get snr & rssi of last packet
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#define OP_CURRENT_RSSI_6X 0x15
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#define OP_MODULATION_PARAMS_6X 0x8B // bw, sf, cr, etc.
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#define OP_PACKET_PARAMS_6X 0x8C // crc, preamble, payload length, etc.
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#define OP_MODULATION_PARAMS_6X 0x8B // BW, SF, CR, etc.
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#define OP_PACKET_PARAMS_6X 0x8C // CRC, preamble, payload length, etc.
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#define OP_STATUS_6X 0xC0
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#define OP_TX_PARAMS_6X 0x8E // set dbm, etc
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#define OP_TX_PARAMS_6X 0x8E // Set dbm, etc
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#define OP_PACKET_TYPE_6X 0x8A
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#define OP_BUFFER_BASE_ADDR_6X 0x8F
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#define OP_READ_REGISTER_6X 0x1D
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@ -63,7 +60,7 @@
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#define OP_FIFO_WRITE_6X 0x0E
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#define OP_FIFO_READ_6X 0x1E
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#define REG_OCP_6X 0x08E7
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#define REG_LNA_6X 0x08AC // no agc in sx1262
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#define REG_LNA_6X 0x08AC // No agc in sx1262
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#define REG_SYNC_WORD_MSB_6X 0x0740
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#define REG_SYNC_WORD_LSB_6X 0x0741
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#define REG_PAYLOAD_LENGTH_6X 0x0702 // https://github.com/beegee-tokyo/SX126x-Arduino/blob/master/src/radio/sx126x/sx126x.h#L98
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@ -118,10 +115,7 @@ sx126x::sx126x() :
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_packet({0}),
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_preinit_done(false),
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_onReceive(NULL)
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{
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// overide Stream timeout value
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setTimeout(0);
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}
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{ setTimeout(0); }
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bool sx126x::preInit() {
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pinMode(_ss, OUTPUT);
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@ -133,7 +127,7 @@ bool sx126x::preInit() {
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SPI.begin();
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#endif
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// check version (retry for up to 2 seconds)
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// Check version (retry for up to 2 seconds)
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// TODO: Actually read version registers, not syncwords
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long start = millis();
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uint8_t syncmsb;
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@ -154,31 +148,24 @@ bool sx126x::preInit() {
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return true;
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}
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uint8_t ISR_VECT sx126x::readRegister(uint16_t address)
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{
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uint8_t ISR_VECT sx126x::readRegister(uint16_t address) {
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return singleTransfer(OP_READ_REGISTER_6X, address, 0x00);
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}
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void sx126x::writeRegister(uint16_t address, uint8_t value)
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{
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void sx126x::writeRegister(uint16_t address, uint8_t value) {
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singleTransfer(OP_WRITE_REGISTER_6X, address, value);
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}
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uint8_t ISR_VECT sx126x::singleTransfer(uint8_t opcode, uint16_t address, uint8_t value)
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{
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uint8_t ISR_VECT sx126x::singleTransfer(uint8_t opcode, uint16_t address, uint8_t value) {
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waitOnBusy();
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uint8_t response;
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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SPI.transfer((address & 0xFF00) >> 8);
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SPI.transfer(address & 0x00FF);
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if (opcode == OP_READ_REGISTER_6X) {
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SPI.transfer(0x00);
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}
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if (opcode == OP_READ_REGISTER_6X) { SPI.transfer(0x00); }
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response = SPI.transfer(value);
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SPI.endTransaction();
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@ -187,15 +174,12 @@ uint8_t ISR_VECT sx126x::singleTransfer(uint8_t opcode, uint16_t address, uint8_
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return response;
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}
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void sx126x::rxAntEnable()
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{
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if (_rxen != -1) {
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digitalWrite(_rxen, HIGH);
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}
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void sx126x::rxAntEnable() {
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if (_rxen != -1) { digitalWrite(_rxen, HIGH); }
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}
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void sx126x::loraMode() {
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// enable lora mode on the SX1262 chip
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// Enable lora mode on the SX1262 chip
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uint8_t mode = MODE_LONG_RANGE_MODE_6X;
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executeOpcode(OP_PACKET_TYPE_6X, &mode, 1);
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}
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@ -203,141 +187,90 @@ void sx126x::loraMode() {
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void sx126x::waitOnBusy() {
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unsigned long time = millis();
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if (_busy != -1) {
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while (digitalRead(_busy) == HIGH)
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{
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if (millis() >= (time + 100)) {
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break;
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}
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// do nothing
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while (digitalRead(_busy) == HIGH) {
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if (millis() >= (time + 100)) { break; }
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}
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}
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}
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void sx126x::executeOpcode(uint8_t opcode, uint8_t *buffer, uint8_t size)
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{
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void sx126x::executeOpcode(uint8_t opcode, uint8_t *buffer, uint8_t size) {
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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for (int i = 0; i < size; i++)
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{
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SPI.transfer(buffer[i]);
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}
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for (int i = 0; i < size; i++) { SPI.transfer(buffer[i]); }
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::executeOpcodeRead(uint8_t opcode, uint8_t *buffer, uint8_t size)
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{
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void sx126x::executeOpcodeRead(uint8_t opcode, uint8_t *buffer, uint8_t size) {
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(opcode);
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SPI.transfer(0x00);
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for (int i = 0; i < size; i++)
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{
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buffer[i] = SPI.transfer(0x00);
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}
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for (int i = 0; i < size; i++) { buffer[i] = SPI.transfer(0x00); }
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::writeBuffer(const uint8_t* buffer, size_t size)
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{
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void sx126x::writeBuffer(const uint8_t* buffer, size_t size) {
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(OP_FIFO_WRITE_6X);
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SPI.transfer(_fifo_tx_addr_ptr);
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for (int i = 0; i < size; i++)
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{
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SPI.transfer(buffer[i]);
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_fifo_tx_addr_ptr++;
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}
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for (int i = 0; i < size; i++) { SPI.transfer(buffer[i]); _fifo_tx_addr_ptr++; }
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::readBuffer(uint8_t* buffer, size_t size)
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{
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void sx126x::readBuffer(uint8_t* buffer, size_t size) {
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waitOnBusy();
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digitalWrite(_ss, LOW);
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SPI.beginTransaction(_spiSettings);
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SPI.transfer(OP_FIFO_READ_6X);
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SPI.transfer(_fifo_rx_addr_ptr);
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SPI.transfer(0x00);
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for (int i = 0; i < size; i++)
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{
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buffer[i] = SPI.transfer(0x00);
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}
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for (int i = 0; i < size; i++) { buffer[i] = SPI.transfer(0x00); }
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SPI.endTransaction();
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digitalWrite(_ss, HIGH);
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}
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void sx126x::setModulationParams(uint8_t sf, uint8_t bw, uint8_t cr, int ldro) {
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// because there is no access to these registers on the sx1262, we have
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// Because there is no access to these registers on the sx1262, we have
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// to set all these parameters at once or not at all.
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uint8_t buf[8];
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buf[0] = sf;
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buf[1] = bw;
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buf[2] = cr;
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// low data rate toggle
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buf[3] = ldro;
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// unused params in LoRa mode
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buf[4] = 0x00;
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buf[3] = ldro; // Low data rate toggle
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buf[4] = 0x00; // Unused params in LoRa mode
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buf[5] = 0x00;
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buf[6] = 0x00;
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buf[7] = 0x00;
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executeOpcode(OP_MODULATION_PARAMS_6X, buf, 8);
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}
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void sx126x::setPacketParams(long preamble, uint8_t headermode, uint8_t length, uint8_t crc) {
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// because there is no access to these registers on the sx1262, we have
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// Because there is no access to these registers on the sx1262, we have
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// to set all these parameters at once or not at all.
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uint8_t buf[9];
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buf[0] = uint8_t((preamble & 0xFF00) >> 8);
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buf[1] = uint8_t((preamble & 0x00FF));
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buf[2] = headermode;
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buf[3] = length;
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buf[4] = crc;
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// standard IQ setting (no inversion)
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buf[5] = 0x00;
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// unused params
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buf[6] = 0x00;
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buf[5] = 0x00; // standard IQ setting (no inversion)
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buf[6] = 0x00; // unused params
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buf[7] = 0x00;
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buf[8] = 0x00;
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executeOpcode(OP_PACKET_PARAMS_6X, buf, 9);
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}
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void sx126x::reset(void) {
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if (_reset != -1) {
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pinMode(_reset, OUTPUT);
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// perform reset
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digitalWrite(_reset, LOW);
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delay(10);
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digitalWrite(_reset, HIGH);
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@ -350,7 +283,7 @@ void sx126x::calibrate(void) {
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uint8_t mode_byte = MODE_STDBY_RC_6X;
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executeOpcode(OP_STANDBY_6X, &mode_byte, 1);
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// calibrate RC64k, RC13M, PLL, ADC and image
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// Calibrate RC64k, RC13M, PLL, ADC and image
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uint8_t calibrate = MASK_CALIBRATE_ALL;
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executeOpcode(OP_CALIBRATE_6X, &calibrate, 1);
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@ -360,55 +293,25 @@ void sx126x::calibrate(void) {
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void sx126x::calibrate_image(long frequency) {
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uint8_t image_freq[2] = {0};
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if (frequency >= 430E6 && frequency <= 440E6) {
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image_freq[0] = 0x6B;
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image_freq[1] = 0x6F;
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}
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else if (frequency >= 470E6 && frequency <= 510E6) {
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image_freq[0] = 0x75;
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image_freq[1] = 0x81;
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}
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else if (frequency >= 779E6 && frequency <= 787E6) {
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image_freq[0] = 0xC1;
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image_freq[1] = 0xC5;
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}
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else if (frequency >= 863E6 && frequency <= 870E6) {
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image_freq[0] = 0xD7;
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image_freq[1] = 0xDB;
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}
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else if (frequency >= 902E6 && frequency <= 928E6) {
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image_freq[0] = 0xE1;
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image_freq[1] = 0xE9;
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}
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if (frequency >= 430E6 && frequency <= 440E6) { image_freq[0] = 0x6B; image_freq[1] = 0x6F; }
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else if (frequency >= 470E6 && frequency <= 510E6) { image_freq[0] = 0x75; image_freq[1] = 0x81; }
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else if (frequency >= 779E6 && frequency <= 787E6) { image_freq[0] = 0xC1; image_freq[1] = 0xC5; }
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else if (frequency >= 863E6 && frequency <= 870E6) { image_freq[0] = 0xD7; image_freq[1] = 0xDB; }
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else if (frequency >= 902E6 && frequency <= 928E6) { image_freq[0] = 0xE1; image_freq[1] = 0xE9; }
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executeOpcode(OP_CALIBRATE_IMAGE_6X, image_freq, 2);
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waitOnBusy();
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}
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int sx126x::begin(long frequency)
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{
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int sx126x::begin(long frequency) {
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reset();
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if (_busy != -1) {
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pinMode(_busy, INPUT);
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}
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if (!_preinit_done) {
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if (!preInit()) {
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return false;
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}
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}
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if (_rxen != -1) {
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pinMode(_rxen, OUTPUT);
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}
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if (_busy != -1) { pinMode(_busy, INPUT); }
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if (!_preinit_done) { if (!preInit()) { return false; } }
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if (_rxen != -1) { pinMode(_rxen, OUTPUT); }
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calibrate();
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calibrate_image(frequency);
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enableTCXO();
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loraMode();
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standby();
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@ -422,18 +325,11 @@ int sx126x::begin(long frequency)
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#endif
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rxAntEnable();
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setFrequency(frequency);
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// set output power to 2 dBm
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setTxPower(2);
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enableCrc();
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// set LNA boost
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writeRegister(REG_LNA_6X, 0x96);
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// set base addresses
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uint8_t basebuf[2] = {0};
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writeRegister(REG_LNA_6X, 0x96); // Set LNA boost
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uint8_t basebuf[2] = {0}; // Set base addresses
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executeOpcode(OP_BUFFER_BASE_ADDR_6X, basebuf, 2);
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setModulationParams(_sf, _bw, _cr, _ldro);
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@ -442,26 +338,12 @@ int sx126x::begin(long frequency)
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return 1;
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}
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void sx126x::end()
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{
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// put in sleep mode
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sleep();
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void sx126x::end() { sleep(); SPI.end(); _preinit_done = false; }
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// stop SPI
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SPI.end();
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_preinit_done = false;
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}
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int sx126x::beginPacket(int implicitHeader)
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{
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int sx126x::beginPacket(int implicitHeader) {
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standby();
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if (implicitHeader) {
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implicitHeaderMode();
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} else {
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explicitHeaderMode();
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}
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if (implicitHeader) { implicitHeaderMode(); }
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else { explicitHeaderMode(); }
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_payloadLength = 0;
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_fifo_tx_addr_ptr = 0;
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@ -470,24 +352,19 @@ int sx126x::beginPacket(int implicitHeader)
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return 1;
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}
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int sx126x::endPacket()
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{
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int sx126x::endPacket() {
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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// put in single TX mode
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uint8_t timeout[3] = {0};
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uint8_t timeout[3] = {0}; // Put in single TX mode
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executeOpcode(OP_TX_6X, timeout, 3);
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uint8_t buf[2];
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buf[0] = 0x00;
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buf[1] = 0x00;
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executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
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// Wait for TX done
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bool timed_out = false;
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uint32_t w_timeout = millis()+LORA_MODEM_TIMEOUT_MS;
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// wait for TX done
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while ((millis() < w_timeout) && ((buf[1] & IRQ_TX_DONE_MASK_6X) == 0)) {
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buf[0] = 0x00;
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buf[1] = 0x00;
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@ -497,32 +374,24 @@ int sx126x::endPacket()
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if (!(millis() < w_timeout)) { timed_out = true; }
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// clear IRQ's
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// Clear IRQs
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uint8_t mask[2];
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mask[0] = 0x00;
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mask[1] = IRQ_TX_DONE_MASK_6X;
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executeOpcode(OP_CLEAR_IRQ_STATUS_6X, mask, 2);
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if (timed_out) {
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return 0;
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} else {
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return 1;
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}
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if (timed_out) { return 0; } else { return 1; }
|
||||
}
|
||||
|
||||
uint8_t sx126x::modemStatus() {
|
||||
// imitate the register status from the sx1276 / 78
|
||||
// Imitate the register status from the sx1276 / 78
|
||||
uint8_t buf[2] = {0};
|
||||
|
||||
executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
|
||||
uint8_t clearbuf[2] = {0};
|
||||
uint8_t byte = 0x00;
|
||||
|
||||
if ((buf[1] & IRQ_PREAMBLE_DET_MASK_6X) != 0) {
|
||||
byte = byte | 0x01 | 0x04;
|
||||
// clear register after reading
|
||||
clearbuf[1] = IRQ_PREAMBLE_DET_MASK_6X;
|
||||
clearbuf[1] = IRQ_PREAMBLE_DET_MASK_6X; // Clear register after reading
|
||||
}
|
||||
|
||||
if ((buf[1] & IRQ_HEADER_DET_MASK_6X) != 0) {
|
||||
@ -530,7 +399,6 @@ uint8_t sx126x::modemStatus() {
|
||||
}
|
||||
|
||||
executeOpcode(OP_CLEAR_IRQ_STATUS_6X, clearbuf, 2);
|
||||
|
||||
return byte;
|
||||
}
|
||||
|
||||
@ -555,7 +423,7 @@ uint8_t sx126x::packetRssiRaw() {
|
||||
}
|
||||
|
||||
int ISR_VECT sx126x::packetRssi() {
|
||||
// may need more calculations here
|
||||
// TODO: May need more calculations here
|
||||
uint8_t buf[3] = {0};
|
||||
executeOpcodeRead(OP_PACKET_STATUS_6X, buf, 3);
|
||||
int pkt_rssi = -buf[0] / 2;
|
||||
@ -563,7 +431,7 @@ int ISR_VECT sx126x::packetRssi() {
|
||||
}
|
||||
|
||||
int ISR_VECT sx126x::packetRssi(uint8_t pkt_snr_raw) {
|
||||
// may need more calculations here
|
||||
// TODO: May need more calculations here
|
||||
uint8_t buf[3] = {0};
|
||||
executeOpcodeRead(OP_PACKET_STATUS_6X, buf, 3);
|
||||
int pkt_rssi = -buf[0] / 2;
|
||||
@ -582,50 +450,33 @@ float ISR_VECT sx126x::packetSnr() {
|
||||
return float(buf[1]) * 0.25;
|
||||
}
|
||||
|
||||
long sx126x::packetFrequencyError()
|
||||
{
|
||||
// todo: implement this, no idea how to check it on the sx1262
|
||||
long sx126x::packetFrequencyError() {
|
||||
// TODO: Implement this, no idea how to check it on the sx1262
|
||||
const float fError = 0.0;
|
||||
return static_cast<long>(fError);
|
||||
}
|
||||
|
||||
size_t sx126x::write(uint8_t byte)
|
||||
{
|
||||
return write(&byte, sizeof(byte));
|
||||
}
|
||||
|
||||
size_t sx126x::write(const uint8_t *buffer, size_t size)
|
||||
{
|
||||
if ((_payloadLength + size) > MAX_PKT_LENGTH) {
|
||||
size = MAX_PKT_LENGTH - _payloadLength;
|
||||
}
|
||||
|
||||
// write data
|
||||
size_t sx126x::write(uint8_t byte) { return write(&byte, sizeof(byte)); }
|
||||
size_t sx126x::write(const uint8_t *buffer, size_t size) {
|
||||
if ((_payloadLength + size) > MAX_PKT_LENGTH) { size = MAX_PKT_LENGTH - _payloadLength; }
|
||||
writeBuffer(buffer, size);
|
||||
_payloadLength = _payloadLength + size;
|
||||
return size;
|
||||
}
|
||||
|
||||
int ISR_VECT sx126x::available()
|
||||
{
|
||||
int ISR_VECT sx126x::available() {
|
||||
uint8_t buf[2] = {0};
|
||||
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, buf, 2);
|
||||
return buf[0] - _packetIndex;
|
||||
}
|
||||
|
||||
int ISR_VECT sx126x::read()
|
||||
{
|
||||
if (!available()) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// if received new packet
|
||||
int ISR_VECT sx126x::read(){
|
||||
if (!available()) { return -1; }
|
||||
if (_packetIndex == 0) {
|
||||
uint8_t rxbuf[2] = {0};
|
||||
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
|
||||
int size = rxbuf[0];
|
||||
_fifo_rx_addr_ptr = rxbuf[1];
|
||||
|
||||
readBuffer(_packet, size);
|
||||
}
|
||||
|
||||
@ -634,19 +485,13 @@ int ISR_VECT sx126x::read()
|
||||
return byte;
|
||||
}
|
||||
|
||||
int sx126x::peek()
|
||||
{
|
||||
if (!available()) {
|
||||
return -1;
|
||||
}
|
||||
|
||||
// if received new packet
|
||||
int sx126x::peek() {
|
||||
if (!available()) { return -1; }
|
||||
if (_packetIndex == 0) {
|
||||
uint8_t rxbuf[2] = {0};
|
||||
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
|
||||
int size = rxbuf[0];
|
||||
_fifo_rx_addr_ptr = rxbuf[1];
|
||||
|
||||
readBuffer(_packet, size);
|
||||
}
|
||||
|
||||
@ -654,41 +499,29 @@ int sx126x::peek()
|
||||
return b;
|
||||
}
|
||||
|
||||
void sx126x::flush()
|
||||
{
|
||||
}
|
||||
void sx126x::flush() { }
|
||||
|
||||
void sx126x::onReceive(void(*callback)(int))
|
||||
{
|
||||
void sx126x::onReceive(void(*callback)(int)){
|
||||
_onReceive = callback;
|
||||
|
||||
if (callback) {
|
||||
pinMode(_dio0, INPUT);
|
||||
|
||||
// set preamble and header detection irqs, plus dio0 mask
|
||||
uint8_t buf[8];
|
||||
|
||||
// set irq masks, enable all
|
||||
buf[0] = 0xFF;
|
||||
uint8_t buf[8]; // Set preamble and header detection irqs, plus dio0 mask
|
||||
buf[0] = 0xFF; // Set irq masks, enable all
|
||||
buf[1] = 0xFF;
|
||||
|
||||
// set dio0 masks
|
||||
buf[2] = 0x00;
|
||||
buf[2] = 0x00; // Set dio0 masks
|
||||
buf[3] = IRQ_RX_DONE_MASK_6X;
|
||||
|
||||
// set dio1 masks
|
||||
buf[4] = 0x00;
|
||||
buf[4] = 0x00; // Set dio1 masks
|
||||
buf[5] = 0x00;
|
||||
|
||||
// set dio2 masks
|
||||
buf[6] = 0x00;
|
||||
buf[6] = 0x00; // Set dio2 masks
|
||||
buf[7] = 0x00;
|
||||
|
||||
executeOpcode(OP_SET_IRQ_FLAGS_6X, buf, 8);
|
||||
|
||||
#ifdef SPI_HAS_NOTUSINGINTERRUPT
|
||||
SPI.usingInterrupt(digitalPinToInterrupt(_dio0));
|
||||
#endif
|
||||
attachInterrupt(digitalPinToInterrupt(_dio0), sx126x::onDio0Rise, RISING);
|
||||
|
||||
} else {
|
||||
detachInterrupt(digitalPinToInterrupt(_dio0));
|
||||
#ifdef SPI_HAS_NOTUSINGINTERRUPT
|
||||
@ -697,40 +530,24 @@ void sx126x::onReceive(void(*callback)(int))
|
||||
}
|
||||
}
|
||||
|
||||
void sx126x::receive(int size)
|
||||
{
|
||||
void sx126x::receive(int size) {
|
||||
if (size > 0) {
|
||||
implicitHeaderMode();
|
||||
|
||||
// tell radio payload length
|
||||
_payloadLength = size;
|
||||
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
||||
} else {
|
||||
explicitHeaderMode();
|
||||
}
|
||||
} else { explicitHeaderMode(); }
|
||||
|
||||
if (_rxen != -1) {
|
||||
rxAntEnable();
|
||||
}
|
||||
|
||||
uint8_t mode[3] = {0xFF, 0xFF, 0xFF}; // continuous mode
|
||||
if (_rxen != -1) { rxAntEnable(); }
|
||||
uint8_t mode[3] = {0xFF, 0xFF, 0xFF}; // Continuous mode
|
||||
executeOpcode(OP_RX_6X, mode, 3);
|
||||
}
|
||||
|
||||
void sx126x::standby()
|
||||
{
|
||||
// STDBY_XOSC
|
||||
uint8_t byte = MODE_STDBY_XOSC_6X;
|
||||
// STDBY_RC
|
||||
// uint8_t byte = MODE_STDBY_RC_6X;
|
||||
void sx126x::standby() {
|
||||
uint8_t byte = MODE_STDBY_XOSC_6X; // STDBY_XOSC
|
||||
executeOpcode(OP_STANDBY_6X, &byte, 1);
|
||||
}
|
||||
|
||||
void sx126x::sleep()
|
||||
{
|
||||
uint8_t byte = 0x00;
|
||||
executeOpcode(OP_SLEEP_6X, &byte, 1);
|
||||
}
|
||||
void sx126x::sleep() { uint8_t byte = 0x00; executeOpcode(OP_SLEEP_6X, &byte, 1); }
|
||||
|
||||
void sx126x::enableTCXO() {
|
||||
#if HAS_TCXO
|
||||
@ -755,78 +572,60 @@ void sx126x::enableTCXO() {
|
||||
void sx126x::disableTCXO() { }
|
||||
|
||||
void sx126x::setTxPower(int level, int outputPin) {
|
||||
// currently no low power mode for SX1262 implemented, assuming PA boost
|
||||
// Currently no low power mode for SX1262 implemented, assuming PA boost
|
||||
|
||||
// WORKAROUND - Better Resistance of the SX1262 Tx to Antenna Mismatch, see DS_SX1261-2_V1.2 datasheet chapter 15.2
|
||||
// RegTxClampConfig = @address 0x08D8
|
||||
writeRegister(0x08D8, readRegister(0x08D8) | (0x0F << 1));
|
||||
|
||||
uint8_t pa_buf[4];
|
||||
|
||||
pa_buf[0] = 0x04; // PADutyCycle needs to be 0x04 to achieve 22dBm output, but can be lowered for better efficiency at lower outputs
|
||||
pa_buf[1] = 0x07; // HPMax at 0x07 is maximum supported for SX1262
|
||||
pa_buf[2] = 0x00; // DeviceSel 0x00 for SX1262 (0x01 for SX1261)
|
||||
pa_buf[3] = 0x01; // PALut always 0x01 (reserved according to datasheet)
|
||||
|
||||
executeOpcode(OP_PA_CONFIG_6X, pa_buf, 4); // set pa_config for high power
|
||||
|
||||
if (level > 22) { level = 22; }
|
||||
else if (level < -9) { level = -9; }
|
||||
|
||||
writeRegister(REG_OCP_6X, OCP_TUNED); // Use board-specific tuned OCP
|
||||
|
||||
uint8_t tx_buf[2];
|
||||
|
||||
tx_buf[0] = level;
|
||||
tx_buf[1] = 0x02; // PA ramping time - 40 microseconds
|
||||
|
||||
executeOpcode(OP_TX_PARAMS_6X, tx_buf, 2);
|
||||
|
||||
_txp = level;
|
||||
}
|
||||
|
||||
uint8_t sx126x::getTxPower() {
|
||||
return _txp;
|
||||
}
|
||||
uint8_t sx126x::getTxPower() { return _txp; }
|
||||
|
||||
void sx126x::setFrequency(long frequency) {
|
||||
_frequency = frequency;
|
||||
|
||||
uint8_t buf[4];
|
||||
|
||||
uint32_t freq = (uint32_t)((double)frequency / (double)FREQ_STEP_6X);
|
||||
|
||||
buf[0] = ((freq >> 24) & 0xFF);
|
||||
buf[1] = ((freq >> 16) & 0xFF);
|
||||
buf[2] = ((freq >> 8) & 0xFF);
|
||||
buf[3] = (freq & 0xFF);
|
||||
|
||||
executeOpcode(OP_RF_FREQ_6X, buf, 4);
|
||||
}
|
||||
|
||||
uint32_t sx126x::getFrequency() {
|
||||
// we can't read the frequency on the sx1262 / 80
|
||||
// We can't read the frequency on the sx1262 / 80
|
||||
uint32_t frequency = _frequency;
|
||||
|
||||
return frequency;
|
||||
}
|
||||
|
||||
void sx126x::setSpreadingFactor(int sf)
|
||||
{
|
||||
if (sf < 5) {
|
||||
sf = 5;
|
||||
} else if (sf > 12) {
|
||||
sf = 12;
|
||||
}
|
||||
|
||||
void sx126x::setSpreadingFactor(int sf) {
|
||||
if (sf < 5) { sf = 5; }
|
||||
else if (sf > 12) { sf = 12; }
|
||||
_sf = sf;
|
||||
|
||||
handleLowDataRate();
|
||||
setModulationParams(sf, _bw, _cr, _ldro);
|
||||
}
|
||||
|
||||
long sx126x::getSignalBandwidth()
|
||||
{
|
||||
long sx126x::getSignalBandwidth() {
|
||||
int bw = _bw;
|
||||
switch (bw) {
|
||||
case 0x00: return 7.8E3;
|
||||
@ -844,96 +643,52 @@ long sx126x::getSignalBandwidth()
|
||||
}
|
||||
|
||||
void sx126x::handleLowDataRate(){
|
||||
if ( long( (1<<_sf) / (getSignalBandwidth()/1000)) > 16) {
|
||||
_ldro = 0x01;
|
||||
} else {
|
||||
_ldro = 0x00;
|
||||
}
|
||||
if ( long( (1<<_sf) / (getSignalBandwidth()/1000)) > 16) { _ldro = 0x01; }
|
||||
else { _ldro = 0x00; }
|
||||
}
|
||||
|
||||
void sx126x::optimizeModemSensitivity(){
|
||||
// todo: check if there's anything the sx1262 can do here
|
||||
}
|
||||
// TODO: check if there's anything the sx1262 can do here
|
||||
void sx126x::optimizeModemSensitivity(){ }
|
||||
|
||||
void sx126x::setSignalBandwidth(long sbw)
|
||||
{
|
||||
if (sbw <= 7.8E3) {
|
||||
_bw = 0x00;
|
||||
} else if (sbw <= 10.4E3) {
|
||||
_bw = 0x08;
|
||||
} else if (sbw <= 15.6E3) {
|
||||
_bw = 0x01;
|
||||
} else if (sbw <= 20.8E3) {
|
||||
_bw = 0x09;
|
||||
} else if (sbw <= 31.25E3) {
|
||||
_bw = 0x02;
|
||||
} else if (sbw <= 41.7E3) {
|
||||
_bw = 0x0A;
|
||||
} else if (sbw <= 62.5E3) {
|
||||
_bw = 0x03;
|
||||
} else if (sbw <= 125E3) {
|
||||
_bw = 0x04;
|
||||
} else if (sbw <= 250E3) {
|
||||
_bw = 0x05;
|
||||
} else /*if (sbw <= 250E3)*/ {
|
||||
_bw = 0x06;
|
||||
}
|
||||
void sx126x::setSignalBandwidth(long sbw) {
|
||||
if (sbw <= 7.8E3) { _bw = 0x00; }
|
||||
else if (sbw <= 10.4E3) { _bw = 0x08; }
|
||||
else if (sbw <= 15.6E3) { _bw = 0x01; }
|
||||
else if (sbw <= 20.8E3) { _bw = 0x09; }
|
||||
else if (sbw <= 31.25E3) { _bw = 0x02; }
|
||||
else if (sbw <= 41.7E3) { _bw = 0x0A; }
|
||||
else if (sbw <= 62.5E3) { _bw = 0x03; }
|
||||
else if (sbw <= 125E3) { _bw = 0x04; }
|
||||
else if (sbw <= 250E3) { _bw = 0x05; }
|
||||
else { _bw = 0x06; }
|
||||
|
||||
handleLowDataRate();
|
||||
setModulationParams(_sf, _bw, _cr, _ldro);
|
||||
|
||||
optimizeModemSensitivity();
|
||||
}
|
||||
|
||||
void sx126x::setCodingRate4(int denominator)
|
||||
{
|
||||
if (denominator < 5) {
|
||||
denominator = 5;
|
||||
} else if (denominator > 8) {
|
||||
denominator = 8;
|
||||
}
|
||||
|
||||
void sx126x::setCodingRate4(int denominator) {
|
||||
if (denominator < 5) { denominator = 5; }
|
||||
else if (denominator > 8) { denominator = 8; }
|
||||
int cr = denominator - 4;
|
||||
|
||||
_cr = cr;
|
||||
|
||||
setModulationParams(_sf, _bw, cr, _ldro);
|
||||
}
|
||||
|
||||
void sx126x::setPreambleLength(long length)
|
||||
{
|
||||
void sx126x::setPreambleLength(long length) {
|
||||
_preambleLength = length;
|
||||
setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode);
|
||||
}
|
||||
|
||||
void sx126x::setSyncWord(uint16_t sw)
|
||||
{
|
||||
// TODO: Fix
|
||||
void sx126x::setSyncWord(uint16_t sw) {
|
||||
// TODO: Why was this hardcoded instead of using the config value?
|
||||
// writeRegister(REG_SYNC_WORD_MSB_6X, (sw & 0xFF00) >> 8);
|
||||
// writeRegister(REG_SYNC_WORD_LSB_6X, sw & 0x00FF);
|
||||
writeRegister(REG_SYNC_WORD_MSB_6X, 0x14);
|
||||
writeRegister(REG_SYNC_WORD_LSB_6X, 0x24);
|
||||
}
|
||||
|
||||
void sx126x::enableCrc()
|
||||
{
|
||||
_crcMode = 1;
|
||||
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
||||
}
|
||||
|
||||
void sx126x::disableCrc()
|
||||
{
|
||||
_crcMode = 0;
|
||||
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
||||
}
|
||||
|
||||
byte sx126x::random()
|
||||
{
|
||||
return readRegister(REG_RANDOM_GEN_6X);
|
||||
}
|
||||
|
||||
void sx126x::setPins(int ss, int reset, int dio0, int busy, int rxen)
|
||||
{
|
||||
void sx126x::setPins(int ss, int reset, int dio0, int busy, int rxen) {
|
||||
_ss = ss;
|
||||
_reset = reset;
|
||||
_dio0 = dio0;
|
||||
@ -941,13 +696,7 @@ void sx126x::setPins(int ss, int reset, int dio0, int busy, int rxen)
|
||||
_rxen = rxen;
|
||||
}
|
||||
|
||||
void sx126x::setSPIFrequency(uint32_t frequency)
|
||||
{
|
||||
_spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0);
|
||||
}
|
||||
|
||||
void sx126x::dumpRegisters(Stream& out)
|
||||
{
|
||||
void sx126x::dumpRegisters(Stream& out) {
|
||||
for (int i = 0; i < 128; i++) {
|
||||
out.print("0x");
|
||||
out.print(i, HEX);
|
||||
@ -956,49 +705,29 @@ void sx126x::dumpRegisters(Stream& out)
|
||||
}
|
||||
}
|
||||
|
||||
void sx126x::explicitHeaderMode()
|
||||
{
|
||||
_implicitHeaderMode = 0;
|
||||
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
||||
}
|
||||
|
||||
void sx126x::implicitHeaderMode()
|
||||
{
|
||||
_implicitHeaderMode = 1;
|
||||
setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
|
||||
}
|
||||
|
||||
|
||||
void ISR_VECT sx126x::handleDio0Rise()
|
||||
{
|
||||
void ISR_VECT sx126x::handleDio0Rise() {
|
||||
uint8_t buf[2];
|
||||
|
||||
buf[0] = 0x00;
|
||||
buf[1] = 0x00;
|
||||
|
||||
executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
|
||||
|
||||
executeOpcode(OP_CLEAR_IRQ_STATUS_6X, buf, 2);
|
||||
|
||||
if ((buf[1] & IRQ_PAYLOAD_CRC_ERROR_MASK_6X) == 0) {
|
||||
// received a packet
|
||||
_packetIndex = 0;
|
||||
|
||||
// read packet length
|
||||
uint8_t rxbuf[2] = {0};
|
||||
uint8_t rxbuf[2] = {0}; // Read packet length
|
||||
executeOpcodeRead(OP_RX_BUFFER_STATUS_6X, rxbuf, 2);
|
||||
int packetLength = rxbuf[0];
|
||||
|
||||
if (_onReceive) {
|
||||
_onReceive(packetLength);
|
||||
}
|
||||
if (_onReceive) { _onReceive(packetLength); }
|
||||
}
|
||||
}
|
||||
|
||||
void ISR_VECT sx126x::onDio0Rise()
|
||||
{
|
||||
sx126x_modem.handleDio0Rise();
|
||||
}
|
||||
void ISR_VECT sx126x::onDio0Rise() { sx126x_modem.handleDio0Rise(); }
|
||||
void sx126x::setSPIFrequency(uint32_t frequency) { _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); }
|
||||
void sx126x::enableCrc() { _crcMode = 1; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
void sx126x::disableCrc() { _crcMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
void sx126x::explicitHeaderMode() { _implicitHeaderMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
void sx126x::implicitHeaderMode() { _implicitHeaderMode = 1; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
byte sx126x::random() { return readRegister(REG_RANDOM_GEN_6X); }
|
||||
|
||||
sx126x sx126x_modem;
|
||||
|
||||
|
||||
5
sx126x.h
5
sx126x.h
@ -1,9 +1,6 @@
|
||||
// Copyright (c) Sandeep Mistry. All rights reserved.
|
||||
// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
|
||||
// Licensed under the MIT license.
|
||||
|
||||
// Modifications and additions copyright 2024 by Mark Qvist
|
||||
// Obviously still under the MIT license.
|
||||
|
||||
#ifndef SX126X_H
|
||||
#define SX126X_H
|
||||
|
||||
|
||||
58
sx127x.cpp
58
sx127x.cpp
@ -1,9 +1,6 @@
|
||||
// Copyright (c) Sandeep Mistry. All rights reserved.
|
||||
// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
|
||||
// Licensed under the MIT license.
|
||||
|
||||
// Modifications and additions copyright 2024 by Mark Qvist
|
||||
// Obviously still under the MIT license.
|
||||
|
||||
#include "Boards.h"
|
||||
|
||||
#if MODEM == SX1276
|
||||
@ -81,10 +78,7 @@ extern SPIClass SPI;
|
||||
sx127x::sx127x() :
|
||||
_spiSettings(8E6, MSBFIRST, SPI_MODE0),
|
||||
_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN),
|
||||
_frequency(0),
|
||||
_packetIndex(0),
|
||||
_preinit_done(false),
|
||||
_onReceive(NULL) { setTimeout(0); }
|
||||
_frequency(0), _packetIndex(0), _preinit_done(false), _onReceive(NULL) { setTimeout(0); }
|
||||
|
||||
void sx127x::setSPIFrequency(uint32_t frequency) { _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); }
|
||||
void sx127x::setPins(int ss, int reset, int dio0, int busy) { _ss = ss; _reset = reset; _dio0 = dio0; _busy = busy; }
|
||||
@ -123,7 +117,6 @@ bool sx127x::preInit() {
|
||||
}
|
||||
|
||||
if (version != 0x12) { return false; }
|
||||
|
||||
_preinit_done = true;
|
||||
return true;
|
||||
}
|
||||
@ -144,8 +137,6 @@ uint8_t ISR_VECT sx127x::singleTransfer(uint8_t address, uint8_t value) {
|
||||
int sx127x::begin(long frequency) {
|
||||
if (_reset != -1) {
|
||||
pinMode(_reset, OUTPUT);
|
||||
|
||||
// Perform reset
|
||||
digitalWrite(_reset, LOW);
|
||||
delay(10);
|
||||
digitalWrite(_reset, HIGH);
|
||||
@ -153,19 +144,16 @@ int sx127x::begin(long frequency) {
|
||||
}
|
||||
|
||||
if (_busy != -1) { pinMode(_busy, INPUT); }
|
||||
|
||||
if (!_preinit_done) {
|
||||
if (!preInit()) { return false; }
|
||||
}
|
||||
if (!_preinit_done) { if (!preInit()) { return false; } }
|
||||
|
||||
sleep();
|
||||
setFrequency(frequency);
|
||||
|
||||
// set base addresses
|
||||
// Set base addresses
|
||||
writeRegister(REG_FIFO_TX_BASE_ADDR_7X, 0);
|
||||
writeRegister(REG_FIFO_RX_BASE_ADDR_7X, 0);
|
||||
|
||||
// set LNA boost and auto AGC
|
||||
// Set LNA boost and auto AGC
|
||||
writeRegister(REG_LNA_7X, readRegister(REG_LNA_7X) | 0x03);
|
||||
writeRegister(REG_MODEM_CONFIG_3_7X, 0x04);
|
||||
|
||||
@ -178,20 +166,13 @@ int sx127x::begin(long frequency) {
|
||||
return 1;
|
||||
}
|
||||
|
||||
void sx127x::end() {
|
||||
sleep();
|
||||
SPI.end();
|
||||
_preinit_done = false;
|
||||
}
|
||||
void sx127x::end() { sleep(); SPI.end(); _preinit_done = false; }
|
||||
|
||||
int sx127x::beginPacket(int implicitHeader) {
|
||||
standby();
|
||||
|
||||
if (implicitHeader) {
|
||||
implicitHeaderMode();
|
||||
} else {
|
||||
explicitHeaderMode();
|
||||
}
|
||||
if (implicitHeader) { implicitHeaderMode(); }
|
||||
else { explicitHeaderMode(); }
|
||||
|
||||
// Reset FIFO address and payload length
|
||||
writeRegister(REG_FIFO_ADDR_PTR_7X, 0);
|
||||
@ -253,9 +234,8 @@ int ISR_VECT sx127x::packetRssi() {
|
||||
|
||||
if (_frequency < 820E6) pkt_rssi -= 7;
|
||||
|
||||
if (pkt_snr < 0) {
|
||||
pkt_rssi += pkt_snr;
|
||||
} else {
|
||||
if (pkt_snr < 0) { pkt_rssi += pkt_snr; }
|
||||
else {
|
||||
// Slope correction is (16/15)*pkt_rssi,
|
||||
// this estimation looses one floating point
|
||||
// operation, and should be precise enough.
|
||||
@ -264,13 +244,9 @@ int ISR_VECT sx127x::packetRssi() {
|
||||
return pkt_rssi;
|
||||
}
|
||||
|
||||
uint8_t ISR_VECT sx127x::packetSnrRaw() {
|
||||
return readRegister(REG_PKT_SNR_VALUE_7X);
|
||||
}
|
||||
uint8_t ISR_VECT sx127x::packetSnrRaw() { return readRegister(REG_PKT_SNR_VALUE_7X); }
|
||||
|
||||
float ISR_VECT sx127x::packetSnr() {
|
||||
return ((int8_t)readRegister(REG_PKT_SNR_VALUE_7X)) * 0.25;
|
||||
}
|
||||
float ISR_VECT sx127x::packetSnr() { return ((int8_t)readRegister(REG_PKT_SNR_VALUE_7X)) * 0.25; }
|
||||
|
||||
long sx127x::packetFrequencyError() {
|
||||
int32_t freqError = 0;
|
||||
@ -294,15 +270,11 @@ size_t sx127x::write(uint8_t byte) { return write(&byte, sizeof(byte)); }
|
||||
|
||||
size_t sx127x::write(const uint8_t *buffer, size_t size) {
|
||||
int currentLength = readRegister(REG_PAYLOAD_LENGTH_7X);
|
||||
if ((currentLength + size) > MAX_PKT_LENGTH) {
|
||||
size = MAX_PKT_LENGTH - currentLength;
|
||||
}
|
||||
|
||||
for (size_t i = 0; i < size; i++) {
|
||||
writeRegister(REG_FIFO_7X, buffer[i]);
|
||||
}
|
||||
if ((currentLength + size) > MAX_PKT_LENGTH) { size = MAX_PKT_LENGTH - currentLength; }
|
||||
|
||||
for (size_t i = 0; i < size; i++) { writeRegister(REG_FIFO_7X, buffer[i]); }
|
||||
writeRegister(REG_PAYLOAD_LENGTH_7X, currentLength + size);
|
||||
|
||||
return size;
|
||||
}
|
||||
|
||||
|
||||
5
sx127x.h
5
sx127x.h
@ -1,9 +1,6 @@
|
||||
// Copyright (c) Sandeep Mistry. All rights reserved.
|
||||
// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
|
||||
// Licensed under the MIT license.
|
||||
|
||||
// Modifications and additions copyright 2024 by Mark Qvist
|
||||
// Obviously still under the MIT license.
|
||||
|
||||
#ifndef SX1276_H
|
||||
#define SX1276_H
|
||||
|
||||
|
||||
97
sx128x.cpp
97
sx128x.cpp
@ -1,12 +1,11 @@
|
||||
// Copyright (c) Sandeep Mistry. All rights reserved.
|
||||
// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
|
||||
// Licensed under the MIT license.
|
||||
|
||||
// Modifications and additions copyright 2024 by Mark Qvist & Jacob Eva
|
||||
// Obviously still under the MIT license.
|
||||
|
||||
#include "sx128x.h"
|
||||
#include "Boards.h"
|
||||
|
||||
#if MODEM == SX1280
|
||||
#include "sx128x.h"
|
||||
|
||||
#define MCU_1284P 0x91
|
||||
#define MCU_2560 0x92
|
||||
#define MCU_ESP32 0x81
|
||||
@ -44,19 +43,19 @@
|
||||
#define OP_STANDBY_8X 0x80
|
||||
#define OP_TX_8X 0x83
|
||||
#define OP_RX_8X 0x82
|
||||
#define OP_SET_IRQ_FLAGS_8X 0x8D // also provides info such as
|
||||
#define OP_SET_IRQ_FLAGS_8X 0x8D // Also provides info such as
|
||||
// preamble detection, etc for
|
||||
// knowing when it's safe to switch
|
||||
// antenna modes
|
||||
#define OP_CLEAR_IRQ_STATUS_8X 0x97
|
||||
#define OP_GET_IRQ_STATUS_8X 0x15
|
||||
#define OP_RX_BUFFER_STATUS_8X 0x17
|
||||
#define OP_PACKET_STATUS_8X 0x1D // get snr & rssi of last packet
|
||||
#define OP_PACKET_STATUS_8X 0x1D // Get snr & rssi of last packet
|
||||
#define OP_CURRENT_RSSI_8X 0x1F
|
||||
#define OP_MODULATION_PARAMS_8X 0x8B // bw, sf, cr, etc.
|
||||
#define OP_PACKET_PARAMS_8X 0x8C // crc, preamble, payload length, etc.
|
||||
#define OP_MODULATION_PARAMS_8X 0x8B // BW, SF, CR, etc.
|
||||
#define OP_PACKET_PARAMS_8X 0x8C // CRC, preamble, payload length, etc.
|
||||
#define OP_STATUS_8X 0xC0
|
||||
#define OP_TX_PARAMS_8X 0x8E // set dbm, etc
|
||||
#define OP_TX_PARAMS_8X 0x8E // Set dbm, etc
|
||||
#define OP_PACKET_TYPE_8X 0x8A
|
||||
#define OP_BUFFER_BASE_ADDR_8X 0x8F
|
||||
#define OP_READ_REGISTER_8X 0x19
|
||||
@ -93,24 +92,8 @@ extern SPIClass SPI;
|
||||
sx128x::sx128x() :
|
||||
_spiSettings(8E6, MSBFIRST, SPI_MODE0),
|
||||
_ss(LORA_DEFAULT_SS_PIN), _reset(LORA_DEFAULT_RESET_PIN), _dio0(LORA_DEFAULT_DIO0_PIN), _rxen(pin_rxen), _busy(LORA_DEFAULT_BUSY_PIN), _txen(pin_txen),
|
||||
_frequency(0),
|
||||
_txp(0),
|
||||
_sf(0x05),
|
||||
_bw(0x34),
|
||||
_cr(0x01),
|
||||
_packetIndex(0),
|
||||
_implicitHeaderMode(0),
|
||||
_payloadLength(255),
|
||||
_crcMode(0),
|
||||
_fifo_tx_addr_ptr(0),
|
||||
_fifo_rx_addr_ptr(0),
|
||||
_rxPacketLength(0),
|
||||
_preinit_done(false),
|
||||
_tcxo(false)
|
||||
{
|
||||
// overide Stream timeout value
|
||||
setTimeout(0);
|
||||
}
|
||||
_frequency(0), _txp(0), _sf(0x05), _bw(0x34), _cr(0x01), _packetIndex(0), _implicitHeaderMode(0), _payloadLength(255), _crcMode(0), _fifo_tx_addr_ptr(0),
|
||||
_fifo_rx_addr_ptr(0), _rxPacketLength(0), _preinit_done(false), _tcxo(false) { setTimeout(0); }
|
||||
|
||||
bool ISR_VECT sx128x::getPacketValidity() {
|
||||
uint8_t buf[2];
|
||||
@ -472,23 +455,17 @@ float ISR_VECT sx128x::packetSnr() {
|
||||
}
|
||||
|
||||
long sx128x::packetFrequencyError() {
|
||||
// TODO: implement this, page 120 of sx1280 datasheet
|
||||
// TODO: Implement this, page 120 of sx1280 datasheet
|
||||
int32_t freqError = 0;
|
||||
const float fError = 0.0;
|
||||
return static_cast<long>(fError);
|
||||
}
|
||||
|
||||
void sx128x::flush() { }
|
||||
|
||||
int ISR_VECT sx128x::available() { return _rxPacketLength - _packetIndex; }
|
||||
|
||||
size_t sx128x::write(uint8_t byte) { return write(&byte, sizeof(byte)); }
|
||||
|
||||
size_t sx128x::write(const uint8_t *buffer, size_t size) {
|
||||
if ((_payloadLength + size) > MAX_PKT_LENGTH) {
|
||||
size = MAX_PKT_LENGTH - _payloadLength;
|
||||
}
|
||||
|
||||
if ((_payloadLength + size) > MAX_PKT_LENGTH) { size = MAX_PKT_LENGTH - _payloadLength; }
|
||||
writeBuffer(buffer, size);
|
||||
_payloadLength = _payloadLength + size;
|
||||
return size;
|
||||
@ -716,7 +693,7 @@ void sx128x::setTxPower(int level, int outputPin) {
|
||||
}
|
||||
|
||||
tx_buf[0] = reg_value + 18;
|
||||
tx_buf[1] = 0xE0; // ramping time - 20 microseconds
|
||||
tx_buf[1] = 0xE0; // Ramping time, 20 microseconds
|
||||
executeOpcode(OP_TX_PARAMS_8X, tx_buf, 2);
|
||||
|
||||
// T3S3 SX1280 PA
|
||||
@ -795,7 +772,7 @@ void sx128x::setTxPower(int level, int outputPin) {
|
||||
break;
|
||||
}
|
||||
tx_buf[0] = reg_value;
|
||||
tx_buf[1] = 0xE0; // ramping time - 20 microseconds
|
||||
tx_buf[1] = 0xE0; // Ramping time, 20 microseconds
|
||||
|
||||
// For SX1280 boards with no specific PA requirements
|
||||
#else
|
||||
@ -803,7 +780,7 @@ void sx128x::setTxPower(int level, int outputPin) {
|
||||
else if (level < -18) { level = -18; }
|
||||
_txp = level;
|
||||
tx_buf[0] = level + 18;
|
||||
tx_buf[1] = 0xE0; // ramping time - 20 microseconds
|
||||
tx_buf[1] = 0xE0; // Ramping time, 20 microseconds
|
||||
#endif
|
||||
|
||||
executeOpcode(OP_TX_PARAMS_8X, tx_buf, 2);
|
||||
@ -821,7 +798,7 @@ void sx128x::setFrequency(uint32_t frequency) {
|
||||
}
|
||||
|
||||
uint32_t sx128x::getFrequency() {
|
||||
// we can't read the frequency on the sx1280
|
||||
// We can't read the frequency on the sx1280
|
||||
uint32_t frequency = _frequency;
|
||||
return frequency;
|
||||
}
|
||||
@ -847,12 +824,6 @@ uint32_t sx128x::getSignalBandwidth() {
|
||||
return 0;
|
||||
}
|
||||
|
||||
// TODO: Is this needed for SX1280?
|
||||
void sx128x::handleLowDataRate() { }
|
||||
|
||||
// TODO: Check if there's anything the sx1280 can do here
|
||||
void sx128x::optimizeModemSensitivity() { }
|
||||
|
||||
void sx128x::setSignalBandwidth(uint32_t sbw) {
|
||||
if (sbw <= 203.125E3) { _bw = 0x34; }
|
||||
else if (sbw <= 406.25E3) { _bw = 0x26; }
|
||||
@ -872,40 +843,22 @@ void sx128x::setCodingRate4(int denominator) {
|
||||
setModulationParams(_sf, _bw, _cr);
|
||||
}
|
||||
|
||||
void sx128x::handleLowDataRate() { } // TODO: Is this needed for SX1280?
|
||||
void sx128x::optimizeModemSensitivity() { } // TODO: Check if there's anything the sx1280 can do here
|
||||
uint8_t sx128x::getCodingRate4() { return _cr + 4; }
|
||||
|
||||
void sx128x::setPreambleLength(long length) {
|
||||
_preambleLength = length;
|
||||
setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode);
|
||||
}
|
||||
|
||||
// TODO: Implement
|
||||
void sx128x::setSyncWord(int sw) { }
|
||||
|
||||
// TODO: need to check how to implement on sx1280
|
||||
void sx128x::enableTCXO() { }
|
||||
|
||||
// TODO: need to check how to implement on sx1280
|
||||
void sx128x::disableTCXO() { }
|
||||
|
||||
void sx128x::setPreambleLength(long length) { _preambleLength = length; setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
void sx128x::setSyncWord(int sw) { } // TODO: Implement
|
||||
void sx128x::enableTCXO() { } // TODO: Need to check how to implement on sx1280
|
||||
void sx128x::disableTCXO() { } // TODO: Need to check how to implement on sx1280
|
||||
void sx128x::sleep() { uint8_t byte = 0x00; executeOpcode(OP_SLEEP_8X, &byte, 1); }
|
||||
|
||||
uint8_t sx128x::getTxPower() { return _txp; }
|
||||
|
||||
uint8_t sx128x::getSpreadingFactor() { return _sf; }
|
||||
|
||||
void sx128x::enableCrc() { _crcMode = 0x20; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
|
||||
void sx128x::disableCrc() { _crcMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
|
||||
void sx128x::setSPIFrequency(uint32_t frequency) { _spiSettings = SPISettings(frequency, MSBFIRST, SPI_MODE0); }
|
||||
|
||||
void sx128x::explicitHeaderMode() { _implicitHeaderMode = 0; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
|
||||
void sx128x::implicitHeaderMode() { _implicitHeaderMode = 0x80; setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode); }
|
||||
|
||||
void sx128x::dumpRegisters(Stream& out) {
|
||||
for (int i = 0; i < 128; i++) { out.print("0x"); out.print(i, HEX); out.print(": 0x"); out.println(readRegister(i), HEX); }
|
||||
}
|
||||
void sx128x::dumpRegisters(Stream& out) { for (int i = 0; i < 128; i++) { out.print("0x"); out.print(i, HEX); out.print(": 0x"); out.println(readRegister(i), HEX); } }
|
||||
|
||||
sx128x sx128x_modem;
|
||||
#endif
|
||||
7
sx128x.h
7
sx128x.h
@ -1,9 +1,6 @@
|
||||
// Copyright (c) Sandeep Mistry. All rights reserved.
|
||||
// Copyright Sandeep Mistry, Mark Qvist and Jacob Eva.
|
||||
// Licensed under the MIT license.
|
||||
|
||||
// Modifications and additions copyright 2024 by Mark Qvist
|
||||
// Obviously still under the MIT license.
|
||||
|
||||
#ifndef SX128X_H
|
||||
#define SX128X_H
|
||||
|
||||
@ -18,10 +15,8 @@
|
||||
#define LORA_DEFAULT_TXEN_PIN -1
|
||||
#define LORA_DEFAULT_BUSY_PIN -1
|
||||
#define LORA_MODEM_TIMEOUT_MS 15E3
|
||||
|
||||
#define PA_OUTPUT_RFO_PIN 0
|
||||
#define PA_OUTPUT_PA_BOOST_PIN 1
|
||||
|
||||
#define RSSI_OFFSET 157
|
||||
|
||||
class sx128x : public Stream {
|
||||
|
||||
Loading…
Reference in New Issue
Block a user