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https://github.com/markqvist/RNode_Firmware.git
synced 2025-12-10 06:05:48 -05:00
Reworked board defines, fixed RSSI and waterfall bugs for SX1262.
This commit is contained in:
Mark Qvist
parent
cac58b318a
commit
6f62a5394b
8 changed files with 465 additions and 453 deletions
158
sx126x.cpp
158
sx126x.cpp
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@ -4,9 +4,11 @@
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// Modifications and additions copyright 2023 by Mark Qvist
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// Obviously still under the MIT license.
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#include "sx126x.h"
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#include "Boards.h"
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#if MODEM == SX1262
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#include "sx126x.h"
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#define MCU_1284P 0x91
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#define MCU_2560 0x92
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#define MCU_ESP32 0x81
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@ -67,6 +69,7 @@
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#define IRQ_TX_DONE_MASK_6X 0x01
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#define IRQ_RX_DONE_MASK_6X 0x02
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#define IRQ_HEADER_DET_MASK_6X 0x10
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#define IRQ_PREAMBLE_DET_MASK_6X 0x04
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#define IRQ_PAYLOAD_CRC_ERROR_MASK_6X 0x40
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#define MODE_LONG_RANGE_MODE_6X 0x01
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@ -81,8 +84,16 @@
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#define REG_RANDOM_GEN_6X 0x0819
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#define MODE_TCXO_3_3V_6X 0x07
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#define MODE_TCXO_3_0V_6X 0x06
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#define MODE_TCXO_2_7V_6X 0x06
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#define MODE_TCXO_2_4V_6X 0x06
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#define MODE_TCXO_2_2V_6X 0x03
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#define MODE_TCXO_1_8V_6X 0x02
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#define MODE_TCXO_1_7V_6X 0x01
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#define MODE_TCXO_1_6V_6X 0x00
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#define SYNC_WORD_6X 0x1424
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#define IRQ_PREAMBLE_DET_MASK_6X 0x04
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#define XTAL_FREQ_6X (double)32000000
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#define FREQ_DIV_6X (double)pow(2.0, 25.0)
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#define FREQ_STEP_6X (double)(XTAL_FREQ_6X / FREQ_DIV_6X)
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@ -126,34 +137,28 @@ bool sx126x::preInit() {
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// set SS high
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digitalWrite(_ss, HIGH);
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Serial.println("SPI INIT");
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#if BOARD_MODEL == BOARD_RNODE_NG_22
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SPI.begin(pin_sclk, pin_miso, pin_mosi, pin_cs);
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#else
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SPI.begin();
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#endif
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Serial.println("DONE");
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// check version (retry for up to 2 seconds)
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long start = millis();
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uint8_t syncmsb;
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uint8_t synclsb;
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Serial.println("TRYING REGISTER READ");
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while (((millis() - start) < 2000) && (millis() >= start)) {
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syncmsb = readRegister(REG_SYNC_WORD_MSB_6X);
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synclsb = readRegister(REG_SYNC_WORD_LSB_6X);
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if ( uint16_t(syncmsb << 8 | synclsb) == 0x1424 || uint16_t(syncmsb << 8 | synclsb) == 0x4434) {
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Serial.println("CORRECT VALUE RETURNED");
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break;
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}
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delay(100);
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}
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if ( uint16_t(syncmsb << 8 | synclsb) != 0x1424 && uint16_t(syncmsb << 8 | synclsb) != 0x4434) {
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Serial.println("REG READ FAILED");
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return false;
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}
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Serial.println("MODEM PREINIT SUCCESS");
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_preinit_done = true;
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return true;
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}
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@ -193,10 +198,9 @@ uint8_t ISR_VECT sx126x::singleTransfer(uint8_t opcode, uint16_t address, uint8_
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void sx126x::rxAntEnable()
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{
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uint8_t byte = 0x01;
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// enable dio2 rf switch
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executeOpcode(OP_DIO2_RF_CTRL_6X, &byte, 1);
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digitalWrite(_rxen, HIGH);
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if (_rxen != -1) {
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digitalWrite(_rxen, HIGH);
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}
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}
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void sx126x::loraMode() {
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@ -361,35 +365,48 @@ int sx126x::begin(long frequency)
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}
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}
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//#if HAS_TCXO
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// turn TCXO on
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enableTCXO();
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//#endif
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loraMode();
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idle();
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// cannot access registers in sleep mode on sx1262, set to idle instead
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if (_rxen != -1) {
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pinMode(_rxen, OUTPUT);
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rxAntEnable();
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}
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// calibrate RC64k, RC13M, PLL, ADC and image
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uint8_t calibrate = 0x7F;
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executeOpcode(OP_CALIBRATE_6X, &calibrate, 1);
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loraMode();
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// cannot access registers in sleep mode on sx1262, set to idle instead
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idle();
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setFrequency(frequency);
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#if HAS_TCXO
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enableTCXO();
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#endif
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// set output power to 2 dBm
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setTxPower(2);
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if (_rxen != -1) {
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pinMode(_rxen, OUTPUT);
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}
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// set LNA boost
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writeRegister(REG_LNA_6X, 0x96);
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#if DIO2_AS_RF_SWITCH
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// enable dio2 rf switch
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uint8_t byte = 0x01;
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executeOpcode(OP_DIO2_RF_CTRL_6X, &byte, 1);
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#endif
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// set base addresses
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uint8_t basebuf[2] = {0};
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executeOpcode(OP_BUFFER_BASE_ADDR_6X, basebuf, 2);
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rxAntEnable();
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setModulationParams(_sf, _bw, _cr, _ldro);
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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// Set sync word
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setSyncWord(SYNC_WORD_6X);
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// calibrate RC64k, RC13M, PLL, ADC and image
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uint8_t calibrate = 0x7F;
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executeOpcode(OP_CALIBRATE_6X, &calibrate, 1);
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setFrequency(frequency);
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// set output power to 2 dBm
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setTxPower(2);
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enableCrc();
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// set LNA boost
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writeRegister(REG_LNA_6X, 0x96);
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// set base addresses
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uint8_t basebuf[2] = {0};
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executeOpcode(OP_BUFFER_BASE_ADDR_6X, basebuf, 2);
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setModulationParams(_sf, _bw, _cr, _ldro);
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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return 1;
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}
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@ -416,9 +433,9 @@ int sx126x::beginPacket(int implicitHeader)
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explicitHeaderMode();
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}
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_payloadLength = 0;
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_fifo_tx_addr_ptr = 0;
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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_payloadLength = 0;
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_fifo_tx_addr_ptr = 0;
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setPacketParams(_preambleLength, _implicitHeaderMode, _payloadLength, _crcMode);
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return 1;
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}
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@ -459,23 +476,18 @@ uint8_t sx126x::modemStatus() {
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// imitate the register status from the sx1276 / 78
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uint8_t buf[2] = {0};
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executeOpcodeRead(OP_GET_IRQ_STATUS_6X, buf, 2);
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uint8_t clearbuf[2] = {0};
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uint8_t byte = 0x00;
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if (buf[1] & IRQ_PREAMBLE_DET_MASK_6X != 0) {
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byte = byte | 0x01 | 0x04;
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// clear register after reading
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clearbuf[1] = IRQ_PREAMBLE_DET_MASK_6X;
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if ((buf[1] & IRQ_PREAMBLE_DET_MASK_6X) != 0) {
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byte = byte | 0x01 | 0x04;
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// clear register after reading
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clearbuf[1] = IRQ_PREAMBLE_DET_MASK_6X;
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}
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if (buf[1] & IRQ_HEADER_DET_MASK_6X != 0) {
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byte = byte | 0x02 | 0x04;
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// clear register after reading
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clearbuf[1] = clearbuf[1] | IRQ_HEADER_DET_MASK_6X;
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if ((buf[1] & IRQ_HEADER_DET_MASK_6X) != 0) {
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byte = byte | 0x02 | 0x04;
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}
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executeOpcode(OP_CLEAR_IRQ_STATUS_6X, clearbuf, 2);
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@ -494,7 +506,7 @@ int ISR_VECT sx126x::currentRssi() {
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uint8_t byte = 0;
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executeOpcodeRead(OP_CURRENT_RSSI_6X, &byte, 1);
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int rssi = -(int(byte)) / 2;
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return rssi - RSSI_OFFSET;
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return rssi;
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}
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uint8_t sx126x::packetRssiRaw() {
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@ -508,7 +520,7 @@ int ISR_VECT sx126x::packetRssi() {
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uint8_t buf[3] = {0};
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executeOpcodeRead(OP_PACKET_STATUS_6X, buf, 3);
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int pkt_rssi = -buf[0] / 2;
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return pkt_rssi - RSSI_OFFSET;
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return pkt_rssi;
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}
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uint8_t ISR_VECT sx126x::packetSnrRaw() {
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@ -653,20 +665,18 @@ void sx126x::receive(int size)
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if (_rxen != -1) {
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rxAntEnable();
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}
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uint8_t mode[3] = {0xFF, 0xFF, 0xFF}; // continuous mode
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executeOpcode(OP_RX_6X, mode, 3);
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}
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void sx126x::idle()
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{
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//#if HAS_TCXO
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// STDBY_XOSC
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uint8_t byte = 0x01;
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//#else
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// // STDBY_RC
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// uint8_t byte = 0x00;
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//#endif
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executeOpcode(OP_STANDBY_6X, &byte, 1);
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// STDBY_XOSC
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uint8_t byte = 0x01;
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// STDBY_RC
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// uint8_t byte = 0x00;
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executeOpcode(OP_STANDBY_6X, &byte, 1);
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}
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void sx126x::sleep()
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@ -677,7 +687,12 @@ void sx126x::sleep()
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void sx126x::enableTCXO() {
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// only tested for RAK4630, voltage may be different on other platforms
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uint8_t buf[4] = {MODE_TCXO_3_3V_6X, 0x00, 0x00, 0xFF};
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#if BOARD_MODEL == BOARD_RAK4630
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uint8_t buf[4] = {MODE_TCXO_3_3V_6X, 0x00, 0x00, 0xFF};
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#elif BOARD_MODEL == BOARD_TBEAM
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uint8_t buf[4] = {MODE_TCXO_1_8V_6X, 0x00, 0x00, 0xFF};
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#endif
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executeOpcode(OP_DIO3_TCXO_CTRL_6X, buf, 4);
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}
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@ -756,7 +771,7 @@ void sx126x::setSpreadingFactor(int sf)
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_sf = sf;
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setModulationParams(sf, _bw, _cr, _ldro);
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setModulationParams(sf, _bw, _cr, _ldro);
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handleLowDataRate();
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}
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@ -834,13 +849,17 @@ void sx126x::setCodingRate4(int denominator)
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void sx126x::setPreambleLength(long length)
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{
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setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode);
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_preambleLength = length;
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setPacketParams(length, _implicitHeaderMode, _payloadLength, _crcMode);
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}
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void sx126x::setSyncWord(int sw)
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void sx126x::setSyncWord(uint16_t sw)
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{
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writeRegister(REG_SYNC_WORD_MSB_6X, sw & 0xFF00);
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writeRegister(REG_SYNC_WORD_LSB_6X, sw & 0x00FF);
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// TODO: Fix
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// writeRegister(REG_SYNC_WORD_MSB_6X, (sw & 0xFF00) >> 8);
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// writeRegister(REG_SYNC_WORD_LSB_6X, sw & 0x00FF);
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writeRegister(REG_SYNC_WORD_MSB_6X, 0x14);
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writeRegister(REG_SYNC_WORD_LSB_6X, 0x24);
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}
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void sx126x::enableCrc()
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@ -921,6 +940,11 @@ void ISR_VECT sx126x::handleDio0Rise()
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_onReceive(packetLength);
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}
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}
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// else {
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// Serial.println("CRCE");
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// Serial.println(buf[0]);
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// Serial.println(buf[1]);
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// }
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}
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void ISR_VECT sx126x::onDio0Rise()
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@ -929,3 +953,5 @@ void ISR_VECT sx126x::onDio0Rise()
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}
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sx126x sx126x_modem;
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#endif
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