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https://github.com/markqvist/OpenModem.git
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341 lines
10 KiB
C
341 lines
10 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2010,2011 Develer S.r.l. (http://www.develer.com/)
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*
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* -->
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*
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* \author Stefano Fedrigo <aleph@develer.com>
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*/
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#ifndef SAM3_H
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#define SAM3_H
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#include <cpu/detect.h>
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#include <cfg/compiler.h>
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/*
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* Peripherals IDs.
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*/
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/*\{*/
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#if CPU_CM3_SAM3N
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#define SUPC_ID 0 ///< Supply Controller (SUPC)
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#define RSTC_ID 1 ///< Reset Controller (RSTC)
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#define RTC_ID 2 ///< Real Time Clock (RTC)
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#define RTT_ID 3 ///< Real Time Timer (RTT)
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#define WDT_ID 4 ///< Watchdog Timer (WDT)
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#define PMC_ID 5 ///< Power Management Controller (PMC)
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#define EEFC0_ID 6 ///< Enhanced Flash Controller
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#define UART0_ID 8 ///< UART 0 (UART0)
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#define UART1_ID 9 ///< UART 1 (UART1)
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#define PIOA_ID 11 ///< Parallel I/O Controller A (PIOA)
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#define PIOB_ID 12 ///< Parallel I/O Controller B (PIOB)
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#define PIOC_ID 13 ///< Parallel I/O Controller C (PIOC)
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#define US0_ID 14 ///< USART 0 (USART0)
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#define US1_ID 15 ///< USART 1 (USART1)
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#define TWI0_ID 19 ///< Two Wire Interface 0 (TWI0)
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#define TWI1_ID 20 ///< Two Wire Interface 1 (TWI1)
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#define SPI0_ID 21 ///< Serial Peripheral Interface (SPI)
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#define TC0_ID 23 ///< Timer/Counter 0 (TC0)
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#define TC1_ID 24 ///< Timer/Counter 1 (TC1)
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#define TC2_ID 25 ///< Timer/Counter 2 (TC2)
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#define TC3_ID 26 ///< Timer/Counter 3 (TC3)
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#define TC4_ID 27 ///< Timer/Counter 4 (TC4)
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#define TC5_ID 28 ///< Timer/Counter 5 (TC5)
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#define ADC_ID 29 ///< Analog To Digital Converter (ADC)
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#define DACC_ID 30 ///< Digital To Analog Converter (DACC)
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#define PWM_ID 31 ///< Pulse Width Modulation (PWM)
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#elif CPU_CM3_SAM3X
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#define SUPC_ID 0 ///< Supply Controller (SUPC)
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#define RSTC_ID 1 ///< Reset Controller (RSTC)
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#define RTC_ID 2 ///< Real Time Clock (RTC)
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#define RTT_ID 3 ///< Real Time Timer (RTT)
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#define WDT_ID 4 ///< Watchdog Timer (WDT)
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#define PMC_ID 5 ///< Power Management Controller (PMC)
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#define EEFC0_ID 6 ///< Enhanced Flash Controller
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#define EEFC1_ID 7 ///< Enhanced Flash Controller
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#define UART0_ID 8 ///< UART 0 (UART0)
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#define SMC_SDRAMC_ID 9 ///< Satic memory controller / SDRAM controller
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#define SDRAMC_ID 10 ///< Satic memory controller / SDRAM controller
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#define PIOA_ID 11 ///< Parallel I/O Controller A
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#define PIOB_ID 12 ///< Parallel I/O Controller B
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#define PIOC_ID 13 ///< Parallel I/O Controller C
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#define PIOD_ID 14 ///< Parallel I/O Controller D
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#define PIOE_ID 15 ///< Parallel I/O Controller E
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#define PIOF_ID 16 ///< Parallel I/O Controller F
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#define US0_ID 17 ///< USART 0
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#define US1_ID 18 ///< USART 1
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#define US2_ID 19 ///< USART 2
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#define US3_ID 20 ///< USART 3
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#define HSMCI_ID 21 ///< High speed multimedia card interface
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#define TWI0_ID 22 ///< Two Wire Interface 0
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#define TWI1_ID 23 ///< Two Wire Interface 1
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#define SPI0_ID 24 ///< Serial Peripheral Interface
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#define SPI1_ID 25 ///< Serial Peripheral Interface
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#define SSC_ID 26 ///< Synchronous serial controller
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#define TC0_ID 27 ///< Timer/Counter 0
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#define TC1_ID 28 ///< Timer/Counter 1
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#define TC2_ID 29 ///< Timer/Counter 2
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#define TC3_ID 30 ///< Timer/Counter 3
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#define TC4_ID 31 ///< Timer/Counter 4
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#define TC5_ID 32 ///< Timer/Counter 5
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#define TC6_ID 33 ///< Timer/Counter 6
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#define TC7_ID 34 ///< Timer/Counter 7
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#define TC8_ID 35 ///< Timer/Counter 8
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#define PWM_ID 36 ///< Pulse width modulation controller
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#define ADC_ID 37 ///< ADC controller
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#define DACC_ID 38 ///< DAC controller
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#define DMAC_ID 39 ///< DMA controller
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#define UOTGHS_ID 40 ///< USB OTG high speed
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#define TRNG_ID 41 ///< True random number generator
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#define EMAC_ID 42 ///< Ethernet MAC
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#define CAN0_ID 43 ///< CAN controller 0
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#define CAN1_ID 44 ///< CAN controller 1
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#else
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#error Peripheral IDs undefined
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#endif
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/*\}*/
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/*
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* Hardware features for drivers.
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*/
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#define USART_HAS_PDC 1
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#define SPI_HAS_PDC 1
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#if CPU_CM3_SAM3X || CPU_CM3_SAM3U
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#define USART_PORTS 1
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#define UART_PORTS 4
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#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
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#define USART_PORTS 2
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#define UART_PORTS 2
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#else
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#error undefined U(S)ART_PORTS for this cpu
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#endif
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#include "sam3_sysctl.h"
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#include "sam3_pdc.h"
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#include "sam3_pmc.h"
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#include "sam3_smc.h"
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#include "sam3_sdramc.h"
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#include "sam3_ints.h"
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#include "sam3_pio.h"
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#include "sam3_nvic.h"
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#include "sam3_uart.h"
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#include "sam3_usart.h"
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#include "sam3_spi.h"
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#include "sam3_flash.h"
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#include "sam3_wdt.h"
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#include "sam3_emac.h"
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#include "sam3_rstc.h"
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#include "sam3_adc.h"
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#include "sam3_dacc.h"
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#include "sam3_tc.h"
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#include "sam3_twi.h"
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#include "sam3_ssc.h"
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/**
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* U(S)ART I/O pins
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*/
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/*\{*/
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#if CPU_CM3_SAM3U
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#define UART0_PORT PIOA_BASE
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#define USART0_PORT PIOA_BASE
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#define USART1_PORT PIOA_BASE
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#define USART2_PORT PIOA_BASE
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#define USART3_PORT PIOC_BASE
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#define UART0_PERIPH PIO_PERIPH_A
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#define USART0_PERIPH PIO_PERIPH_A
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#define USART1_PERIPH PIO_PERIPH_A
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#define USART2_PERIPH PIO_PERIPH_A
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#define USART3_PERIPH PIO_PERIPH_B
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#define URXD0 11
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#define UTXD0 12
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#define RXD0 19
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#define TXD0 18
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#define RXD1 21
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#define TXD1 20
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#define RXD2 23
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#define TXD2 22
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#define RXD3 13
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#define TXD3 12
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#elif CPU_CM3_SAM3X
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#define UART0_PORT PIOA_BASE
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#define USART0_PORT PIOA_BASE
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#define USART1_PORT PIOA_BASE
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#define USART2_PORT PIOB_BASE
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#define USART3_PORT PIOD_BASE
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#define UART0_PERIPH PIO_PERIPH_A
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#define USART0_PERIPH PIO_PERIPH_A
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#define USART1_PERIPH PIO_PERIPH_A
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#define USART2_PERIPH PIO_PERIPH_A
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#define USART3_PERIPH PIO_PERIPH_B
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#define URXD0 8
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#define UTXD0 9
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#define RXD0 10
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#define TXD0 11
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#define RXD1 12
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#define TXD1 13
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#define RXD2 21
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#define TXD2 20
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#define RXD3 5
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#define TXD3 4
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#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
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#define UART0_PORT PIOA_BASE
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#define UART1_PORT PIOB_BASE
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#define USART0_PORT PIOA_BASE
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#define USART1_PORT PIOA_BASE
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#define UART0_PERIPH PIO_PERIPH_A
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#define UART1_PERIPH PIO_PERIPH_A
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#define USART0_PERIPH PIO_PERIPH_A
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#define USART1_PERIPH PIO_PERIPH_A
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#define URXD0 9
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#define UTXD0 10
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#define URXD1 2
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#define UTXD1 3
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#define RXD0 5
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#define TXD0 6
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#define RXD1 21
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#define TXD1 22
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#endif
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/*\}*/
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/**
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* SPI I/O pins
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*/
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/*\{*/
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#if CPU_CM3_SAM3U
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#define SPI0_SPCK 15
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#define SPI0_MOSI 14
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#define SPI0_MISO 13
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#elif CPU_CM3_SAM3X
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#define SPI0_SPCK 27
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#define SPI0_MOSI 26
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#define SPI0_MISO 25
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#else
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#define SPI0_SPCK 14
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#define SPI0_MOSI 13
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#define SPI0_MISO 12
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#endif
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/*\}*/
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/**
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* TWI I/O pins
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*/
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/*\{*/
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#if CPU_CM3_SAM3X
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#define TWI0_PORT PIOA_BASE
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#define TWI1_PORT PIOA_BASE
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#define TWI0_PERIPH PIO_PERIPH_A
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#define TWI1_PERIPH PIO_PERIPH_A
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#define TWI0_TWD 17
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#define TWI0_TWCK 18
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#define TWI1_TWD 12
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#define TWI1_TWCK 13
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#elif CPU_CM3_SAM3N || CPU_CM3_SAM3S
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#define TWI0_PORT PIOA_BASE
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#define TWI1_PORT PIOB_BASE
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#define TWI0_PERIPH PIO_PERIPH_A
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#define TWI1_PERIPH PIO_PERIPH_A
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#define TWI0_TWD 3
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#define TWI0_TWCK 4
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#define TWI1_TWD 4
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#define TWI1_TWCK 5
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#elif CPU_CM3_SAM3U
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#define TWI0_PORT PIOA_BASE
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#define TWI1_PORT PIOA_BASE
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#define TWI0_PERIPH PIO_PERIPH_A
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#define TWI1_PERIPH PIO_PERIPH_A
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#define TWI0_TWD 9
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#define TWI0_TWCK 10
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#define TWI1_TWD 24
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#define TWI1_TWCK 25
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#endif
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#if CPU_CM3_SAM3X
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#define SSC_PORT PIOA_BASE
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#define SSC_PIO_PDR PIOA_PDR
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#define SSC_RECV_PERIPH PIO_PERIPH_A
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#define SSC_TRAN_PERIPH PIO_PERIPH_B
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#define SSC_RD 18
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#define SSC_RF 17
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#define SSC_RK 19
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#define SSC_TD 16
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#define SSC_TF 15
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#define SSC_TK 14
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#elif CPU_CM3_SAM3N
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#define SSC_PORT /* None! */
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#define SSC_PIO_PDR /* None! */
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#define SSC_RECV_PERIPH /* None! */
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#define SSC_TRAN_PERIPH /* None! */
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#define SSC_RD /* None! */
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#define SSC_RF /* None! */
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#define SSC_RK /* None! */
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#define SSC_TD /* None! */
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#define SSC_TF /* None! */
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#define SSC_TK /* None! */
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#elif CPU_CM3_SAM3S
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#define SSC_PORT PIOA_BASE
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#define SSC_PIO_PDR PIOA_PDR
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#define SSC_RECV_PERIPH PIO_PERIPH_A
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#define SSC_TRAN_PERIPH PIO_PERIPH_A
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#define SSC_RD 18
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#define SSC_RF 20
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#define SSC_RK 19
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#define SSC_TD 17
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#define SSC_TF 15
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#define SSC_TK 16
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#elif CPU_CM3_SAM3U
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#define SSC_PORT PIOA_BASE
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#define SSC_PIO_PDR PIOA_PDR
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#define SSC_RECV_PERIPH PIO_PERIPH_A
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#define SSC_TRAN_PERIPH PIO_PERIPH_A
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#define SSC_RD 27
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#define SSC_RF 31
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#define SSC_RK 29
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#define SSC_TD 26
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#define SSC_TF 30
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#define SSC_TK 28
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#else
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#error no ssc pins are defined for this cpu
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#endif
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/*\}*/
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#endif /* SAM3_H */
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