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304 lines
8.9 KiB
C
304 lines
8.9 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2004, 2005, 2006, 2007, 2008 Develer S.r.l. (http://www.develer.com/)
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* Copyright 2004 Giovanni Bajo
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* -->
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*
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* \brief CPU-specific attributes.
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*
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* \author Giovanni Bajo <rasky@develer.com>
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* \author Bernie Innocenti <bernie@codewiz.org>
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* \author Stefano Fedrigo <aleph@develer.com>
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* \author Francesco Sacchi <batt@develer.com>
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*/
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#ifndef CPU_ATTR_H
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#define CPU_ATTR_H
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#include "detect.h"
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#include "cfg/cfg_proc.h" /* CONFIG_KERN_PREEMPT */
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#include "cfg/cfg_attr.h" /* CONFIG_FAST_MEM */
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/**
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* \name Macros for determining CPU endianness.
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* \{
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*/
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#define CPU_BIG_ENDIAN 0x1234
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#define CPU_LITTLE_ENDIAN 0x3412 /* Look twice, pal. This is not a bug. */
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/*\}*/
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/** Macro to include cpu-specific versions of the headers. */
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#define CPU_HEADER(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).h)
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/** Macro to include cpu-specific versions of implementation files. */
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#define CPU_CSOURCE(module) PP_STRINGIZE(drv/PP_CAT3(module, _, CPU_ID).c)
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#if CPU_I196
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#define NOP nop_instruction()
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#define CPU_REG_BITS 16
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#define CPU_REGS_CNT 16
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#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
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#define CPU_HARVARD 0
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/// Valid pointers should be >= than this value (used for debug)
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#define CPU_RAM_START 0x100
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#elif CPU_X86
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#define CPU_REGS_CNT 7
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#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
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#define CPU_HARVARD 0
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#if CPU_X86_64
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#define CPU_REG_BITS 64
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#ifdef __WIN64__
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/* WIN64 is an IL32-P64 weirdo. */
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#define SIZEOF_LONG 4
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#endif
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#else
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#define CPU_REG_BITS 32
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#endif
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/// Valid pointers should be >= than this value (used for debug)
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#define CPU_RAM_START 0x1000
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#ifdef __GNUC__
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#define NOP asm volatile ("nop")
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/* This is a good thing to insert into busy-wait loops. */
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#define PAUSE asm volatile ("rep; nop" ::: "memory")
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#define BREAKPOINT asm volatile ("int3" ::)
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#endif
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#elif CPU_ARM
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#define CPU_REG_BITS 32
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#define CPU_REGS_CNT 16
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#define CPU_HARVARD 0
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/// Valid pointers should be >= than this value (used for debug)
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#if CPU_ARM_AT91
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#define CPU_RAM_START 0x00200000
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#elif CPU_ARM_LPC2
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#define CPU_RAM_START 0x40000000
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#else
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#warning Fix CPU_RAM_START address for your ARM, default value set to 0x200
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#define CPU_RAM_START 0x200
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#endif
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#ifdef __IAR_SYSTEMS_ICC__
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#warning Check CPU_BYTE_ORDER
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#define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
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#define NOP __no_operation()
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#else /* GCC and compatibles */
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#if defined(__ARMEB__)
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#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
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#elif defined(__ARMEL__)
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#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
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#else
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#error Unable to detect ARM endianness!
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#endif
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#define NOP asm volatile ("mov r0,r0" ::)
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#define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
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#if CONFIG_FAST_MEM
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/**
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* Function attribute for use with performance critical code.
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*
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* On the AT91 family, code residing in flash has wait states.
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* Moving functions to the data section is a quick & dirty way
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* to get them transparently copied to SRAM for zero-wait-state
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* operation.
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*/
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#define FAST_FUNC __attribute__((section(".ramfunc")))
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/**
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* Data attribute to move constant data to fast memory storage.
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*
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* \see FAST_FUNC
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*/
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#define FAST_RODATA __attribute__((section(".data")))
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#else // !CONFIG_FAST_MEM
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#define FAST_RODATA /**/
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#define FAST_FUNC /**/
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#endif
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/*
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* Function attribute to move it into ram memory.
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*/
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#define RAM_FUNC __attribute__((section(".ramfunc")))
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#endif /* !__IAR_SYSTEMS_ICC_ */
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#elif CPU_CM3
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#define CPU_REG_BITS 32
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#define CPU_REGS_CNT 16
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#define CPU_HARVARD 0
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/// Valid pointers should be >= than this value (used for debug)
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#if (CPU_CM3_LM3S1968 || CPU_CM3_LM3S8962 || CPU_CM3_STM32 || CPU_CM3_SAM3)
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#define CPU_RAM_START 0x20000000
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#else
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#warning Fix CPU_RAM_START address for your Cortex-M3, default value set to 0x20000000
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#define CPU_RAM_START 0x20000000
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#endif
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#if defined( __ICCARM__)
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#if ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 0))
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#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
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#elif ((defined __LITTLE_ENDIAN__) && (__LITTLE_ENDIAN__ == 1))
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#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
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#else
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#error Unable to detect Cortex-M3 endianess!
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#endif
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#define NOP __no_operation()
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#else
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#if defined(__ARMEB__) // GCC
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#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
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#elif defined(__ARMEL__) // GCC
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#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
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#else
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#error Unable to detect Cortex-M3 endianess!
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#endif
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#define NOP asm volatile ("nop")
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#define PAUSE asm volatile ("wfi" ::: "memory")
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#define BREAKPOINT /* asm("bkpt 0") DOES NOT WORK */
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/*
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* Function attribute to move it into ram memory.
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*/
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#define RAM_FUNC __attribute__((section(".ramfunc")))
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#endif
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#elif CPU_PPC
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#define CPU_REG_BITS (CPU_PPC32 ? 32 : 64)
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#define CPU_REGS_CNT FIXME
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#define CPU_BYTE_ORDER (__BIG_ENDIAN__ ? CPU_BIG_ENDIAN : CPU_LITTLE_ENDIAN)
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#define CPU_HARVARD 0
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/// Valid pointers should be >= than this value (used for debug)
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#define CPU_RAM_START 0x1000
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#ifdef __GNUC__
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#define NOP asm volatile ("nop" ::)
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#define BREAKPOINT asm volatile ("twge 2,2" ::)
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#endif
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#elif CPU_DSP56K
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#define CPU_REG_BITS 16
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#define CPU_REGS_CNT FIXME
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#define CPU_BYTE_ORDER CPU_BIG_ENDIAN
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#define CPU_HARVARD 1
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/* Memory is word-addessed in the DSP56K */
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#define CPU_BITS_PER_CHAR 16
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#define SIZEOF_SHORT 1
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#define SIZEOF_INT 1
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#define SIZEOF_LONG 2
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#define SIZEOF_PTR 1
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/// Valid pointers should be >= than this value (used for debug)
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#define CPU_RAM_START 0x200
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#define NOP asm(nop)
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#define BREAKPOINT asm(debug)
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#elif CPU_AVR
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#define NOP asm volatile ("nop" ::)
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#define CPU_REG_BITS 8
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#define CPU_REGS_CNT 33 /* Includes SREG */
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#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
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#define CPU_HARVARD 1
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/// Valid pointers should be >= than this value (used for debug)
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#if CPU_AVR_ATMEGA8 || CPU_AVR_ATMEGA32 || CPU_AVR_ATMEGA103
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#define CPU_RAM_START 0x60
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#elif CPU_AVR_ATMEGA64 || CPU_AVR_ATMEGA128 || CPU_AVR_ATMEGA168 || CPU_AVR_ATMEGA328P
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#define CPU_RAM_START 0x100
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#elif CPU_AVR_ATMEGA1281 || CPU_AVR_ATMEGA1280 || CPU_AVR_ATMEGA2560
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#define CPU_RAM_START 0x200
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#elif CPU_AVR_XMEGA_D
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#define CPU_RAM_START 0x2000
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#else
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#warning Fix CPU_RAM_START address for your AVR, default value set to 0x100
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#define CPU_RAM_START 0x100
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#endif
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#elif CPU_MSP430
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#define CPU_REG_BITS 16
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#define CPU_REGS_CNT 12
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#define CPU_BYTE_ORDER CPU_LITTLE_ENDIAN
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#define CPU_HARVARD 0
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/// Valid pointers should be >= than this value (used for debug)
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#define CPU_RAM_START 0x200
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#define NOP __asm__ __volatile__ ("nop")
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#else
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#error No CPU_... defined.
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#endif
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#ifndef BREAKPOINT
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#define BREAKPOINT /* nop */
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#endif
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#ifndef FAST_FUNC
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/// Function attribute for use with performance critical code.
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#define FAST_FUNC /* */
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#endif
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#ifndef FAST_RODATA
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/// Data attribute to move constant data to fast memory storage.
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#define FAST_RODATA /* */
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#endif
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#ifndef PAUSE
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/// Generic PAUSE implementation.
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#define PAUSE do {NOP; MEMORY_BARRIER;} while (0)
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#endif
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#endif /* CPU_ATTR_H */
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