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418 lines
12 KiB
C
418 lines
12 KiB
C
/**
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* \file
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* <!--
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* This file is part of BeRTOS.
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*
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* Bertos is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*
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* As a special exception, you may use this file as part of a free software
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* library without restriction. Specifically, if other files instantiate
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* templates or use macros or inline functions from this file, or you compile
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* this file and link it with other files to produce an executable, this
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* file does not by itself cause the resulting executable to be covered by
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* the GNU General Public License. This exception does not however
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* invalidate any other reasons why the executable file might be covered by
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* the GNU General Public License.
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*
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* Copyright 2008 Develer S.r.l. (http://www.develer.com/)
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* All Rights Reserved.
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* -->
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*
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* \brief Stepper driver interface implementation.
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*
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* This module use the three timer on the at91 family, to generate a
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* six periodic variable pwm waveform. The pulse width is fix, and could
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* change by setting the STEPPER_DELAY_ON_COMPARE_C define, but you make
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* an attention to do this, becouse the pulse width is not exactly
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* STEPPER_DELAY_ON_COMPARE_C. The pulse width depend also to latency
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* time of cpu to serve an interrupt, this generate an pwm waveform affect
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* to noise. This noise not effect the period but only the pulse width,
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* becouse the raising edge is generate by hardware comply with the our
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* period settings.
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*
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* Note: is most important to set STEPPER_DELAY_ON_COMPARE_C value minor
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* than a interrupt time service, becouse the falling edge must be happen
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* inside to inerrupt service to guarantee a correct functionaly of pwm
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* generator.
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*
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*
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*
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* \author Daniele Basile <asterix@develer.com>
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*/
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#include "stepper_at91.h"
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#include "cfg/cfg_stepper.h"
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#include <cfg/macros.h>
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#include <cfg/debug.h>
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#include <cpu/types.h>
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#include <cpu/irq.h>
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#include <io/arm.h>
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/*
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* Delay to set C compare to clear output
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* on select TIO output
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*/
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#define STEPPER_DELAY_ON_COMPARE_C 20
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/*
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* Forward declaration for interrupt handler
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*/
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static ISR_PROTO(stepper_tc0_irq);
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static ISR_PROTO(stepper_tc1_irq);
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static ISR_PROTO(stepper_tc2_irq);
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///< Static array of timer counter struct for stepper.
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static struct TimerCounter stepper_timers[CONFIG_TC_STEPPER_MAX_NUM] =
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{
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{ //Timer Counter settings for TIOA0 output pin
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.timer_id = TC0_ID,
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.blk_ctrl_set = TC_NONEXC0,
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.chl_mode_reg = &TC0_CMR,
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.chl_ctrl_reg = &TC0_CCR,
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.comp_effect_mask = TC_ACPA_MASK,
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.comp_effect_set = TC_ACPA_SET_OUTPUT,
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.comp_effect_clear = TC_ACPA_CLEAR_OUTPUT,
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.comp_effect_c_mask = TC_ACPC_MASK,
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.comp_effect_c_clear = TC_ACPC_CLEAR_OUTPUT,
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.ext_event_set = TC_EEVT_XC0,
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.comp_reg = &TC0_RA,
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.comp_c_reg = &TC0_RC,
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.count_val_reg = &TC0_CV,
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.irq_enable_reg = &TC0_IER,
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.irq_disable_reg = &TC0_IDR,
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.irq_set_mask = BV(TC_CPAS),
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.irq_mask_reg = &TC0_IMR,
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.isr = stepper_tc0_irq,
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.status_reg = &TC0_SR,
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.tio_pin = TIOA0,
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.callback = NULL,
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.motor = NULL,
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},
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{ //Timer Counter settings for TIOB0 output pin
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.timer_id = TC0_ID,
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.blk_ctrl_set = TC_NONEXC0,
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.chl_mode_reg = &TC0_CMR,
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.chl_ctrl_reg = &TC0_CCR,
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.comp_reg = &TC0_RB,
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.comp_c_reg = &TC0_RC,
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.count_val_reg = &TC0_CV,
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.comp_effect_mask = TC_BCPB_MASK,
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.comp_effect_set = TC_BCPB_SET_OUTPUT,
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.comp_effect_clear = TC_BCPB_CLEAR_OUTPUT,
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.comp_effect_c_mask = TC_BCPC_MASK,
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.comp_effect_c_clear = TC_BCPC_CLEAR_OUTPUT,
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.ext_event_set = TC_EEVT_XC0,
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.irq_enable_reg = &TC0_IER,
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.irq_disable_reg = &TC0_IDR,
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.irq_set_mask = BV(TC_CPBS),
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.irq_mask_reg = &TC0_IMR,
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.isr = stepper_tc0_irq,
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.status_reg = &TC0_SR,
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.tio_pin = TIOB0,
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.callback = NULL,
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.motor = NULL,
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},
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{ //Timer Counter settings for TIOA1 output pin
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.timer_id = TC1_ID,
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.blk_ctrl_set = TC_NONEXC1,
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.chl_mode_reg = &TC1_CMR,
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.chl_ctrl_reg = &TC1_CCR,
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.comp_reg = &TC1_RA,
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.comp_c_reg = &TC1_RC,
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.count_val_reg = &TC1_CV,
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.comp_effect_mask = TC_ACPA_MASK,
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.comp_effect_set = TC_ACPA_SET_OUTPUT,
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.comp_effect_clear = TC_ACPA_CLEAR_OUTPUT,
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.comp_effect_c_mask = TC_ACPC_MASK,
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.comp_effect_c_clear = TC_ACPC_CLEAR_OUTPUT,
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.ext_event_set = TC_EEVT_XC1,
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.irq_enable_reg = &TC1_IER,
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.irq_disable_reg = &TC1_IDR,
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.irq_set_mask = BV(TC_CPAS),
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.irq_mask_reg = &TC1_IMR,
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.isr = stepper_tc1_irq,
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.status_reg = &TC1_SR,
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.tio_pin = TIOA1,
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.callback = NULL,
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.motor = NULL,
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},
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{ //Timer Counter settings for TIOB1 output pin
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.timer_id = TC1_ID,
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.blk_ctrl_set = TC_NONEXC1,
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.chl_mode_reg = &TC1_CMR,
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.chl_ctrl_reg = &TC1_CCR,
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.comp_reg = &TC1_RB,
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.comp_c_reg = &TC1_RC,
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.count_val_reg = &TC1_CV,
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.comp_effect_mask = TC_BCPB_MASK,
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.comp_effect_set = TC_BCPB_SET_OUTPUT,
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.comp_effect_clear = TC_BCPB_CLEAR_OUTPUT,
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.comp_effect_c_mask = TC_BCPC_MASK,
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.comp_effect_c_clear = TC_BCPC_CLEAR_OUTPUT,
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.ext_event_set = TC_EEVT_XC1,
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.irq_enable_reg = &TC1_IER,
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.irq_disable_reg = &TC1_IDR,
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.irq_set_mask = BV(TC_CPBS),
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.irq_mask_reg = &TC1_IMR,
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.isr = stepper_tc1_irq,
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.status_reg = &TC1_SR,
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.tio_pin = TIOB1,
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.callback = NULL,
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.motor = NULL,
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},
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{ //Timer Counter settings for TIOA2 output pin
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.timer_id = TC2_ID,
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.blk_ctrl_set = TC_NONEXC2,
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.chl_mode_reg = &TC2_CMR,
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.chl_ctrl_reg = &TC2_CCR,
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.comp_reg = &TC2_RA,
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.comp_c_reg = &TC2_RC,
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.count_val_reg = &TC2_CV,
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.comp_effect_mask = TC_ACPA_MASK,
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.comp_effect_set = TC_ACPA_SET_OUTPUT,
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.comp_effect_clear = TC_ACPA_CLEAR_OUTPUT,
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.comp_effect_c_mask = TC_ACPC_MASK,
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.comp_effect_c_clear = TC_ACPC_CLEAR_OUTPUT,
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.ext_event_set = TC_EEVT_XC2,
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.irq_enable_reg = &TC2_IER,
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.irq_disable_reg = &TC2_IDR,
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.irq_set_mask = BV(TC_CPAS),
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.irq_mask_reg = &TC2_IMR,
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.isr = stepper_tc2_irq,
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.status_reg = &TC2_SR,
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.tio_pin = TIOA2,
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.callback = NULL,
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.motor = NULL,
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},
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{ //Timer Counter settings for TIOB2 output pin
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.timer_id = TC2_ID,
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.blk_ctrl_set = TC_NONEXC2,
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.chl_mode_reg = &TC2_CMR,
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.chl_ctrl_reg = &TC2_CCR,
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.comp_reg = &TC2_RB,
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.comp_c_reg = &TC2_RC,
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.count_val_reg = &TC2_CV,
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.comp_effect_mask = TC_BCPB_MASK,
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.comp_effect_set = TC_BCPB_SET_OUTPUT,
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.comp_effect_clear = TC_BCPB_CLEAR_OUTPUT,
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.comp_effect_c_mask = TC_BCPC_MASK,
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.comp_effect_c_clear = TC_BCPC_CLEAR_OUTPUT,
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.ext_event_set = TC_EEVT_XC2,
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.irq_enable_reg = &TC2_IER,
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.irq_disable_reg = &TC2_IDR,
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.irq_set_mask = BV(TC_CPBS),
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.irq_mask_reg = &TC2_IMR,
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.isr = stepper_tc2_irq,
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.status_reg = &TC2_SR,
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.tio_pin = TIOB2,
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.callback = NULL,
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.motor = NULL,
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}
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};
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/**
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* Generic TIO interrupt handler.
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*/
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INLINE void stepper_tc_tio_irq(struct TimerCounter * t)
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{
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//
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*t->chl_mode_reg &= ~t->comp_effect_c_mask;
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*t->chl_mode_reg |= t->comp_effect_c_clear;
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/*
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* Cleat TIO output on c register compare.
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* This generate an pulse with variable lenght, this
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* depend to delay that interrupt is realy service.
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*/
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*t->comp_c_reg = *t->count_val_reg + STEPPER_DELAY_ON_COMPARE_C;
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//Call the associate callback
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t->callback(t->motor);
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*t->chl_mode_reg &= ~t->comp_effect_c_mask;
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}
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/*
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* Interrupt handler for timer counter TCKL0
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*/
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DECLARE_ISR(stepper_tc0_irq)
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{
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/*
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* Warning: when we read the status_reg register, we reset it.
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* That mean if is occur an interrupt event we can read only
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* the last that has been occur. To not miss an interrupt event
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* we save the status_reg register and then we read it.
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*/
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uint32_t status_reg = TC0_SR & TC0_IMR;
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if (status_reg & BV(TC_CPAS))
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stepper_tc_tio_irq(&stepper_timers[TC_TIOA0]);
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if (status_reg & BV(TC_CPBS))
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stepper_tc_tio_irq(&stepper_timers[TC_TIOB0]);
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/* Inform hw that we have served the IRQ */
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AIC_EOICR = 0;
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}
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/*
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* Interrupt handler for timer counter TCKL1
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*/
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DECLARE_ISR(stepper_tc1_irq)
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{
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/*
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* Warning: when we read the status_reg register, we reset it.
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* That mean if is occur an interrupt event we can read only
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* the last that has been occur. To not miss an interrupt event
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* we save the status_reg register and then we read it.
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*/
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uint32_t status_reg = TC1_SR & TC1_IMR;
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if (status_reg & BV(TC_CPAS))
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stepper_tc_tio_irq(&stepper_timers[TC_TIOA1]);
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if (status_reg & BV(TC_CPBS))
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stepper_tc_tio_irq(&stepper_timers[TC_TIOB1]);
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/* Inform hw that we have served the IRQ */
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AIC_EOICR = 0;
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}
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/*
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* Interrupt handler for timer counter TCKL2
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*/
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DECLARE_ISR(stepper_tc2_irq)
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{
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/*
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* Warning: when we read the status_reg register, we reset it.
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* That mean if is occur an interrupt event we can read only
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* the last that has been occur. To not miss an interrupt event
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* we save the status_reg register and then we read it.
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*/
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uint32_t status_reg = TC2_SR & TC2_IMR;
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if (status_reg & BV(TC_CPAS))
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stepper_tc_tio_irq(&stepper_timers[TC_TIOA2]);
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if (status_reg & BV(TC_CPBS))
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stepper_tc_tio_irq(&stepper_timers[TC_TIOB2]);
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/* Inform hw that we have served the IRQ */
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AIC_EOICR = 0;
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}
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/**
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* Timer couter setup.
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*
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* This function apply to select timer couter all needed settings.
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* Every settings are stored in stepper_timers[].
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*/
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void stepper_tc_setup(int index, stepper_isr_t callback, struct Stepper *motor)
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{
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ASSERT(index < CONFIG_TC_STEPPER_MAX_NUM);
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motor->timer = &stepper_timers[index];
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//Disable PIO controller and enable TIO function
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TIO_PIO_PDR = BV(motor->timer->tio_pin);
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TIO_PIO_ABSR = BV(motor->timer->tio_pin);
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/*
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* Sets timer counter in waveform mode.
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* We set as default:
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* - Waveform mode 00 (see datasheet for more detail.)
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* - Master clock prescaler to STEPPER_MCK_PRESCALER
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* - Set none external event
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* - Clear pin output on comp_reg
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* - None effect on reg C compare
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*/
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*motor->timer->chl_mode_reg = BV(TC_WAVE);
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*motor->timer->chl_mode_reg |= motor->timer->ext_event_set;
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*motor->timer->chl_mode_reg &= ~TC_WAVSEL_MASK;
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*motor->timer->chl_mode_reg |= TC_WAVSEL_UP;
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*motor->timer->chl_mode_reg |= STEPPER_MCK_PRESCALER;
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*motor->timer->chl_mode_reg |= motor->timer->comp_effect_clear;
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*motor->timer->chl_mode_reg &= ~motor->timer->comp_effect_c_mask;
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//Reset comp_reg and C compare register
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*motor->timer->comp_reg = 0;
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*motor->timer->comp_c_reg = 0;
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//Register interrupt vector
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cpu_flags_t flags;
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IRQ_SAVE_DISABLE(flags);
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/*
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* Warning: To guarantee a correct management of interrupt event, we must
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* trig the interrupt on level sensitive. This becouse, we have only a common
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* line for interrupt request, and if we have at the same time two interrupt
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* request could be that the is service normaly but the second will never
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* been detected and interrupt will stay active but never serviced.
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*/
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AIC_SVR(motor->timer->timer_id) = motor->timer->isr;
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AIC_SMR(motor->timer->timer_id) = AIC_SRCTYPE_INT_LEVEL_SENSITIVE;
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AIC_IECR = BV(motor->timer->timer_id);
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// Disable interrupt on select timer counter
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stepper_tc_irq_disable(motor->timer);
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IRQ_RESTORE(flags);
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//Register callback
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motor->timer->callback = callback;
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motor->timer->motor = motor;
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}
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/**
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* Timer counter init.
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*/
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void stepper_tc_init(void)
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{
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STEPPER_STROBE_INIT;
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ASSERT(CONFIG_NUM_STEPPER_MOTORS <= CONFIG_TC_STEPPER_MAX_NUM);
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/*
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* Enable timer counter:
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* - power on all timer counter
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* - disable all interrupt
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* - disable all external event/timer source
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*/
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for (int i = 0; i < CONFIG_TC_STEPPER_MAX_NUM; i++)
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{
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PMC_PCER = BV(stepper_timers[i].timer_id);
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*stepper_timers[i].irq_disable_reg = 0xFFFFFFFF;
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TC_BMR = stepper_timers[i].blk_ctrl_set;
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}
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/*
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* Enable timer counter and start it.
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*/
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for (int i = 0; i < CONFIG_TC_STEPPER_MAX_NUM; i++)
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*stepper_timers[i].chl_ctrl_reg = (BV(TC_CLKEN) | BV(TC_SWTRG));
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}
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