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Reworked AFSK Struct

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Mark Qvist 2014-04-03 23:22:15 +02:00
parent 854d0abbe5
commit e76216875e
4 changed files with 115 additions and 153 deletions
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81
Modem/afsk.h
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@ -26,74 +26,49 @@ typedef struct Hdlc
typedef struct Afsk
{
// I/O hardware pins
int adcPin; // Pin for incoming signal
int dacPin; // Pin for outgoing signal
KFile fd;
// I/O hardware pins
int adcPin; // Pin for incoming signal
int dacPin; // Pin for outgoing signal
// General values
Hdlc hdlc; // We need a link control structure
uint16_t preambleLength; // Length of sync preamble
uint16_t tailLength; // Length of transmission tail
Hdlc hdlc; // We need a link control structure
uint16_t preambleLength; // Length of sync preamble
uint16_t tailLength; // Length of transmission tail
// Modulation values
uint8_t sample_index; // Current sample index for outgoing bit
uint8_t currentOutputByte; // Current byte to be modulated
uint8_t txBit; // Mask of current modulated bit
uint8_t sampleIndex; // Current sample index for outgoing bit
uint8_t currentOutputByte; // Current byte to be modulated
uint8_t txBit; // Mask of current modulated bit
bool bitStuff; // Whether bitstuffing is allowed
uint8_t bitstuffCount; // Counter for bit-stuffing
uint8_t bitstuffCount; // Counter for bit-stuffing
uint16_t phaseAcc; // Phase accumulator
uint16_t phaseInc; // Phase increment per sample
uint16_t phaseAcc; // Phase accumulator
uint16_t phaseInc; // Phase increment per sample
FIFOBuffer txFifo; // FIFO for transmit data
uint8_t txBuffer[TX_BUFLEN];// Actial data storage for said FIFO
FIFOBuffer txFifo; // FIFO for transmit data
uint8_t tx_buf[CONFIG_AFSK_TX_BUFLEN]; // Actial data storage for said FIFO
volatile bool sending; // Set when modem is sending
volatile bool sending; // Set when modem is sending
// Demodulation values
FIFOBuffer delayFifo; // Delayed FIFO for frequency discrimination
int8_t delayBuffer[5]; // Actual data storage for said FIFO
FIFOBuffer delayFifo; // Delayed FIFO for frequency discrimination
int8_t delay_buf[SAMPLESPERBIT / 2 + 1];// Actual data storage for said FIFO
FIFOBuffer rxFifo; // FIFO for received data
uint8_t rxBuffer[RX_BUFLEN];// Actual data storage for said FIFO
FIFOBuffer rxFifo; // FIFO for received data
uint8_t rx_buf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO
int16_t iirX[2]; // IIR Filter X cells
int16_t iirY[2]; // IIR Filter Y cells
int16_t iirX[2]; // IIR Filter X cells
int16_t iirY[2]; // IIR Filter Y cells
uint8_t sampledBits; // Bits sampled by the demodulator (at ADC speed)
int8_t currentPhase; // Current phase of the demodulator
uint8_t actualBits; // Actual found bits at correct bitrate
uint8_t sampledBits; // Bits sampled by the demodulator (at ADC speed)
int8_t currentPhase; // Current phase of the demodulator
uint8_t actualBits; // Actual found bits at correct bitrate
volatile int status; // Status of the modem, 0 means OK
volatile int status; // Status of the modem, 0 means OK
/*
KFile fd;
int adc_ch;
int dac_ch;
uint8_t sample_count;
uint8_t curr_out;
uint8_t tx_bit;
bool bit_stuff;
uint8_t stuff_cnt;
uint16_t phase_acc;
uint16_t phase_inc;
FIFOBuffer delay_fifo;
int8_t delay_buf[SAMPLESPERBIT / 2 + 1];
FIFOBuffer rx_fifo;
uint8_t rx_buf[CONFIG_AFSK_RX_BUFLEN];
FIFOBuffer tx_fifo;
uint8_t tx_buf[CONFIG_AFSK_TX_BUFLEN];
int16_t iir_x[2];
int16_t iir_y[2];
uint8_t sampled_bits;
int8_t curr_phase;
uint8_t found_bits;
volatile bool sending;
volatile int status;
Hdlc hdlc;
uint16_t preamble_len;
uint16_t trailer_len;
*/
} Afsk;
#define KFT_AFSK MAKE_ID('F', 'S', 'K', 'M')