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Migrated HDLC
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parent
16fd081e4b
commit
66ab74fca7
56
Modem/afsk.c
56
Modem/afsk.c
@ -62,23 +62,18 @@ STATIC_ASSERT(!(CONFIG_AFSK_DAC_SAMPLERATE % BITRATE));
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#define DAC_SAMPLESPERBIT (CONFIG_AFSK_DAC_SAMPLERATE / BITRATE)
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static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo)
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{
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static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo) {
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bool ret = true;
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hdlc->demodulatedBits <<= 1;
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hdlc->demodulatedBits |= bit ? 1 : 0;
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/* HDLC Flag */
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if (hdlc->demodulatedBits == HDLC_FLAG)
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{
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if (!fifo_isfull(fifo))
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{
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// Check if we have received a HDLC flag (01111110)
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if (hdlc->demodulatedBits == HDLC_FLAG) {
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if (!fifo_isfull(fifo)) {
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fifo_push(fifo, HDLC_FLAG);
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hdlc->receiving = true;
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}
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else
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{
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} else {
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ret = false;
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hdlc->receiving = false;
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}
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@ -88,56 +83,59 @@ static bool hdlcParse(Hdlc *hdlc, bool bit, FIFOBuffer *fifo)
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return ret;
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}
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/* Reset */
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if ((hdlc->demodulatedBits & HDLC_RESET) == HDLC_RESET)
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{
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// Check if we have received a RESET flag (01111111)
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if ((hdlc->demodulatedBits & HDLC_RESET) == HDLC_RESET) {
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hdlc->receiving = false;
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return ret;
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}
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// If we are just receiving noise, don't bother with anything
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if (!hdlc->receiving)
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return ret;
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/* Stuffed bit */
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// First check if what we are seeing is a stuffed bit
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if ((hdlc->demodulatedBits & 0x3f) == 0x3e)
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return ret;
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// If we have an actual 1 bit, push this to the current byte
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if (hdlc->demodulatedBits & 0x01)
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hdlc->currentByte |= 0x80;
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if (++hdlc->bitIndex >= 8)
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{
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if ((hdlc->currentByte == HDLC_FLAG
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|| hdlc->currentByte == HDLC_RESET
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|| hdlc->currentByte == AX25_ESC))
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{
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if (!fifo_isfull(fifo))
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// Increment the bitIndex and check if we have a complete byte
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if (++hdlc->bitIndex >= 8) {
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// If we have a HDLC control character,
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// put a AX.25 escape in the received data
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if ((hdlc->currentByte == HDLC_FLAG ||
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hdlc->currentByte == HDLC_RESET ||
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hdlc->currentByte == AX25_ESC)) {
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if (!fifo_isfull(fifo)) {
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fifo_push(fifo, AX25_ESC);
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else
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{
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} else {
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hdlc->receiving = false;
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ret = false;
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}
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}
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if (!fifo_isfull(fifo))
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// Push the actual byte to the received data FIFO
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if (!fifo_isfull(fifo)) {
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fifo_push(fifo, hdlc->currentByte);
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else
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{
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} else {
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hdlc->receiving = false;
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ret = false;
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}
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hdlc->currentByte = 0;
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hdlc->bitIndex = 0;
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}
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else
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} else {
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// We don't have a full byte yet, bitshift the byte
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// to make room for the next bit
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hdlc->currentByte >>= 1;
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}
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return ret;
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}
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void afsk_adc_isr(Afsk *afsk, int8_t currentSample) {
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// To determine the received frequency, and thereby
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// the bit of the sample, we multiply the sample by
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@ -1,2 +1,2 @@
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#define VERS_BUILD 81
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#define VERS_BUILD 93
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#define VERS_HOST "vixen"
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