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EEPROM configuration

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This commit is contained in:
Mark Qvist 2019-02-08 13:18:49 +01:00
parent b3b1a9b253
commit 474f3ad4d2
13 changed files with 429 additions and 131 deletions
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96
hardware/AFSK.c
View file

@ -4,16 +4,9 @@
#include "hardware/LED.h"
#include "protocol/KISS.h"
#include "hardware/SD.h"
// TODO: Remove testing vars ////
#define SAMPLES_TO_CAPTURE 128
ticks_t capturedsamples = 0;
uint8_t samplebuf[SAMPLES_TO_CAPTURE];
/////////////////////////////////
#include "util/Config.h"
extern volatile ticks_t _clock;
extern unsigned long custom_preamble;
extern unsigned long custom_tail;
bool hw_afsk_dac_isr = false;
bool hw_5v_ref = false;
@ -128,11 +121,11 @@ static void AFSK_txStart(Afsk *afsk) {
afsk->sending = true;
afsk->sending_data = true;
LED_TX_ON();
afsk->preambleLength = DIV_ROUND(custom_preamble * BITRATE, 8000);
afsk->preambleLength = DIV_ROUND(config_preamble * BITRATE, 8000);
AFSK_DAC_IRQ_START();
}
ATOMIC_BLOCK(ATOMIC_RESTORESTATE) {
afsk->tailLength = DIV_ROUND(custom_tail * BITRATE, 8000);
afsk->tailLength = DIV_ROUND(config_tail * BITRATE, 8000);
}
}
@ -468,50 +461,12 @@ void AFSK_adc_isr(Afsk *afsk, int8_t currentSample) {
#error No filters defined for specified samplerate!
#endif
// We put the sampled bit in a delay-line:
// First we bitshift everything 1 left
afsk->sampledBits <<= 1;
// And then add the sampled bit to our delay line
afsk->sampledBits |= (afsk->iirY[1] > 0) ? 0 : 1;
//afsk->sampledBits |= (freq_disc > 0) ? 0 : 1;
// Put the current raw sample in the delay FIFO
fifo_push(&afsk->delayFifo, currentSample);
// We need to check whether there is a signal transition.
// If there is, we can recalibrate the phase of our
// sampler to stay in sync with the transmitter. A bit of
// explanation is required to understand how this works.
// Since we have PHASE_MAX/PHASE_BITS = 8 samples per bit,
// we employ a phase counter (currentPhase), that increments
// by PHASE_BITS everytime a sample is captured. When this
// counter reaches PHASE_MAX, it wraps around by modulus
// PHASE_MAX. We then look at the last three samples we
// captured and determine if the bit was a one or a zero.
//
// This gives us a "window" looking into the stream of
// samples coming from the ADC. Sort of like this:
//
// Past Future
// 0000000011111111000000001111111100000000
// |________|
// ||
// Window
//
// Every time we detect a signal transition, we adjust
// where this window is positioned a little. How much we
// adjust it is defined by PHASE_INC. If our current phase
// phase counter value is less than half of PHASE_MAX (ie,
// the window size) when a signal transition is detected,
// add PHASE_INC to our phase counter, effectively moving
// the window a little bit backward (to the left in the
// illustration), inversely, if the phase counter is greater
// than half of PHASE_MAX, we move it forward a little.
// This way, our "window" is constantly seeking to position
// it's center at the bit transitions. Thus, we synchronise
// our timing to the transmitter, even if it's timing is
// a little off compared to our own.
if (SIGNAL_TRANSITIONED(afsk->sampledBits)) {
if (afsk->currentPhase < PHASE_THRESHOLD) {
afsk->currentPhase += PHASE_INC;
@ -523,24 +478,12 @@ void AFSK_adc_isr(Afsk *afsk, int8_t currentSample) {
afsk->silentSamples++;
}
// We increment our phase counter
afsk->currentPhase += PHASE_BITS;
// Check if we have reached the end of
// our sampling window.
if (afsk->currentPhase >= PHASE_MAX) {
// If we have, wrap around our phase
// counter by modulus
afsk->currentPhase %= PHASE_MAX;
// Bitshift to make room for the next
// bit in our stream of demodulated bits
afsk->actualBits <<= 1;
// We determine the actual bit value by reading
// the last 3 sampled bits. If there is two or
// more 1's, we will assume that the transmitter
// sent us a one, otherwise we assume a zero
uint8_t bits = afsk->sampledBits & 0x07;
if (bits == 0x07 || // 111
@ -551,39 +494,6 @@ void AFSK_adc_isr(Afsk *afsk, int8_t currentSample) {
afsk->actualBits |= 1;
}
//// Alternative using six bits ////////////////
// uint8_t bits = afsk->sampledBits & 0x3F;
// uint8_t c = 0;
// c += bits & _BV(0);
// c += bits & _BV(1);
// c += bits & _BV(2);
// c += bits & _BV(3);
// c += bits & _BV(4);
// c += bits & _BV(5);
// if (c >= 3) afsk->actualBits |= 1;
/////////////////////////////////////////////////
// Now we can pass the actual bit to the HDLC parser.
// We are using NRZ-S coding, so if 2 consecutive bits
// have the same value, we have a 1, otherwise a 0.
// We use the TRANSITION_FOUND function to determine this.
//
// This is smart in combination with bit stuffing,
// since it ensures a transmitter will never send more
// than five consecutive 1's. When sending consecutive
// ones, the signal stays at the same level, and if
// this happens for longer periods of time, we would
// not be able to synchronize our phase to the transmitter
// and would start experiencing "bit slip".
//
// By combining bit-stuffing with NRZ-S coding, we ensure
// that the signal will regularly make transitions
// that we can use to synchronize our phase.
//
// We also check the return of the Link Control parser
// to check if an error occured.
if (!hdlcParse(&afsk->hdlc, !TRANSITION_FOUND(afsk->actualBits), &afsk->rxFifo)) {
afsk->status |= 1;
if (fifo_isfull(&afsk->rxFifo)) {

1
hardware/AFSK.h
View file

@ -36,7 +36,6 @@ inline static uint8_t sinSample(uint16_t i) {
#define TRANSITION_FOUND(bits) BITS_DIFFER((bits), (bits) >> 1)
#define DUAL_XOR(bits1, bits2) ((((bits1)^(bits2)) & 0x03) == 0x03)
#define QUAD_XOR(bits1, bits2) ((((bits1)^(bits2)) & 0x0F) == 0x0F)
#define CPU_FREQ F_CPU

50
hardware/Crypto.c
View file

@ -1,4 +1,5 @@
#include "Crypto.h"
#include "util/Config.h"
bool encryption_enabled = false;
uint8_t active_key[CRYPTO_KEY_SIZE];
@ -18,17 +19,39 @@ FRESULT crypto_fr; // Result codes
void crypto_init(void) {
encryption_enabled = false;
if (load_key()) {
if (load_entropy_index() && load_entropy()) {
encryption_enabled = true;
if (should_disable_enryption()) {
if (config_crypto_lock) config_crypto_lock_disable();
} else {
if (load_key()) {
if (load_entropy_index() && load_entropy()) {
config_crypto_lock_enable();
encryption_enabled = true;
}
}
if (config_crypto_lock) {
if (encryption_enabled) {
LED_indicate_enabled_crypto();
} else {
LED_indicate_error_crypto();
}
}
}
}
if (encryption_enabled) {
LED_indicate_enabled_crypto();
} else {
LED_indicate_error_crypto();
bool crypto_wait(void) {
size_t wait_timer = 0;
size_t interval_ms = 100;
while (!crypto_enabled()) {
delay_ms(100);
wait_timer++;
sd_jobs();
if (wait_timer*interval_ms > CRYPTO_WAIT_TIMEOUT_MS) {
return false;
}
}
return true;
}
void crypto_generate_hmac(uint8_t *data, size_t length) {
@ -170,6 +193,19 @@ bool load_entropy(void) {
return false;
}
bool should_disable_enryption(void) {
if (sd_mounted()) {
crypto_fr = f_open(&crypto_fp, PATH_CRYPTO_DISABLE, FA_READ);
if (crypto_fr == FR_OK) {
f_close(&crypto_fp);
return true;
}
}
return false;
}
bool load_key(void) {
if (sd_mounted()) {
crypto_fr = f_open(&crypto_fp, PATH_AES_128_KEY, FA_READ);

6
hardware/Crypto.h
View file

@ -13,6 +13,7 @@
#define PATH_ENTROPY_INDEX "OpenModem/entropy.index"
#define PATH_ENTROPY_SOURCE "OpenModem/entropy.source"
#define PATH_AES_128_KEY "OpenModem/aes128.key"
#define PATH_CRYPTO_DISABLE "OpenModem/aes128.disable"
#define CRYPTO_KEY_SIZE_BITS 128
#define CRYPTO_KEY_SIZE (CRYPTO_KEY_SIZE_BITS/8)
@ -20,9 +21,13 @@
#define CRYPTO_HMAC_SIZE (CRYPTO_HMAC_SIZE_BITS/8)
#define MAX_IVS_PER_ENTROPY_BLOCK 128
#define CRYPTO_WAIT_TIMEOUT_MS 2000
uint8_t crypto_work_block[CRYPTO_KEY_SIZE];
void crypto_init(void);
bool crypto_wait(void);
bool crypto_enabled(void);
bool crypto_generate_iv(void);
uint8_t* crypto_get_iv(void);
@ -35,6 +40,7 @@ void crypto_decrypt_block(uint8_t block[CRYPTO_KEY_SIZE]);
void crypto_test(void);
bool should_disable_enryption(void);
bool load_key(void);
bool load_entropy(void);
bool load_entropy_index(void);

16
hardware/VREF.c
View file

@ -1,7 +1,5 @@
#include "VREF.h"
uint8_t adcReference = CONFIG_ADC_REF;
uint8_t dacReference = CONFIG_DAC_REF;
#include "util/Config.h"
void VREF_init(void) {
// Enable output for OC2A and OC2B (PD7 and PD6)
@ -14,17 +12,17 @@ void VREF_init(void) {
TCCR2B = _BV(CS20);
OCR2A = adcReference;
OCR2B = dacReference;
OCR2A = config_input_gain;
OCR2B = config_output_gain;
}
void vref_setADC(uint8_t value) {
adcReference = value;
OCR2A = adcReference;
config_input_gain = value;
OCR2A = config_input_gain;
}
void vref_setDAC(uint8_t value) {
dacReference = value;
OCR2B = dacReference;
config_output_gain = value;
OCR2B = config_output_gain;
}