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Reworked afsk init. Found the error :P

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Mark Qvist 2014-04-03 23:45:41 +02:00
parent e84705e5e1
commit 3265f99e8f
3 changed files with 31 additions and 31 deletions
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52
Modem/afsk.c
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@ -237,7 +237,7 @@ void afsk_adc_isr(Afsk *af, int8_t curr_sample)
* a 1 is received, otherwise it's a 0. * a 1 is received, otherwise it's a 0.
*/ */
if (!hdlcParse(&af->hdlc, !EDGE_FOUND(af->actualBits), &af->rxFifo)) if (!hdlcParse(&af->hdlc, !EDGE_FOUND(af->actualBits), &af->rxFifo))
af->status |= AFSK_RXFIFO_OVERRUN; af->status |= RX_OVERRUN;
} }
@ -459,34 +459,34 @@ static void afsk_clearerr(KFile *fd)
ATOMIC(af->status = 0); ATOMIC(af->status = 0);
} }
void afsk_init(Afsk *af, int adcPin, int dacPin) void afsk_init(Afsk *afsk, int _adcPin, int _dacPin) {
{ // Allocate memory for struct
#if CONFIG_AFSK_RXTIMEOUT != -1 memset(afsk, 0, sizeof(*afsk));
MOD_CHECK(timer);
#endif
memset(af, 0, sizeof(*af));
af->adcPin = adcPin;
af->dacPin = dacPin;
fifo_init(&af->delayFifo, (uint8_t *)af->delay_buf, sizeof(af->delay_buf)); // Configure pins
fifo_init(&af->rxFifo, af->rx_buf, sizeof(af->rx_buf)); afsk->adcPin = _adcPin;
afsk->dacPin = _dacPin;
afsk->phaseInc = MARK_INC;
/* Fill sample FIFO with 0 */ // Init FIFO buffers
for (int i = 0; i < SAMPLESPERBIT / 2; i++) fifo_init(&afsk->delayFifo, (uint8_t *)afsk->delayBuf, sizeof(afsk->delayBuf));
fifo_push(&af->delayFifo, 0); fifo_init(&afsk->rxFifo, afsk->rxBuf, sizeof(afsk->rxBuf));
fifo_init(&afsk->txFifo, afsk->txBuf, sizeof(afsk->txBuf));
fifo_init(&af->txFifo, af->tx_buf, sizeof(af->tx_buf)); // Fill delay FIFO with zeroes
for (int i = 0; i<SAMPLESPERBIT / 2; i++) {
fifo_push(&afsk->delayFifo, 0);
}
AFSK_ADC_INIT(adcPin, af); // Init DAC & ADC
AFSK_DAC_INIT(dacPin, af); AFSK_ADC_INIT(_adcPin, afsk);
AFSK_DAC_INIT(_dacPin, afsk);
AFSK_STROBE_INIT(); AFSK_STROBE_INIT();
//LOG_INFO("MARK_INC %d, SPACE_INC %d\n", MARK_INC, SPACE_INC);
DB(af->fd._type = KFT_AFSK); DB(afsk->fd._type = KFT_AFSK);
af->fd.write = afsk_write; afsk->fd.write = afsk_write;
af->fd.read = afsk_read; afsk->fd.read = afsk_read;
af->fd.flush = afsk_flush; afsk->fd.flush = afsk_flush;
af->fd.error = afsk_error; afsk->fd.error = afsk_error;
af->fd.clearerr = afsk_clearerr; afsk->fd.clearerr = afsk_clearerr;
af->phaseInc = MARK_INC; }
}

8
Modem/afsk.h
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@ -22,7 +22,7 @@ typedef struct Hdlc
bool receiving; // Whether or not where actually receiving data (or just noise ;P) bool receiving; // Whether or not where actually receiving data (or just noise ;P)
} Hdlc; } Hdlc;
#define AFSK_RXFIFO_OVERRUN BV(0) #define RX_OVERRUN BV(0)
typedef struct Afsk typedef struct Afsk
{ {
@ -49,16 +49,16 @@ typedef struct Afsk
uint16_t phaseInc; // Phase increment per sample uint16_t phaseInc; // Phase increment per sample
FIFOBuffer txFifo; // FIFO for transmit data FIFOBuffer txFifo; // FIFO for transmit data
uint8_t tx_buf[CONFIG_AFSK_TX_BUFLEN]; // Actial data storage for said FIFO uint8_t txBuf[CONFIG_AFSK_TX_BUFLEN]; // Actial data storage for said FIFO
volatile bool sending; // Set when modem is sending volatile bool sending; // Set when modem is sending
// Demodulation values // Demodulation values
FIFOBuffer delayFifo; // Delayed FIFO for frequency discrimination FIFOBuffer delayFifo; // Delayed FIFO for frequency discrimination
int8_t delay_buf[SAMPLESPERBIT / 2 + 1];// Actual data storage for said FIFO int8_t delayBuf[SAMPLESPERBIT / 2 + 1];// Actual data storage for said FIFO
FIFOBuffer rxFifo; // FIFO for received data FIFOBuffer rxFifo; // FIFO for received data
uint8_t rx_buf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO uint8_t rxBuf[CONFIG_AFSK_RX_BUFLEN]; // Actual data storage for said FIFO
int16_t iirX[2]; // IIR Filter X cells int16_t iirX[2]; // IIR Filter X cells
int16_t iirY[2]; // IIR Filter Y cells int16_t iirY[2]; // IIR Filter Y cells

2
buildrev.h
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@ -1,2 +1,2 @@
#define VERS_BUILD 51 #define VERS_BUILD 76
#define VERS_HOST "vixen" #define VERS_HOST "vixen"