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Implemented KISS flow control

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This commit is contained in:
Mark Qvist 2018-04-24 14:34:59 +02:00
parent 9b4105c585
commit 2c80adbda4
5 changed files with 25 additions and 4 deletions
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3
hardware/AFSK.c
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@ -84,6 +84,7 @@ static void AFSK_txStart(Afsk *afsk) {
afsk->phaseAcc = 0;
afsk->bitstuffCount = 0;
afsk->sending = true;
afsk->sending_data = true;
LED_TX_ON();
afsk->preambleLength = DIV_ROUND(custom_preamble * BITRATE, 8000);
AFSK_DAC_IRQ_START();
@ -121,6 +122,7 @@ uint8_t AFSK_dac_isr(Afsk *afsk) {
if (fifo_isempty(&afsk->txFifo) && afsk->tailLength == 0) {
AFSK_DAC_IRQ_STOP();
afsk->sending = false;
afsk->sending_data = false;
LED_TX_OFF();
return 0;
} else {
@ -128,6 +130,7 @@ uint8_t AFSK_dac_isr(Afsk *afsk) {
afsk->bitStuff = true;
if (afsk->preambleLength == 0) {
if (fifo_isempty(&afsk->txFifo)) {
afsk->sending_data = false;
afsk->tailLength--;
afsk->currentOutputByte = HDLC_FLAG;
} else {

3
hardware/AFSK.h
View file

@ -104,9 +104,10 @@ typedef struct Afsk
uint16_t phaseInc; // Phase increment per sample
FIFOBuffer txFifo; // FIFO for transmit data
uint8_t txBuf[CONFIG_AFSK_TX_BUFLEN]; // Actial data storage for said FIFO
uint8_t txBuf[CONFIG_AFSK_TX_BUFLEN]; // Actual data storage for said FIFO
volatile bool sending; // Set when modem is sending
volatile bool sending_data; // Set when modem is sending data
// Demodulation values
FIFOBuffer delayFifo; // Delayed FIFO for frequency discrimination