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Preamble timing
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parent
0a1c0716ed
commit
13873775e8
10
Modem/afsk.c
10
Modem/afsk.c
@ -353,6 +353,8 @@ void afsk_adc_isr(Afsk *afsk, int8_t currentSample) {
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// the last 3 sampled bits. If there is two or
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// the last 3 sampled bits. If there is two or
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// more 1's, we will assume that the transmitter
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// more 1's, we will assume that the transmitter
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// sent us a one, otherwise we assume a zero
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// sent us a one, otherwise we assume a zero
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// FIXME: Increasing this to 5 bit determine
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uint8_t bits = afsk->sampledBits & 0x07;
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uint8_t bits = afsk->sampledBits & 0x07;
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if (bits == 0x07 || // 111
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if (bits == 0x07 || // 111
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bits == 0x06 || // 110
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bits == 0x06 || // 110
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@ -361,6 +363,14 @@ void afsk_adc_isr(Afsk *afsk, int8_t currentSample) {
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) {
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) {
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afsk->actualBits |= 1;
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afsk->actualBits |= 1;
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}
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}
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// uint8_t bits = afsk->sampledBits & 0x0f;
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// uint8_t c = 0;
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// c += bits & BV(1);
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// c += bits & BV(2);
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// c += bits & BV(3);
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// c += bits & BV(4);
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// c += bits & BV(5);
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// if (c >= 3) afsk->actualBits |= 1;
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// Now we can pass the actual bit to the HDLC parser.
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// Now we can pass the actual bit to the HDLC parser.
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// We are using NRZ coding, so if 2 consecutive bits
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// We are using NRZ coding, so if 2 consecutive bits
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@ -1,2 +1,2 @@
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#define VERS_BUILD 444
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#define VERS_BUILD 448
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#define VERS_HOST "vixen"
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#define VERS_HOST "vixen"
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