mirror of
https://github.com/Divested-Mobile/DivestOS-Build.git
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244 lines
13 KiB
Diff
244 lines
13 KiB
Diff
From 946a09f5411890b1b1ec945b8c882bfa042f4523 Mon Sep 17 00:00:00 2001
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From: anarkia1976 <stefano.villa1976@gmail.com>
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Date: Wed, 5 Feb 2014 07:12:48 +0100
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Subject: [PATCH] msm: cpu: overclock: use higher bus speed at lower CPU freqs
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Thanks to @bedalus and @mrg666
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Bedalus suggested that if lower CPU frequencies can offer higher bus
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speed,
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GPU use during games wouldn't require higher CPU frequency.
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My testing demonstrated 4C drop in CPU temp during 3DMark benchmark.
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Still needs to be tested for everyday use.
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---
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arch/arm/mach-msm/acpuclock-8064.c | 172 +++++++++++++++++++------------------
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1 file changed, 88 insertions(+), 84 deletions(-)
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diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
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index 7879be1d564..cd045cf0c97 100644
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--- a/arch/arm/mach-msm/acpuclock-8064.c
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+++ b/arch/arm/mach-msm/acpuclock-8064.c
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@@ -132,6 +132,14 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
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.name = "acpuclk-8064",
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};
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+#ifdef CONFIG_LOW_CPUCLOCKS
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+#define L2_BW_MID 6
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+#define L2_BW_HIGH 15
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+#else
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+#define L2_BW_MID 5
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+#define L2_BW_HIGH 14
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+#endif
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+
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static struct l2_level l2_freq_tbl[] __initdata = {
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#ifdef CONFIG_LOW_CPUCLOCKS
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[0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 },
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@@ -175,32 +183,31 @@ static struct acpu_level tbl_slow[] __initdata = {
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{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
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{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 },
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{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 },
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- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 },
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 },
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#else
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
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#endif
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- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
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- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
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- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
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- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
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- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
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- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
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- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1075000 },
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- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1075000 },
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- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1100000 },
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- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1100000 },
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- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1125000 },
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- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1125000 },
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- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1175000 },
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- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1175000 },
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- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1200000 },
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- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1200000 },
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- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1225000 },
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- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1225000 },
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- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 },
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- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 },
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- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 },
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+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 975000 },
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+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 975000 },
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+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 1000000 },
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+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 1000000 },
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+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 1025000 },
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+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 1025000 },
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+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 1075000 },
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+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 1075000 },
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+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1100000 },
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+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1100000 },
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+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1125000 },
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+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1125000 },
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+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1175000 },
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+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1175000 },
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+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1200000 },
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+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1200000 },
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+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1225000 },
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+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1225000 },
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+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1237500 },
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+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1237500 },
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+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1250000 },
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#ifdef CONFIG_CPU_OVERCLOCK
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 },
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@@ -216,32 +223,31 @@ static struct acpu_level tbl_nom[] __initdata = {
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{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
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{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 },
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{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 },
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- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 },
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 },
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#else
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
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#endif
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- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
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- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
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- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 },
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- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
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- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 975000 },
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- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 },
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- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1025000 },
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- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1025000 },
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- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1050000 },
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- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1050000 },
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- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1075000 },
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- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1075000 },
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- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1125000 },
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- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1125000 },
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- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1150000 },
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- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1150000 },
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- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1175000 },
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- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1175000 },
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- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 },
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- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 },
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- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 },
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+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 925000 },
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+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 925000 },
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+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 950000 },
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+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 950000 },
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+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 975000 },
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+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 975000 },
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+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 1025000 },
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+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 1025000 },
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+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1050000 },
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+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1050000 },
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+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1075000 },
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+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1075000 },
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+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1125000 },
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+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1125000 },
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+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1150000 },
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+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1150000 },
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+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1175000 },
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+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1175000 },
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+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1187500 },
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+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1187500 },
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+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1200000 },
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#ifdef CONFIG_CPU_OVERCLOCK
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 },
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@@ -257,32 +263,31 @@ static struct acpu_level tbl_fast[] __initdata = {
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{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
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{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
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{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
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- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
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#else
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
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#endif
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- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
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- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
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- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
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- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
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- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
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- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
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- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 975000 },
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- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
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- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1000000 },
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- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
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- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1025000 },
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- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1025000 },
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- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1075000 },
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- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
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- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1100000 },
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- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1100000 },
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- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1125000 },
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- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
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- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 },
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- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 },
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- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 },
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+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 },
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+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 },
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+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 },
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+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 900000 },
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+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 925000 },
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+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 925000 },
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+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 975000 },
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+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 975000 },
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+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1000000 },
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+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1000000 },
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+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1025000 },
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+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1025000 },
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+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1075000 },
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+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1075000 },
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+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1100000 },
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+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1100000 },
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+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1125000 },
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+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1125000 },
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+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1137500 },
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+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1137500 },
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+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1150000 },
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#ifdef CONFIG_CPU_OVERCLOCK
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{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 },
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{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
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@@ -298,28 +303,27 @@ static struct acpu_level tbl_faster[] __initdata = {
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{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
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{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
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{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
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- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
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#else
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
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#endif
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- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
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- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
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- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
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- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
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- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
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- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
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- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 962500 },
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- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
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- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 975000 },
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- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
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- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1000000 },
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- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1000000 },
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- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1050000 },
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- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1050000 },
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- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1075000 },
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- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1075000 },
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- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1100000 },
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+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 },
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+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 },
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+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 },
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+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 900000 },
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+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 925000 },
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+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 925000 },
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+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 962500 },
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+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 962500 },
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+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 975000 },
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+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 975000 },
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+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1000000 },
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+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1000000 },
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+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1050000 },
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+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1050000 },
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+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1075000 },
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+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1075000 },
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+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1100000 },
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|
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1100000 },
|
|
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 },
|
|
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
|