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DivestOS/Patches/LineageOS-15.1/android_kernel_lge_mako/0001-Overclock.patch
Tad fcea2b8d1d Lots of cleanup 
- Some overclocks might be missing'
2018-04-06 14:10:43 -04:00

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From 5858badcc16994ea21140b5a905536d365da45b4 Mon Sep 17 00:00:00 2001
From: anarkia1976 <stefano.villa1976@gmail.com>
Date: Sun, 12 Jan 2014 20:26:27 +0100
Subject: [PATCH] msm: cpu: overclock: added low (162Mhz) and high (1944Mhz)
cpu
---
arch/arm/mach-msm/Kconfig | 13 ++++++
arch/arm/mach-msm/acpuclock-8064.c | 91 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-msm/acpuclock-krait.c | 8 +++-
arch/arm/mach-msm/msm_dcvs.c | 5 ++
4 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 890c96e3a1f..814ab1a88b4 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1633,6 +1633,19 @@ config MSM_CPU_FREQ_MIN
endif # CPU_FREQ_MSM
+config LOW_CPUCLOCKS
+ bool "Enable ultra low CPU clocks"
+ default n
+ help
+ Ultra low cpu frequencies enabled for CPU and L2 Cache
+
+config CPU_OVERCLOCK
+ bool "Enable CPU Overclocking option"
+ default n
+ help
+ Krait overclocking up to 1.9 GHz
+
+
config MSM_AVS_HW
bool "Enable Adaptive Voltage Scaling (AVS)"
default n
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 8262946e016..f40edd3d687 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -47,7 +47,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait0", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait0", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -58,7 +62,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait1", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait1", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
@@ -69,7 +77,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x6501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait2", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait2", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait2_mem", 1150000 },
.vreg[VREG_DIG] = { "krait2_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
@@ -80,7 +92,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x7501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait3", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait3", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait3_mem", 1150000 },
.vreg[VREG_DIG] = { "krait3_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
@@ -116,6 +132,24 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
};
static struct l2_level l2_freq_tbl[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ [0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 },
+ [1] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
+ [2] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
+ [3] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
+ [4] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
+ [5] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
+ [6] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
+ [7] = { { 702000, HFPLL, 1, 0x1A }, 1150000, 1150000, 4 },
+ [8] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
+ [9] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
+ [10] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
+ [11] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
+ [12] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 },
+ [13] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
+ [14] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
+ [15] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+#else
[0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
[1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
[2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
@@ -131,11 +165,19 @@ static struct l2_level l2_freq_tbl[] __initdata = {
[12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
[13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
[14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+#endif
{ }
};
static struct acpu_level tbl_slow[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
@@ -157,11 +199,25 @@ static struct acpu_level tbl_slow[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 },
+#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_nom[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 },
@@ -183,11 +239,25 @@ static struct acpu_level tbl_nom[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 },
+#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_fast[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
@@ -209,11 +279,25 @@ static struct acpu_level tbl_fast[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 },
+#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_faster[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
@@ -235,6 +319,13 @@ static struct acpu_level tbl_faster[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 },
+#endif
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index e3a3f5486e4..97f6f3909f5 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -45,6 +45,12 @@
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
+#ifdef CONFIG_LOW_CPUCLOCKS
+#define FREQ_TABLE_SIZE 39
+#else
+#define FREQ_TABLE_SIZE 35
+#endif
+
static DEFINE_MUTEX(driver_lock);
static DEFINE_SPINLOCK(l2_lock);
@@ -913,7 +919,7 @@ static void __init bus_init(const struct l2_level *l2_level)
}
#ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE];
static void __init cpufreq_table_init(void)
{
diff --git a/arch/arm/mach-msm/msm_dcvs.c b/arch/arm/mach-msm/msm_dcvs.c
index 1a919fcf577..1d5e289b9b8 100644
--- a/arch/arm/mach-msm/msm_dcvs.c
+++ b/arch/arm/mach-msm/msm_dcvs.c
@@ -146,7 +146,12 @@ static struct dcvs_core core_list[CORES_MAX];
static struct kobject *cores_kobj;
+#ifdef CONFIG_CPU_OVERCLOCK
+#define DCVS_MAX_NUM_FREQS 20
+#else
#define DCVS_MAX_NUM_FREQS 15
+#endif
+
static struct msm_dcvs_freq_entry cpu_freq_tbl[DCVS_MAX_NUM_FREQS];
static unsigned num_cpu_freqs;
static struct msm_dcvs_platform_data *dcvs_pdata;
--
2.15.1
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