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49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
From fae242db5e1943ba878b4fb215fe6e7f1c387a20 Mon Sep 17 00:00:00 2001
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From: Tony Truong <truong@codeaurora.org>
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Date: Fri, 6 Jan 2017 14:03:03 -0800
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Subject: msm: pcie: add bounds check for debugfs register write
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Via debugfs nodes, users have the option to read and write to
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any PCIe register. To ensure clients do not access registers
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outside the PCIe range, add checks to validate the offset clients
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provide.
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Bug: 33039685
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Change-Id: Ia35cd04c57f01c21a47962be596bca395b5ca247
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Signed-off-by: Tony Truong <truong@codeaurora.org>
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---
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drivers/pci/host/pci-msm.c | 13 ++++++++++---
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1 file changed, 10 insertions(+), 3 deletions(-)
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diff --git a/drivers/pci/host/pci-msm.c b/drivers/pci/host/pci-msm.c
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index 1b80fa1..ffaa059 100644
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--- a/drivers/pci/host/pci-msm.c
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+++ b/drivers/pci/host/pci-msm.c
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@@ -1,4 +1,4 @@
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-/* Copyright (c) 2014-2015, The Linux Foundation. All rights reserved.
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+/* Copyright (c) 2014-2017, The Linux Foundation. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 and
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@@ -1691,8 +1691,15 @@ static void msm_pcie_sel_debug_testcase(struct msm_pcie_dev_t *dev,
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dev->res[base_sel - 1].base,
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wr_offset, wr_mask, wr_value);
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- msm_pcie_write_reg_field(dev->res[base_sel - 1].base,
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- wr_offset, wr_mask, wr_value);
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+ base_sel_size = resource_size(dev->res[base_sel - 1].resource);
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+
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+ if (wr_offset > base_sel_size - 4 ||
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+ msm_pcie_check_align(dev, wr_offset))
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+ pr_alert("PCIe: RC%d: Invalid wr_offset: 0x%x. wr_offset should be no more than 0x%x\n",
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+ dev->rc_idx, wr_offset, base_sel_size - 4);
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+ else
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+ msm_pcie_write_reg_field(dev->res[base_sel - 1].base,
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+ wr_offset, wr_mask, wr_value);
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break;
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case 13: /* dump all registers of base_sel */
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--
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cgit v1.1
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