mirror of
https://github.com/Divested-Mobile/DivestOS-Build.git
synced 2024-12-30 01:46:30 -05:00
125 lines
3.8 KiB
Diff
125 lines
3.8 KiB
Diff
From 323a28bf14c622bdd1b9ecf09a339b00af98c965 Mon Sep 17 00:00:00 2001
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From: Insun Song <insun.song@broadcom.com>
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Date: Wed, 23 Nov 2016 08:29:33 -0800
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Subject: [PATCH] net: wireless: bcmdhd: remove PCIe debug IOVAR access
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delete PCIe debug IOVARs in production build.
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BUG: 31707909
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Signed-off-by: Insun Song <insun.song@broadcom.com>
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Change-Id: Icd659169eeae3e587bec1f5587511a354d482a33
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---
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drivers/net/wireless/bcmdhd/dhd_pcie.c | 98 ----------------------------------
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1 file changed, 98 deletions(-)
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diff --git a/drivers/net/wireless/bcmdhd/dhd_pcie.c b/drivers/net/wireless/bcmdhd/dhd_pcie.c
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index 26201a6d2f39d..c56f789c4797f 100644
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--- a/drivers/net/wireless/bcmdhd/dhd_pcie.c
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+++ b/drivers/net/wireless/bcmdhd/dhd_pcie.c
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@@ -2609,104 +2609,6 @@ dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, cons
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bcmerror = dhdpcie_downloadvars(bus, arg, len);
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break;
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- case IOV_SVAL(IOV_PCIEREG):
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- si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,
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- int_val);
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- si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0,
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- int_val2);
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- break;
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-
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- case IOV_GVAL(IOV_PCIEREG):
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- si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0,
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- int_val);
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- int_val = si_corereg(bus->sih, bus->sih->buscoreidx,
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- OFFSETOF(sbpcieregs_t, configdata), 0, 0);
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- bcopy(&int_val, arg, sizeof(int_val));
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- break;
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-
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- case IOV_GVAL(IOV_BAR0_SECWIN_REG):
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- {
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- uint32 cur_base, base;
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- uchar *bar0;
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- volatile uint32 *offset;
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- /* set the bar0 secondary window to this */
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- /* write the register value */
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- cur_base = dhdpcie_bus_cfg_read_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint));
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- base = int_val & 0xFFFFF000;
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- dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), base);
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- bar0 = (uchar *)bus->regs;
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- offset = (uint32 *)(bar0 + 0x4000 + (int_val & 0xFFF));
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- int_val = *offset;
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- bcopy(&int_val, arg, sizeof(int_val));
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- dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), cur_base);
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- }
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- break;
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- case IOV_SVAL(IOV_BAR0_SECWIN_REG):
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- {
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- uint32 cur_base, base;
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- uchar *bar0;
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- volatile uint32 *offset;
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- /* set the bar0 secondary window to this */
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- /* write the register value */
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- cur_base = dhdpcie_bus_cfg_read_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint));
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- base = int_val & 0xFFFFF000;
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- dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), base);
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- bar0 = (uchar *)bus->regs;
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- offset = (uint32 *)(bar0 + 0x4000 + (int_val & 0xFFF));
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- *offset = int_val2;
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- bcopy(&int_val2, arg, val_size);
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- dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), cur_base);
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- }
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- break;
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-
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- case IOV_SVAL(IOV_PCIECOREREG):
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- si_corereg(bus->sih, bus->sih->buscoreidx, int_val, ~0, int_val2);
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- break;
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- case IOV_GVAL(IOV_SBREG):
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- {
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- sdreg_t sdreg;
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- uint32 addr, coreidx;
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-
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- bcopy(params, &sdreg, sizeof(sdreg));
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-
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- addr = sdreg.offset;
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- coreidx = (addr & 0xF000) >> 12;
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-
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- int_val = si_corereg(bus->sih, coreidx, (addr & 0xFFF), 0, 0);
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- bcopy(&int_val, arg, sizeof(int32));
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- break;
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- }
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-
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- case IOV_SVAL(IOV_SBREG):
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- {
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- sdreg_t sdreg;
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- uint32 addr, coreidx;
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-
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- bcopy(params, &sdreg, sizeof(sdreg));
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-
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- addr = sdreg.offset;
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- coreidx = (addr & 0xF000) >> 12;
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-
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- si_corereg(bus->sih, coreidx, (addr & 0xFFF), ~0, sdreg.value);
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-
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- break;
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- }
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-
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-
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- case IOV_GVAL(IOV_PCIECOREREG):
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- int_val = si_corereg(bus->sih, bus->sih->buscoreidx, int_val, 0, 0);
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- bcopy(&int_val, arg, sizeof(int_val));
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- break;
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-
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- case IOV_SVAL(IOV_PCIECFGREG):
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- OSL_PCI_WRITE_CONFIG(bus->osh, int_val, 4, int_val2);
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- break;
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-
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- case IOV_GVAL(IOV_PCIECFGREG):
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- int_val = OSL_PCI_READ_CONFIG(bus->osh, int_val, 4);
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- bcopy(&int_val, arg, sizeof(int_val));
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- break;
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-
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case IOV_SVAL(IOV_PCIE_LPBK):
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bcmerror = dhdpcie_bus_lpback_req(bus, int_val);
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break;
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