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112 lines
3.8 KiB
Diff
112 lines
3.8 KiB
Diff
From 8fff105e13041e49b82f92eef034f363a6b1c071 Mon Sep 17 00:00:00 2001
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From: "Suzuki K. Poulose" <suzuki.poulose@arm.com>
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Date: Tue, 17 Mar 2015 18:14:59 +0000
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Subject: arm64: perf: reject groups spanning multiple HW PMUs
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The perf core implicitly rejects events spanning multiple HW PMUs, as in
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these cases the event->ctx will differ. However this validation is
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performed after pmu::event_init() is called in perf_init_event(), and
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thus pmu::event_init() may be called with a group leader from a
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different HW PMU.
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The ARM64 PMU driver does not take this fact into account, and when
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validating groups assumes that it can call to_arm_pmu(event->pmu) for
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any HW event. When the event in question is from another HW PMU this is
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wrong, and results in dereferencing garbage.
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This patch updates the ARM64 PMU driver to first test for and reject
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events from other PMUs, moving the to_arm_pmu and related logic after
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this test. Fixes a crash triggered by perf_fuzzer on Linux-4.0-rc2, with
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a CCI PMU present:
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Bad mode in Synchronous Abort handler detected, code 0x86000006 -- IABT (current EL)
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CPU: 0 PID: 1371 Comm: perf_fuzzer Not tainted 3.19.0+ #249
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Hardware name: V2F-1XV7 Cortex-A53x2 SMM (DT)
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task: ffffffc07c73a280 ti: ffffffc07b0a0000 task.ti: ffffffc07b0a0000
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PC is at 0x0
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LR is at validate_event+0x90/0xa8
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pc : [<0000000000000000>] lr : [<ffffffc000090228>] pstate: 00000145
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sp : ffffffc07b0a3ba0
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[< (null)>] (null)
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[<ffffffc0000907d8>] armpmu_event_init+0x174/0x3cc
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[<ffffffc00015d870>] perf_try_init_event+0x34/0x70
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[<ffffffc000164094>] perf_init_event+0xe0/0x10c
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[<ffffffc000164348>] perf_event_alloc+0x288/0x358
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[<ffffffc000164c5c>] SyS_perf_event_open+0x464/0x98c
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Code: bad PC value
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Also cleans up the code to use the arm_pmu only when we know
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that we are dealing with an arm pmu event.
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Cc: Will Deacon <will.deacon@arm.com>
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Acked-by: Mark Rutland <mark.rutland@arm.com>
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Acked-by: Peter Ziljstra (Intel) <peterz@infradead.org>
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Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
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Signed-off-by: Will Deacon <will.deacon@arm.com>
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---
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arch/arm64/kernel/perf_event.c | 21 +++++++++++++++------
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1 file changed, 15 insertions(+), 6 deletions(-)
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diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
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index 25a5308..68a7415 100644
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--- a/arch/arm64/kernel/perf_event.c
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+++ b/arch/arm64/kernel/perf_event.c
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@@ -322,22 +322,31 @@ out:
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}
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static int
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-validate_event(struct pmu_hw_events *hw_events,
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- struct perf_event *event)
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+validate_event(struct pmu *pmu, struct pmu_hw_events *hw_events,
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+ struct perf_event *event)
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{
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- struct arm_pmu *armpmu = to_arm_pmu(event->pmu);
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+ struct arm_pmu *armpmu;
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struct hw_perf_event fake_event = event->hw;
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struct pmu *leader_pmu = event->group_leader->pmu;
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if (is_software_event(event))
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return 1;
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+ /*
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+ * Reject groups spanning multiple HW PMUs (e.g. CPU + CCI). The
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+ * core perf code won't check that the pmu->ctx == leader->ctx
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+ * until after pmu->event_init(event).
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+ */
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+ if (event->pmu != pmu)
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+ return 0;
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+
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if (event->pmu != leader_pmu || event->state < PERF_EVENT_STATE_OFF)
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return 1;
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if (event->state == PERF_EVENT_STATE_OFF && !event->attr.enable_on_exec)
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return 1;
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+ armpmu = to_arm_pmu(event->pmu);
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return armpmu->get_event_idx(hw_events, &fake_event) >= 0;
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}
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@@ -355,15 +364,15 @@ validate_group(struct perf_event *event)
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memset(fake_used_mask, 0, sizeof(fake_used_mask));
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fake_pmu.used_mask = fake_used_mask;
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- if (!validate_event(&fake_pmu, leader))
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+ if (!validate_event(event->pmu, &fake_pmu, leader))
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return -EINVAL;
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list_for_each_entry(sibling, &leader->sibling_list, group_entry) {
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- if (!validate_event(&fake_pmu, sibling))
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+ if (!validate_event(event->pmu, &fake_pmu, sibling))
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return -EINVAL;
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}
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- if (!validate_event(&fake_pmu, event))
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+ if (!validate_event(event->pmu, &fake_pmu, event))
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return -EINVAL;
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return 0;
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--
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cgit v1.1
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