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https://github.com/Divested-Mobile/DivestOS-Build.git
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217 lines
7.3 KiB
Diff
217 lines
7.3 KiB
Diff
From 4f57652fcd2dce7741f1ac6dc0417e2f265cd1de Mon Sep 17 00:00:00 2001
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From: =?UTF-8?q?Andr=C3=A9=20Hentschel?= <nerv@dawncrow.de>
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Date: Tue, 18 Jun 2013 23:23:26 +0100
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Subject: ARM: 7735/2: Preserve the user r/w register TPIDRURW on context
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switch and fork
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MIME-Version: 1.0
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Content-Type: text/plain; charset=UTF-8
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Content-Transfer-Encoding: 8bit
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Since commit 6a1c53124aa1 the user writeable TLS register was zeroed to
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prevent it from being used as a covert channel between two tasks.
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There are more and more applications coming to Windows RT,
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Wine could support them, but mostly they expect to have
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the thread environment block (TEB) in TPIDRURW.
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This patch preserves that register per thread instead of clearing it.
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Unlike the TPIDRURO, which is already switched, the TPIDRURW
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can be updated from userspace so needs careful treatment in the case that we
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modify TPIDRURW and call fork(). To avoid this we must always read
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TPIDRURW in copy_thread.
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Change-Id: Ib1e25be7b9faa846ba5335aad2574e21a1246066
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Signed-off-by: André Hentschel <nerv@dawncrow.de>
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Signed-off-by: Will Deacon <will.deacon@arm.com>
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Signed-off-by: Jonathan Austin <jonathan.austin@arm.com>
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Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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Git-commit: a4780adeefd042482f624f5e0d577bf9cdcbb760
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Git-repo: git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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[joonwoop@codeaurora.org: fixed merge conflict]
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CRs-fixed: 561044
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Signed-off-by: Joonwoo Park <joonwoop@codeaurora.org>
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---
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arch/arm/include/asm/thread_info.h | 2 +-
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arch/arm/include/asm/tls.h | 40 +++++++++++++++++++++++++-------------
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arch/arm/kernel/entry-armv.S | 5 +++--
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arch/arm/kernel/process.c | 4 +++-
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arch/arm/kernel/ptrace.c | 2 +-
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arch/arm/kernel/traps.c | 4 ++--
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6 files changed, 37 insertions(+), 20 deletions(-)
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diff --git a/arch/arm/include/asm/thread_info.h b/arch/arm/include/asm/thread_info.h
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index 67d6443..2eb0c2c 100644
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--- a/arch/arm/include/asm/thread_info.h
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+++ b/arch/arm/include/asm/thread_info.h
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@@ -58,7 +58,7 @@ struct thread_info {
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struct cpu_context_save cpu_context; /* cpu context */
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__u32 syscall; /* syscall number */
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__u8 used_cp[16]; /* thread used copro */
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- unsigned long tp_value;
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+ unsigned long tp_value[2]; /* TLS registers */
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struct crunch_state crunchstate;
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union fp_state fpstate __attribute__((aligned(8)));
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union vfp_state vfpstate;
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diff --git a/arch/arm/include/asm/tls.h b/arch/arm/include/asm/tls.h
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index 73409e6..83259b8 100644
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--- a/arch/arm/include/asm/tls.h
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+++ b/arch/arm/include/asm/tls.h
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@@ -2,27 +2,30 @@
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#define __ASMARM_TLS_H
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#ifdef __ASSEMBLY__
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- .macro set_tls_none, tp, tmp1, tmp2
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+#include <asm/asm-offsets.h>
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+ .macro switch_tls_none, base, tp, tpuser, tmp1, tmp2
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.endm
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- .macro set_tls_v6k, tp, tmp1, tmp2
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+ .macro switch_tls_v6k, base, tp, tpuser, tmp1, tmp2
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+ mrc p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
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mcr p15, 0, \tp, c13, c0, 3 @ set TLS register
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- mov \tmp1, #0
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- mcr p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
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+ mcr p15, 0, \tpuser, c13, c0, 2 @ and the user r/w register
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+ str \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
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.endm
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- .macro set_tls_v6, tp, tmp1, tmp2
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+ .macro switch_tls_v6, base, tp, tpuser, tmp1, tmp2
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ldr \tmp1, =elf_hwcap
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ldr \tmp1, [\tmp1, #0]
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mov \tmp2, #0xffff0fff
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tst \tmp1, #HWCAP_TLS @ hardware TLS available?
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- mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
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- movne \tmp1, #0
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- mcrne p15, 0, \tmp1, c13, c0, 2 @ clear user r/w TLS register
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streq \tp, [\tmp2, #-15] @ set TLS value at 0xffff0ff0
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+ mrcne p15, 0, \tmp2, c13, c0, 2 @ get the user r/w register
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+ mcrne p15, 0, \tp, c13, c0, 3 @ yes, set TLS register
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+ mcrne p15, 0, \tpuser, c13, c0, 2 @ set user r/w register
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+ strne \tmp2, [\base, #TI_TP_VALUE + 4] @ save it
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.endm
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- .macro set_tls_software, tp, tmp1, tmp2
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+ .macro switch_tls_software, base, tp, tpuser, tmp1, tmp2
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mov \tmp1, #0xffff0fff
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str \tp, [\tmp1, #-15] @ set TLS value at 0xffff0ff0
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.endm
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@@ -31,19 +34,30 @@
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#ifdef CONFIG_TLS_REG_EMUL
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#define tls_emu 1
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#define has_tls_reg 1
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-#define set_tls set_tls_none
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+#define switch_tls switch_tls_none
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#elif defined(CONFIG_CPU_V6)
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#define tls_emu 0
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#define has_tls_reg (elf_hwcap & HWCAP_TLS)
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-#define set_tls set_tls_v6
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+#define switch_tls switch_tls_v6
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#elif defined(CONFIG_CPU_32v6K)
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#define tls_emu 0
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#define has_tls_reg 1
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-#define set_tls set_tls_v6k
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+#define switch_tls switch_tls_v6k
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#else
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#define tls_emu 0
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#define has_tls_reg 0
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-#define set_tls set_tls_software
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+#define switch_tls switch_tls_software
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#endif
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+#ifndef __ASSEMBLY__
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+static inline unsigned long get_tpuser(void)
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+{
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+ unsigned long reg = 0;
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+
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+ if (has_tls_reg && !tls_emu)
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+ __asm__("mrc p15, 0, %0, c13, c0, 2" : "=r" (reg));
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+
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+ return reg;
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+}
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+#endif
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#endif /* __ASMARM_TLS_H */
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diff --git a/arch/arm/kernel/entry-armv.S b/arch/arm/kernel/entry-armv.S
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index 7a8c2d6..0bdba55 100644
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--- a/arch/arm/kernel/entry-armv.S
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+++ b/arch/arm/kernel/entry-armv.S
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@@ -698,15 +698,16 @@ ENTRY(__switch_to)
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UNWIND(.fnstart )
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UNWIND(.cantunwind )
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add ip, r1, #TI_CPU_SAVE
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- ldr r3, [r2, #TI_TP_VALUE]
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ARM( stmia ip!, {r4 - sl, fp, sp, lr} ) @ Store most regs on stack
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THUMB( stmia ip!, {r4 - sl, fp} ) @ Store most regs on stack
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THUMB( str sp, [ip], #4 )
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THUMB( str lr, [ip], #4 )
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+ ldr r4, [r2, #TI_TP_VALUE]
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+ ldr r5, [r2, #TI_TP_VALUE + 4]
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#ifdef CONFIG_CPU_USE_DOMAINS
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ldr r6, [r2, #TI_CPU_DOMAIN]
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#endif
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- set_tls r3, r4, r5
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+ switch_tls r1, r4, r5, r3, r7
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#if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
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ldr r7, [r2, #TI_TASK]
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ldr r8, =__stack_chk_guard
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diff --git a/arch/arm/kernel/process.c b/arch/arm/kernel/process.c
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index 0ff45bd..18e92f6 100644
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--- a/arch/arm/kernel/process.c
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+++ b/arch/arm/kernel/process.c
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@@ -38,6 +38,7 @@
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#include <asm/thread_notify.h>
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#include <asm/stacktrace.h>
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#include <asm/mach/time.h>
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+#include <asm/tls.h>
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#ifdef CONFIG_CC_STACKPROTECTOR
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#include <linux/stackprotector.h>
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@@ -558,7 +559,8 @@ copy_thread(unsigned long clone_flags, unsigned long stack_start,
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clear_ptrace_hw_breakpoint(p);
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if (clone_flags & CLONE_SETTLS)
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- thread->tp_value = regs->ARM_r3;
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+ thread->tp_value[0] = childregs->ARM_r3;
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+ thread->tp_value[1] = get_tpuser();
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thread_notify(THREAD_NOTIFY_COPY, thread);
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diff --git a/arch/arm/kernel/ptrace.c b/arch/arm/kernel/ptrace.c
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index 9650c14..c6c6be7 100644
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--- a/arch/arm/kernel/ptrace.c
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+++ b/arch/arm/kernel/ptrace.c
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@@ -844,7 +844,7 @@ long arch_ptrace(struct task_struct *child, long request,
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#endif
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case PTRACE_GET_THREAD_AREA:
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- ret = put_user(task_thread_info(child)->tp_value,
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+ ret = put_user(task_thread_info(child)->tp_value[0],
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datap);
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break;
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diff --git a/arch/arm/kernel/traps.c b/arch/arm/kernel/traps.c
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index 12e6fcb..e0a066b 100644
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--- a/arch/arm/kernel/traps.c
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+++ b/arch/arm/kernel/traps.c
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@@ -593,7 +593,7 @@ asmlinkage int arm_syscall(int no, struct pt_regs *regs)
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return regs->ARM_r0;
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case NR(set_tls):
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- thread->tp_value = regs->ARM_r0;
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+ thread->tp_value[0] = regs->ARM_r0;
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if (tls_emu)
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return 0;
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if (has_tls_reg) {
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@@ -711,7 +711,7 @@ static int get_tp_trap(struct pt_regs *regs, unsigned int instr)
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int reg = (instr >> 12) & 15;
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if (reg == 15)
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return 1;
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- regs->uregs[reg] = current_thread_info()->tp_value;
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+ regs->uregs[reg] = current_thread_info()->tp_value[0];
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regs->ARM_pc += 4;
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return 0;
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}
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--
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cgit v1.1
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