From 323a28bf14c622bdd1b9ecf09a339b00af98c965 Mon Sep 17 00:00:00 2001 From: Insun Song Date: Wed, 23 Nov 2016 08:29:33 -0800 Subject: [PATCH] net: wireless: bcmdhd: remove PCIe debug IOVAR access delete PCIe debug IOVARs in production build. BUG: 31707909 Signed-off-by: Insun Song Change-Id: Icd659169eeae3e587bec1f5587511a354d482a33 --- drivers/net/wireless/bcmdhd/dhd_pcie.c | 98 ---------------------------------- 1 file changed, 98 deletions(-) diff --git a/drivers/net/wireless/bcmdhd/dhd_pcie.c b/drivers/net/wireless/bcmdhd/dhd_pcie.c index 26201a6d2f39d..c56f789c4797f 100644 --- a/drivers/net/wireless/bcmdhd/dhd_pcie.c +++ b/drivers/net/wireless/bcmdhd/dhd_pcie.c @@ -2609,104 +2609,6 @@ dhdpcie_bus_doiovar(dhd_bus_t *bus, const bcm_iovar_t *vi, uint32 actionid, cons bcmerror = dhdpcie_downloadvars(bus, arg, len); break; - case IOV_SVAL(IOV_PCIEREG): - si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, - int_val); - si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configdata), ~0, - int_val2); - break; - - case IOV_GVAL(IOV_PCIEREG): - si_corereg(bus->sih, bus->sih->buscoreidx, OFFSETOF(sbpcieregs_t, configaddr), ~0, - int_val); - int_val = si_corereg(bus->sih, bus->sih->buscoreidx, - OFFSETOF(sbpcieregs_t, configdata), 0, 0); - bcopy(&int_val, arg, sizeof(int_val)); - break; - - case IOV_GVAL(IOV_BAR0_SECWIN_REG): - { - uint32 cur_base, base; - uchar *bar0; - volatile uint32 *offset; - /* set the bar0 secondary window to this */ - /* write the register value */ - cur_base = dhdpcie_bus_cfg_read_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint)); - base = int_val & 0xFFFFF000; - dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), base); - bar0 = (uchar *)bus->regs; - offset = (uint32 *)(bar0 + 0x4000 + (int_val & 0xFFF)); - int_val = *offset; - bcopy(&int_val, arg, sizeof(int_val)); - dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), cur_base); - } - break; - case IOV_SVAL(IOV_BAR0_SECWIN_REG): - { - uint32 cur_base, base; - uchar *bar0; - volatile uint32 *offset; - /* set the bar0 secondary window to this */ - /* write the register value */ - cur_base = dhdpcie_bus_cfg_read_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint)); - base = int_val & 0xFFFFF000; - dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), base); - bar0 = (uchar *)bus->regs; - offset = (uint32 *)(bar0 + 0x4000 + (int_val & 0xFFF)); - *offset = int_val2; - bcopy(&int_val2, arg, val_size); - dhdpcie_bus_cfg_write_dword(bus, PCIE2_BAR0_CORE2_WIN, sizeof(uint32), cur_base); - } - break; - - case IOV_SVAL(IOV_PCIECOREREG): - si_corereg(bus->sih, bus->sih->buscoreidx, int_val, ~0, int_val2); - break; - case IOV_GVAL(IOV_SBREG): - { - sdreg_t sdreg; - uint32 addr, coreidx; - - bcopy(params, &sdreg, sizeof(sdreg)); - - addr = sdreg.offset; - coreidx = (addr & 0xF000) >> 12; - - int_val = si_corereg(bus->sih, coreidx, (addr & 0xFFF), 0, 0); - bcopy(&int_val, arg, sizeof(int32)); - break; - } - - case IOV_SVAL(IOV_SBREG): - { - sdreg_t sdreg; - uint32 addr, coreidx; - - bcopy(params, &sdreg, sizeof(sdreg)); - - addr = sdreg.offset; - coreidx = (addr & 0xF000) >> 12; - - si_corereg(bus->sih, coreidx, (addr & 0xFFF), ~0, sdreg.value); - - break; - } - - - case IOV_GVAL(IOV_PCIECOREREG): - int_val = si_corereg(bus->sih, bus->sih->buscoreidx, int_val, 0, 0); - bcopy(&int_val, arg, sizeof(int_val)); - break; - - case IOV_SVAL(IOV_PCIECFGREG): - OSL_PCI_WRITE_CONFIG(bus->osh, int_val, 4, int_val2); - break; - - case IOV_GVAL(IOV_PCIECFGREG): - int_val = OSL_PCI_READ_CONFIG(bus->osh, int_val, 4); - bcopy(&int_val, arg, sizeof(int_val)); - break; - case IOV_SVAL(IOV_PCIE_LPBK): bcmerror = dhdpcie_bus_lpback_req(bus, int_val); break;