From 946a09f5411890b1b1ec945b8c882bfa042f4523 Mon Sep 17 00:00:00 2001 From: anarkia1976 Date: Wed, 5 Feb 2014 07:12:48 +0100 Subject: [PATCH] msm: cpu: overclock: use higher bus speed at lower CPU freqs Thanks to @bedalus and @mrg666 Bedalus suggested that if lower CPU frequencies can offer higher bus speed, GPU use during games wouldn't require higher CPU frequency. My testing demonstrated 4C drop in CPU temp during 3DMark benchmark. Still needs to be tested for everyday use. --- arch/arm/mach-msm/acpuclock-8064.c | 172 +++++++++++++++++++------------------ 1 file changed, 88 insertions(+), 84 deletions(-) diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c index 7879be1d564..cd045cf0c97 100644 --- a/arch/arm/mach-msm/acpuclock-8064.c +++ b/arch/arm/mach-msm/acpuclock-8064.c @@ -132,6 +132,14 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = { .name = "acpuclk-8064", }; +#ifdef CONFIG_LOW_CPUCLOCKS +#define L2_BW_MID 6 +#define L2_BW_HIGH 15 +#else +#define L2_BW_MID 5 +#define L2_BW_HIGH 14 +#endif + static struct l2_level l2_freq_tbl[] __initdata = { #ifdef CONFIG_LOW_CPUCLOCKS [0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 }, @@ -175,32 +183,31 @@ static struct acpu_level tbl_slow[] __initdata = { { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 }, { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 }, - //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 }, { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 }, #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 }, #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 }, - { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 }, - { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 }, - { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 }, - { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1075000 }, - { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1075000 }, - { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1100000 }, - { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1100000 }, - { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1125000 }, - { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1125000 }, - { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1175000 }, - { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1175000 }, - { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1200000 }, - { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1200000 }, - { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1225000 }, - { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1225000 }, - { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 }, - { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 }, - { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 }, + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 975000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 975000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 1000000 }, + { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 1000000 }, + { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 1025000 }, + { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 1025000 }, + { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 1075000 }, + { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 1075000 }, + { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1100000 }, + { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1100000 }, + { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1125000 }, + { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1125000 }, + { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1175000 }, + { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1175000 }, + { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1200000 }, + { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1200000 }, + { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1225000 }, + { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1225000 }, + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1237500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1237500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1250000 }, #ifdef CONFIG_CPU_OVERCLOCK { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 }, { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 }, @@ -216,32 +223,31 @@ static struct acpu_level tbl_nom[] __initdata = { { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 }, { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 }, - //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 }, { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 }, #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 }, #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 }, - { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 }, - { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 975000 }, - { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 }, - { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1025000 }, - { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1025000 }, - { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1050000 }, - { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1050000 }, - { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1075000 }, - { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1075000 }, - { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1125000 }, - { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1125000 }, - { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1150000 }, - { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1150000 }, - { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1175000 }, - { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1175000 }, - { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 }, - { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 }, - { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 }, + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 925000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 925000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 950000 }, + { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 950000 }, + { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 975000 }, + { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 975000 }, + { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 1025000 }, + { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 1025000 }, + { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1050000 }, + { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1050000 }, + { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1075000 }, + { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1075000 }, + { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1125000 }, + { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1125000 }, + { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1150000 }, + { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1150000 }, + { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1175000 }, + { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1175000 }, + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1187500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1187500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1200000 }, #ifdef CONFIG_CPU_OVERCLOCK { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 }, { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 }, @@ -257,32 +263,31 @@ static struct acpu_level tbl_fast[] __initdata = { { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, - //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 }, #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 }, - { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 }, - { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 }, - { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 }, - { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 975000 }, - { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 }, - { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1000000 }, - { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 }, - { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1025000 }, - { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1025000 }, - { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1075000 }, - { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 }, - { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1100000 }, - { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1100000 }, - { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1125000 }, - { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 }, - { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 }, - { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 }, - { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 }, + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 }, + { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 900000 }, + { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 925000 }, + { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 925000 }, + { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 975000 }, + { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 975000 }, + { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1000000 }, + { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1000000 }, + { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1025000 }, + { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1025000 }, + { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1075000 }, + { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1075000 }, + { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1100000 }, + { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1100000 }, + { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1125000 }, + { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1125000 }, + { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1137500 }, + { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1137500 }, + { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1150000 }, #ifdef CONFIG_CPU_OVERCLOCK { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 }, { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 }, @@ -298,28 +303,27 @@ static struct acpu_level tbl_faster[] __initdata = { { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 }, { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 }, { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 }, - //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 }, { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 }, #else { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 }, #endif - { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 }, - { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 }, - { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 }, - { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 }, - { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 }, - { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 }, - { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 962500 }, - { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 }, - { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 975000 }, - { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 }, - { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1000000 }, - { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1000000 }, - { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1050000 }, - { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1050000 }, - { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1075000 }, - { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1075000 }, - { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1100000 }, + { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 }, + { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 }, + { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 }, + { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 900000 }, + { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 925000 }, + { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 925000 }, + { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 962500 }, + { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 962500 }, + { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 975000 }, + { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 975000 }, + { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1000000 }, + { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1000000 }, + { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1050000 }, + { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1050000 }, + { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1075000 }, + { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1075000 }, + { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1100000 }, { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1100000 }, { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 }, { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },