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11.0: nex: switch to -user + add disabled overclock
This commit is contained in:
Tad
parent
3a717605d0
commit
c5d2f25797
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@ -0,0 +1,324 @@
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From 4dba87655f582d250574f7e85c28419d54b4bf4f Mon Sep 17 00:00:00 2001
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From: superr <superr@ddayweb.com>
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Date: Fri, 27 Mar 2015 15:39:54 -0500
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Subject: [PATCH 1/3] Add OC
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---
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arch/arm/mach-msm/acpuclock-8930.c | 14 ++++++++++++++
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1 file changed, 14 insertions(+)
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diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
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index 2dfb3dd..0b35c76 100644
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--- a/arch/arm/mach-msm/acpuclock-8930.c
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+++ b/arch/arm/mach-msm/acpuclock-8930.c
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@@ -149,6 +149,8 @@ static struct l2_level l2_freq_tbl[] __initdata = {
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[13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
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[14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
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[15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
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+ [16] = { { 1242000, HFPLL, 1, 0x30 }, LVL_HIGH, 1150000, 7 },
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+ [17] = { { 1296000, HFPLL, 1, 0x32 }, LVL_HIGH, 1150000, 7 },
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{ }
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};
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@@ -169,6 +171,10 @@ static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
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{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
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+ { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
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+ { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1237500 },
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+ { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1250000 },
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+ { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1275000 },
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{ 0, { 0 } }
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};
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@@ -189,6 +195,10 @@ static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
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{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
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+ { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1200000 },
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+ { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1212500 },
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+ { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1225000 },
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+ { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1250000 },
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{ 0, { 0 } }
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};
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@@ -209,6 +219,10 @@ static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
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{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
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+ { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1150000 },
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+ { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1162500 },
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+ { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1175000 },
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+ { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1200000 },
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{ 0, { 0 } }
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};
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--
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1.8.3.1
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From dc06c5c02d0dbe74ffeac7b4ca4fd01b2fdc3627 Mon Sep 17 00:00:00 2001
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From: superr <superr@ddayweb.com>
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Date: Sat, 28 Mar 2015 09:34:32 -0500
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Subject: [PATCH 2/3] OC to 2GHz
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---
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arch/arm/mach-msm/acpuclock-8930.c | 96 ++++++++++++++++++++++++--------------
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1 file changed, 62 insertions(+), 34 deletions(-)
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diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
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index 0b35c76..9067efc 100644
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--- a/arch/arm/mach-msm/acpuclock-8930.c
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+++ b/arch/arm/mach-msm/acpuclock-8930.c
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@@ -123,6 +123,9 @@ static struct msm_bus_paths bw_level_tbl[] __initdata = {
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[5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
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[6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
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[7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
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+ [8] = BW_MBPS(4532), /* At least 566 MHz on bus. */
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+ [9] = BW_MBPS(4624), /* At least 578 MHz on bus. */
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+ [10] = BW_MBPS(4800), /* At least 600 MHz on bus. */
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};
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static struct msm_bus_scale_pdata bus_scale_data __initdata = {
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@@ -133,24 +136,25 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
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};
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static struct l2_level l2_freq_tbl[] __initdata = {
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- [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 },
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- [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
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- [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
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- [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
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- [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
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- [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
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- [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
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- [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
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- [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
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- [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
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- [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 },
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- [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 },
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- [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 },
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- [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
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- [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
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- [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
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- [16] = { { 1242000, HFPLL, 1, 0x30 }, LVL_HIGH, 1150000, 7 },
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- [17] = { { 1296000, HFPLL, 1, 0x32 }, LVL_HIGH, 1150000, 7 },
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+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 }, //133mhz fsb
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+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
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+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
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+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
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+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
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+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 }, //400mhz fsb
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+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 }, //400mhz fsb
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+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 }, //400mhz fsb
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+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 }, //400mhz fsb
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+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 }, //400mhz fsb
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+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
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+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
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+ [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
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+ [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
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+ [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
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+ [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
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+ [16] = { { 1242000, HFPLL, 1, 0x2E }, LVL_HIGH, 1150000, 7 },
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+ [17] = { { 1296000, HFPLL, 1, 0x30 }, LVL_HIGH, 1150000, 7 },
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+ [18] = { { 1350000, HFPLL, 1, 0x32 }, LVL_HIGH, 1150000, 10 }, //600mhz fsb
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{ }
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};
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@@ -171,14 +175,13 @@ static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
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{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
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- { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
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- { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1237500 },
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- { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1250000 },
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- { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1275000 },
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{ 0, { 0 } }
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};
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static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
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+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 },
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+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 },
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+ { 0, { 378000, HFPLL, 2, 0x1C }, L2(0), 925000 },
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{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
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{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
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@@ -193,17 +196,31 @@ static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
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{ 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 },
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
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- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
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- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
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- { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1200000 },
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- { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1212500 },
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- { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1225000 },
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- { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1250000 },
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+ { 0, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
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+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1150000 },
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+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1150000 },
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+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1175000 },
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+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1175000 },
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+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1187500 },
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+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1187500 },
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+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1200000 },
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+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(18), 1225000 },
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+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(18), 1237500 },
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+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(18), 1250000 },
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+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(18), 1267500 },
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+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(18), 1275000 },
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+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(18), 1300000 },
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+ { 1, { 1944000, HFPLL, 1, 0x48 }, L2(18), 1312500 },
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+ { 1, { 1998000, HFPLL, 1, 0x4A }, L2(18), 1325000 },
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+ { 1, { 2052000, HFPLL, 1, 0x4C }, L2(18), 1337500 },
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{ 0, { 0 } }
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};
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static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
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- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
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+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 850000 },
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+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 875000 },
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+ { 0, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 },
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+ { 0, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
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{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 },
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{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
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{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 },
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@@ -218,11 +235,22 @@ static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
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{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
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{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
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{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
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- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
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- { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1150000 },
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- { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1162500 },
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- { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1175000 },
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- { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1200000 },
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+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
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+ { 0, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1125000 },
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+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1125000 },
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+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1125000 },
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+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1137500 },
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+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1137500 },
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+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1150000 },
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+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(18), 1175000 },
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+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(18), 1190000 },
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+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(18), 1200000 },
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+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(18), 1225000 },
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+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(18), 1250000 },
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+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(18), 1275000 },
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+ { 1, { 1944000, HFPLL, 1, 0x48 }, L2(18), 1312500 },
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+ { 1, { 1998000, HFPLL, 1, 0x4A }, L2(18), 1325000 },
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+ { 1, { 2052000, HFPLL, 1, 0x4C }, L2(18), 1337500 },
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{ 0, { 0 } }
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};
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--
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1.8.3.1
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From d11c45b7a335452b8144c5e125d8a10b07f8feb6 Mon Sep 17 00:00:00 2001
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From: Tad <tad@spotco.us>
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Date: Sun, 11 Dec 2016 20:41:35 -0500
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Subject: [PATCH 3/3] Max OC
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Change-Id: I6e2089eb1f8de9200964acd6271649f6af70edfd
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---
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arch/arm/mach-msm/acpuclock-8930.c | 9 +++++----
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arch/arm/mach-msm/acpuclock-krait.c | 2 +-
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arch/arm/mach-msm/board-8930-regulator-pm8038.c | 4 ++--
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arch/arm/mach-msm/board-8930-regulator-pm8917.c | 4 ++--
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4 files changed, 10 insertions(+), 9 deletions(-)
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diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
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index 9067efc..693a254 100644
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--- a/arch/arm/mach-msm/acpuclock-8930.c
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+++ b/arch/arm/mach-msm/acpuclock-8930.c
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@@ -52,7 +52,7 @@ static struct scalable scalable_pm8917[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x4501,
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- .vreg[VREG_CORE] = { "krait0", 1300000 },
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+ .vreg[VREG_CORE] = { "krait0", 1400000 },
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.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
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.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
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.vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
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@@ -64,7 +64,7 @@ static struct scalable scalable_pm8917[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x5501,
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- .vreg[VREG_CORE] = { "krait1", 1300000 },
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+ .vreg[VREG_CORE] = { "krait1", 1400000 },
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.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
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.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
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.vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
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@@ -88,7 +88,7 @@ static struct scalable scalable[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x4501,
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- .vreg[VREG_CORE] = { "krait0", 1300000 },
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+ .vreg[VREG_CORE] = { "krait0", 1400000 },
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.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
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.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
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.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
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@@ -99,7 +99,7 @@ static struct scalable scalable[] __initdata = {
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.aux_clk_sel = 3,
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.sec_clk_sel = 2,
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.l2cpmr_iaddr = 0x5501,
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||||
- .vreg[VREG_CORE] = { "krait1", 1300000 },
|
||||
+ .vreg[VREG_CORE] = { "krait1", 1400000 },
|
||||
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
|
||||
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
|
||||
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
|
||||
@@ -126,6 +126,7 @@ static struct msm_bus_paths bw_level_tbl[] __initdata = {
|
||||
[8] = BW_MBPS(4532), /* At least 566 MHz on bus. */
|
||||
[9] = BW_MBPS(4624), /* At least 578 MHz on bus. */
|
||||
[10] = BW_MBPS(4800), /* At least 600 MHz on bus. */
|
||||
+ [11] = BW_MBPS(5336), /* At least 667 MHz on bus. */
|
||||
};
|
||||
|
||||
static struct msm_bus_scale_pdata bus_scale_data __initdata = {
|
||||
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
|
||||
index f216ee5..cfbf338 100755
|
||||
--- a/arch/arm/mach-msm/acpuclock-krait.c
|
||||
+++ b/arch/arm/mach-msm/acpuclock-krait.c
|
||||
@@ -932,7 +932,7 @@ static void __init bus_init(const struct l2_level *l2_level)
|
||||
}
|
||||
|
||||
#ifdef CONFIG_CPU_FREQ_MSM
|
||||
-static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
|
||||
+static struct cpufreq_frequency_table freq_table[NR_CPUS][53];
|
||||
|
||||
static void __init cpufreq_table_init(void)
|
||||
{
|
||||
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8038.c b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
|
||||
index 4cf0f54..b5a6602 100755
|
||||
--- a/arch/arm/mach-msm/board-8930-regulator-pm8038.c
|
||||
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
|
||||
@@ -541,9 +541,9 @@ msm8930_pm8038_gpio_regulator_pdata[] __devinitdata = {
|
||||
/* SAW regulator constraints */
|
||||
struct regulator_init_data msm8930_pm8038_saw_regulator_core0_pdata =
|
||||
/* ID vreg_name min_uV max_uV */
|
||||
- SAW_VREG_INIT(S5, "8038_s5", 850000, 1300000);
|
||||
+ SAW_VREG_INIT(S5, "8038_s5", 850000, 1400000);
|
||||
struct regulator_init_data msm8930_pm8038_saw_regulator_core1_pdata =
|
||||
- SAW_VREG_INIT(S6, "8038_s6", 850000, 1300000);
|
||||
+ SAW_VREG_INIT(S6, "8038_s6", 850000, 1400000);
|
||||
|
||||
/* PM8038 regulator constraints */
|
||||
struct pm8xxx_regulator_platform_data
|
||||
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8917.c b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
|
||||
index b0dedad..ce3a17f 100644
|
||||
--- a/arch/arm/mach-msm/board-8930-regulator-pm8917.c
|
||||
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
|
||||
@@ -501,9 +501,9 @@ msm8930_pm8917_gpio_regulator_pdata[] __devinitdata = {
|
||||
/* SAW regulator constraints */
|
||||
struct regulator_init_data msm8930_pm8917_saw_regulator_core0_pdata =
|
||||
/* ID vreg_name min_uV max_uV */
|
||||
- SAW_VREG_INIT(S5, "8917_s5", 850000, 1300000);
|
||||
+ SAW_VREG_INIT(S5, "8917_s5", 850000, 1400000);
|
||||
struct regulator_init_data msm8930_pm8917_saw_regulator_core1_pdata =
|
||||
- SAW_VREG_INIT(S6, "8917_s6", 850000, 1300000);
|
||||
+ SAW_VREG_INIT(S6, "8917_s6", 850000, 1400000);
|
||||
|
||||
/* PM8917 regulator constraints */
|
||||
struct pm8xxx_regulator_platform_data
|
||||
--
|
||||
1.8.3.1
|
||||
|
||||
|
|
@ -80,5 +80,9 @@ if enter "kernel/oppo/msm8974"; then
|
|||
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_oppo_msm8974/0001-OverUnderClock-EXTREME.patch"; #300MHz -> 268MHz, 2.45GHz -> 2.95GHz
|
||||
fi;
|
||||
|
||||
if enter "kernel/zte/msm8930-DISABLED"; then
|
||||
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_zte_msm8930/0001-Overclock.patch";
|
||||
fi;
|
||||
|
||||
cd "$DOS_BUILD_BASE";
|
||||
echo "Overclocks applied!";
|
||||
|
|
|
|||
|
|
@ -49,7 +49,7 @@ export -f buildDeviceDebug;
|
|||
buildAll() {
|
||||
if [ "$DOS_MALWARE_SCAN_ENABLED" = true ]; then scanWorkspaceForMalware; fi;
|
||||
#Select devices are userdebug due to SELinux policy issues
|
||||
brunch lineage_nex-userdebug;
|
||||
brunch lineage_nex-user;
|
||||
}
|
||||
export -f buildAll;
|
||||
|
||||
|
|
@ -63,7 +63,6 @@ patchWorkspace() {
|
|||
repopick -it asb-2018.11-cm11 -e 234695;
|
||||
repopick -it cm.service.adb.root; #security fix for -userdebug
|
||||
repopick -it asb-2018.12-cm11;
|
||||
sed -i 's/2018-08-01/2018-12-01/' build/core/version_defaults.mk; #dirty lies! (kinda)
|
||||
|
||||
source "$DOS_SCRIPTS/Patch.sh";
|
||||
source "$DOS_SCRIPTS/Defaults.sh";
|
||||
|
|
|
|||
|
|
@ -71,6 +71,7 @@ enterAndClear "build";
|
|||
sed -i 's/Mms/Silence/' target/product/*.mk; #Replace AOSP Messaging app with Silence
|
||||
sed -i '497i$(LOCAL_INTERMEDIATE_TARGETS) : PRIVATE_AAPT_FLAGS += --auto-add-overlay' core/base_rules.mk;
|
||||
sed -i '80iLOCAL_AAPT_FLAGS += --auto-add-overlay' core/package.mk;
|
||||
sed -i 's/2018-08-01/2018-12-01/' build/core/version_defaults.mk; #XXX: dirty lies! (kinda)
|
||||
|
||||
enterAndClear "external/sqlite";
|
||||
patch -p1 < "$DOS_PATCHES/android_external_sqlite/0001-Secure_Delete.patch"; #Enable secure_delete by default (CopperheadOS-13.0)
|
||||
|
|
|
|||
Loading…
Reference in New Issue
Block a user