Remove msm8992 overclocks

This commit is contained in:
Tad 2018-06-23 00:23:34 -04:00
parent 9c3996bed9
commit af94760587
16 changed files with 0 additions and 1259 deletions

@ -1,307 +0,0 @@
From df33b6042093a177e2ef593f2d271dd33e1e251c Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Tue, 3 Nov 2015 21:21:34 -0500
Subject: [PATCH] msm8992 initial overclocking
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 30 ++++++++++++--------
arch/arm/boot/dts/qcom/msm8992.dtsi | 40 +++++++++++++++++++-------
drivers/clk/qcom/clock-cpu-8994.c | 8 +++---
drivers/cpufreq/qcom-cpufreq.c | 41 +++++++++++++++++++++++++++
4 files changed, 93 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index d5f68601759..23b23ba4e1a 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -605,7 +605,7 @@
regulator-name = "apc0_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <10>;
+ regulator-max-microvolt = <12>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <640000 700000 800000 850000>;
@@ -669,15 +669,15 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1230000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 1 2 2 3 3 4 4 4 4>;
+ qcom,cpr-corner-map = <1 1 2 2 3 3 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 800000 800000 900000 900000
1000000 1000000 1115000 1115000
- 1180000 1180000>;
+ 1180000 1180000 1180000 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 655000 700000 735000
800000 835000 850000 875000
- 950000 1000000>;
+ 950000 1000000 1000000 1000000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 0 0 0 0 0>,
<0 0xffffffff 1 0 0 0 0>,
@@ -759,10 +759,12 @@
<7 864000000>,
<8 960000000>,
<9 1248000000>,
- <10 1440000000>;
+ <10 1440000000>,
+ <11 1536000000>,
+ <12 1632000000>;
qcom,cpr-speed-bin-max-corners =
<0 0 2 4 6 9>,
- <1 0 2 4 6 10>;
+ <1 0 2 4 6 12>;
qcom,cpr-enable;
};
@@ -774,7 +776,7 @@
regulator-name = "apc1_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <15>;
+ regulator-max-microvolt = <17>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <640000 640000 745000 850000>;
@@ -841,17 +843,19 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1230000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4>;
+ qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 900000 900000 900000 900000
900000 1000000 1000000 1000000
1115000 1115000 1115000 1115000
- 1115000 1115000 1180000>;
+ 1115000 1115000 1180000 1180000
+ 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 640000 665000 690000
735000 745000 770000 785000
850000 860000 880000 900000
- 920000 935000 1000000>;
+ 920000 935000 1000000 1000000
+ 1000000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 0 4 4 4 4>,
<0xffffffff 0xffffffff 1 4 4 4 4>,
@@ -908,9 +912,11 @@
<12 1536000000>,
<13 1632000000>,
<14 1689600000>,
- <15 1824000000>;
+ <15 1824000000>,
+ <16 1958400000>,
+ <17 2016000000>;
qcom,cpr-speed-bin-max-corners =
- <0xFFFFFFFF 0 1 5 8 15>;
+ <0xFFFFFFFF 0 1 5 8 17>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 5ba420c5b9c..8892b569694 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -852,7 +852,9 @@
< 787200 3509 >,
< 864000 4173 >,
< 960000 5271 >,
- < 1440000 7102 >;
+ < 1440000 7102 >,
+ < 1536000 7102 >,
+ < 1632000 7102 >;
cpu-to-dev-map-4 =
< 384000 1525 >,
< 633600 2288 >,
@@ -860,16 +862,22 @@
< 864000 4173 >,
< 960000 5271 >,
< 1344000 5928 >,
- < 1824000 7102 >;
+ < 1824000 7102 >,
+ < 1958400 7102 >,
+ < 2016000 7102 >;
};
mincpubw-cpufreq {
target-dev = <&mincpubw>;
cpu-to-dev-map-0 =
- < 1440000 1525 >;
+ < 1440000 1525 >,
+ < 1536000 1525 >,
+ < 1632000 1525 >;
cpu-to-dev-map-4 =
< 1689600 1525 >,
- < 1824000 5928 >;
+ < 1824000 1525 >,
+ < 1958400 1525 >,
+ < 2016000 5928 >;
};
cci-cpufreq {
@@ -880,7 +888,9 @@
< 787200 384000 >,
< 864000 556800 >,
< 960000 729600 >,
- < 1440000 787200 >;
+ < 1440000 787200 >,
+ < 1536000 787200 >,
+ < 1632000 787200 >;
cpu-to-dev-map-4 =
< 384000 134400 >,
< 480000 300000 >,
@@ -888,7 +898,9 @@
< 768000 556800 >,
< 960000 600000 >,
< 1440000 729600 >,
- < 1824000 787200 >;
+ < 1824000 787200 >,
+ < 1958400 787200 >,
+ < 2016000 787200 >;
};
};
@@ -915,7 +927,9 @@
< 864000 >,
< 960000 >,
< 1248000 >,
- < 1440000 >;
+ < 1440000 >,
+ < 1536000 >,
+ < 1632000 >;
qcom,cpufreq-table-4 =
< 384000 >,
@@ -930,7 +944,9 @@
< 1536000 >,
< 1632000 >,
< 1689600 >,
- < 1824000 >;
+ < 1824000 >,
+ < 1958400 >,
+ < 2016000 >;
};
@@ -968,7 +984,9 @@
< 864000000 7>,
< 960000000 8>,
< 1248000000 9>,
- < 1440000000 10>;
+ < 1440000000 10>,
+ < 1536000000 11>,
+ < 1632000000 12>;
qcom,a57-speedbin0-v0 =
< 0 0>,
< 384000000 5>,
@@ -983,7 +1001,9 @@
< 1536000000 12>,
< 1632000000 13>,
< 1689600000 14>,
- < 1824000000 15>;
+ < 1824000000 15>,
+ < 1958400000 16>,
+ < 2016000000 17>;
qcom,cci-speedbin0-v0 =
< 0 0>,
< 134400000 2>,
diff --git a/drivers/clk/qcom/clock-cpu-8994.c b/drivers/clk/qcom/clock-cpu-8994.c
index 7928f2ec0ca..351a66d4469 100644
--- a/drivers/clk/qcom/clock-cpu-8994.c
+++ b/drivers/clk/qcom/clock-cpu-8994.c
@@ -191,13 +191,13 @@ static struct pll_clk a57_pll0 = {
.test_ctl_lo_val = 0x00010000,
},
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll0",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll0.c),
},
};
@@ -229,13 +229,13 @@ static struct pll_clk a57_pll1 = {
/* Necessary since we'll be setting a rate before handoff on V1 */
.src_rate = 19200000,
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll1",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll1.c),
},
};
diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
index e30b0cb7483..dd3a5898597 100644
--- a/drivers/cpufreq/qcom-cpufreq.c
+++ b/drivers/cpufreq/qcom-cpufreq.c
@@ -31,6 +31,40 @@
static DEFINE_MUTEX(l2bw_lock);
+static unsigned long arg_cpu_max_a53 = 1440000;
+
+static int __init cpufreq_read_cpu_max_a53(char *cpu_max_a53)
+{
+ unsigned long ui_khz;
+ int ret;
+
+ ret = kstrtoul(cpu_max_a53, 0, &ui_khz);
+ if (ret)
+ return -EINVAL;
+
+ arg_cpu_max_a53 = ui_khz;
+ printk("cpu_max_a53=%lu\n", arg_cpu_max_a53);
+ return ret;
+}
+__setup("cpu_max_a53=", cpufreq_read_cpu_max_a53);
+
+static unsigned long arg_cpu_max_a57 = 1824000;
+
+static int __init cpufreq_read_cpu_max_a57(char *cpu_max_a57)
+{
+ unsigned long ui_khz;
+ int ret;
+
+ ret = kstrtoul(cpu_max_a57, 0, &ui_khz);
+ if (ret)
+ return -EINVAL;
+
+ arg_cpu_max_a57 = ui_khz;
+ printk("cpu_max_a57=%lu\n", arg_cpu_max_a57);
+ return ret;
+}
+__setup("cpu_max_a57=", cpufreq_read_cpu_max_a57);
+
static struct clk *cpu_clk[NR_CPUS];
static struct clk *l2_clk;
static DEFINE_PER_CPU(struct cpufreq_frequency_table *, freq_table);
@@ -364,6 +398,13 @@ static struct cpufreq_frequency_table *cpufreq_parse_dt(struct device *dev,
if (i > 0 && f <= ftbl[i-1].frequency)
break;
+ //Custom max freq
+ if ((cpu < 4 && f > arg_cpu_max_a53) ||
+ (cpu >= 4 && f > arg_cpu_max_a57)) {
+ nf = i;
+ break;
+ }
+
ftbl[i].driver_data = i;
ftbl[i].frequency = f;
}

@ -1,47 +0,0 @@
From a7d2988f5ec81cd5e456eddba110d0ef1f809e50 Mon Sep 17 00:00:00 2001
From: Dan Sneddon <dsneddon@codeaurora.org>
Date: Fri, 27 Mar 2015 16:02:02 -0600
Subject: [PATCH] ARM: dts: msm: Adjust SPDM params on 8992
The current SPDM parameters cause a power increase
on 8992. This patch adjusts those parameters to
eliminate the negative power impact.
Change-Id: Ibdfaaf4cb50c346b6433a4a7dc910713bce8125f
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
---
arch/arm/boot/dts/qcom/msm8992-bus.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-bus.dtsi b/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
index 3efc2047d4a..e7b83cc11c0 100644
--- a/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
@@ -1516,8 +1516,8 @@
clocks = <&clock_cpu clk_cci_clk>;
qcom,bw-upstep = <1000>;
- qcom,bw-dwnstep = <1000>;
- qcom,max-vote = <10000>;
+ qcom,bw-dwnstep = <5000>;
+ qcom,max-vote = <5000>;
qcom,up-step-multp = <2>;
qcom,spdm-interval = <100>;
@@ -1527,14 +1527,14 @@
qcom,bucket-size = <8>;
/*max pl1 freq, max pl2 freq*/
- qcom,pl-freqs = <140000000 160000000>;
+ qcom,pl-freqs = <280000000 350000000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
qcom,reject-rate = <5000 5000 5000 5000 5000 5000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
qcom,response-time-us = <10000 10000 10000 10000 3000 3000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
- qcom,cci-response-time-us = <10000 10000 10000 10000 1000 1000>;
+ qcom,cci-response-time-us = <10000 10000 10000 10000 3000 3000>;
qcom,max-cci-freq = <787000000>;
};

@ -1,43 +0,0 @@
From a288adcbf6ed14fccaa7726159b01eb9fcd74dc7 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Mon, 21 Nov 2016 21:40:09 -0500
Subject: [PATCH] msm8992: bump oc voltages
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index 23b23ba4e1a..19a3c1ca720 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -673,11 +673,11 @@
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 800000 800000 900000 900000
1000000 1000000 1115000 1115000
- 1180000 1180000 1180000 1180000>;
+ 1180000 1180000 1180000 1200000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 655000 700000 735000
800000 835000 850000 875000
- 950000 1000000 1000000 1000000>;
+ 950000 1000000 1000000 1100000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 0 0 0 0 0>,
<0 0xffffffff 1 0 0 0 0>,
@@ -849,13 +849,13 @@
900000 1000000 1000000 1000000
1115000 1115000 1115000 1115000
1115000 1115000 1180000 1180000
- 1180000>;
+ 1200000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 640000 665000 690000
735000 745000 770000 785000
850000 860000 880000 900000
920000 935000 1000000 1000000
- 1000000>;
+ 1100000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 0 4 4 4 4>,
<0xffffffff 0xffffffff 1 4 4 4 4>,

@ -1,32 +0,0 @@
From 1be9e1c5a09b3645e47a82ca199bf7153b7ffc35 Mon Sep 17 00:00:00 2001
From: Mathieu Maret <mmaret@genymobile.com>
Date: Wed, 4 Nov 2015 15:21:55 +0100
Subject: [PATCH] arm:dt:msm8994 Correct regulator timming
Documentation describe slew-rate as "time in us it takes for the regulator to change votlage value in one step".
2s seems a lot and qpnp-lab-slew-rate is only 5000us.
So correct it as if a 1000 factor was added.
This reduce the kernel boot time of the karin windy by 80s
Tested on karin windy only
Signed-off-by: Mathieu Maret <mmaret@genymobile.com>
Signed-off-by: mydongistiny <jaysonedson@gmail.com>
Signed-off-by: Joe Maples <joe@frap129.org>
---
arch/arm/boot/dts/qcom/msm-pmi8994.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
index 1303ba6a27b..de8259a53a7 100644
--- a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
@@ -459,7 +459,7 @@
qcom,qpnp-ibb-min-voltage = <1400000>;
qcom,qpnp-ibb-step-size = <100000>;
- qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-slew-rate = <2000>;
qcom,qpnp-ibb-use-default-voltage;
qcom,qpnp-ibb-init-voltage = <5500000>;
qcom,qpnp-ibb-init-amoled-voltage = <4000000>;

@ -1,69 +0,0 @@
From 2368a976be94becdac216b4a09919010fd78b7cb Mon Sep 17 00:00:00 2001
From: Andrew Miyaguchi <XDleader555@gmail.com>
Date: Fri, 28 Jul 2017 16:34:20 -0700
Subject: [PATCH] arm/dts: msm8992: Add clock-frequency property
This commit will remove the following error message at boot
[0.062725,0] /cpus/cpu@0: Missing clock-frequency property
[0.062741,0] /cpus/cpu@1: Missing clock-frequency property
[0.062754,0] /cpus/cpu@2: Missing clock-frequency property
[0.062768,0] /cpus/cpu@3: Missing clock-frequency property
[0.062783,0] /cpus/cpu@4: Missing clock-frequency property
[0.062798,0] /cpus/cpu@5: Missing clock-frequency property
---
arch/arm/boot/dts/qcom/msm8992.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 38998c1b538..da44d9c5c61 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -75,6 +75,7 @@
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x0>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc0>;
@@ -110,6 +111,7 @@
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x1>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc1>;
@@ -139,6 +141,7 @@
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x2>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc2>;
@@ -168,6 +171,7 @@
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x3>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc3>;
@@ -197,6 +201,7 @@
CPU4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a57";
+ clock-frequency = <1824000000>;
reg = <0x100>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc4>;
@@ -236,6 +241,7 @@
CPU5: cpu@5 {
device_type = "cpu";
compatible = "arm,cortex-a57";
+ clock-frequency = <1824000000>;
reg = <0x101>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc5>;

@ -1,32 +0,0 @@
From 813c7c2c64746a1960274b4d1d6277ca01350c67 Mon Sep 17 00:00:00 2001
From: Francisco Franco <franciscofranco.1990@gmail.com>
Date: Thu, 6 Jul 2017 13:02:58 +0000
Subject: [PATCH] bullhead: don't hotplug the perf cluster on BCL event, it
destroys performance and don't throttle so hard
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
---
arch/arm/boot/dts/qcom/msm8992.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index da44d9c5c61..9ecfb89ebbe 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -2754,13 +2754,13 @@
compatible = "qcom,bcl";
qcom,bcl-enable;
qcom,bcl-framework-interface;
- qcom,bcl-hotplug-list = <&CPU4 &CPU5>;
+ /delete-property/ qcom,bcl-hotplug-list;
+ /delete-property/ qcom,bcl-soc-hotplug-list;
qcom,bcl-freq-control-list = <&CPU4 &CPU5>;
- qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5>;
qcom,ibat-monitor {
qcom,low-threshold-uamp = <3400000>;
qcom,high-threshold-uamp = <4200000>;
- qcom,mitigation-freq-khz = <768000>;
+ qcom,mitigation-freq-khz = <960000>;
qcom,vph-high-threshold-uv = <3500000>;
qcom,vph-low-threshold-uv = <3300000>;
qcom,soc-low-threshold = <10>;

@ -1,79 +0,0 @@
From c1f428064fed404f1e2271dda76ac98fcb0f714f Mon Sep 17 00:00:00 2001
From: Andrew Miyaguchi <XDleader555@gmail.com>
Date: Thu, 4 Jan 2018 01:32:30 -0800
Subject: [PATCH] ARM: dts: msm: add support for 302MHz on both A53/A57
Minimalistic edit without touching CCI frequencies
Also update regulator so voltage requests aren't rejected
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 6 +++---
arch/arm/boot/dts/qcom/msm8992.dtsi | 4 ++++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index 506a4542c50..20085cb75b5 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -549,7 +549,7 @@
compatible = "qcom,spm-regulator";
reg = <0x2900 0x100>;
regulator-name = "pm8994_s8";
- regulator-min-microvolt = <700000>;
+ regulator-min-microvolt = <640000>;
regulator-max-microvolt = <1180000>;
qcom,cpu-num = <0>;
};
@@ -750,7 +750,7 @@
qcom,cpr-voltage-scaling-factor-max = <0 0 2000 2000>;
qcom,cpr-quot-adjust-scaling-factor-max = <0 2000 2000 2000>;
qcom,cpr-corner-frequency-map =
- <1 300000000>,
+ <1 302400000>,
<2 384000000>,
<3 460800000>,
<4 600000000>,
@@ -899,7 +899,7 @@
qcom,cpr-quot-adjust-scaling-factor-max = <0 0 2000 2000>;
qcom,cpr-corner-frequency-map =
<1 300000000>, /* SVS Fmin for "SVS2" */
- <2 300000000>,
+ <2 302400000>,
<3 384000000>,
<4 480000000>,
<5 633600000>,
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 2f1c4399f19..7be0fa258ec 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -923,6 +923,7 @@
qcom,governor-per-policy;
qcom,cpufreq-table-0 =
+ < 302400 >,
< 384000 >,
< 460800 >,
< 600000 >,
@@ -936,6 +937,7 @@
< 1632000 >;
qcom,cpufreq-table-4 =
+ < 302400 >,
< 384000 >,
< 480000 >,
< 633600 >,
@@ -980,6 +982,7 @@
< 1248000000 9>;
qcom,a53-speedbin1-v0 =
< 0 0>,
+ < 302400000 1>,
< 384000000 2>,
< 460800000 3>,
< 600000000 4>,
@@ -993,6 +996,7 @@
< 1632000000 12>;
qcom,a57-speedbin0-v0 =
< 0 0>,
+ < 302400000 5>,
< 384000000 5>,
< 480000000 5>,
< 633600000 5>,

@ -1,307 +0,0 @@
From df33b6042093a177e2ef593f2d271dd33e1e251c Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Tue, 3 Nov 2015 21:21:34 -0500
Subject: [PATCH] msm8992 initial overclocking
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 30 ++++++++++++--------
arch/arm/boot/dts/qcom/msm8992.dtsi | 40 +++++++++++++++++++-------
drivers/clk/qcom/clock-cpu-8994.c | 8 +++---
drivers/cpufreq/qcom-cpufreq.c | 41 +++++++++++++++++++++++++++
4 files changed, 93 insertions(+), 26 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index d5f68601759..23b23ba4e1a 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -605,7 +605,7 @@
regulator-name = "apc0_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <10>;
+ regulator-max-microvolt = <12>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <640000 700000 800000 850000>;
@@ -669,15 +669,15 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1230000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 1 2 2 3 3 4 4 4 4>;
+ qcom,cpr-corner-map = <1 1 2 2 3 3 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 800000 800000 900000 900000
1000000 1000000 1115000 1115000
- 1180000 1180000>;
+ 1180000 1180000 1180000 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 655000 700000 735000
800000 835000 850000 875000
- 950000 1000000>;
+ 950000 1000000 1000000 1000000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 0 0 0 0 0>,
<0 0xffffffff 1 0 0 0 0>,
@@ -759,10 +759,12 @@
<7 864000000>,
<8 960000000>,
<9 1248000000>,
- <10 1440000000>;
+ <10 1440000000>,
+ <11 1536000000>,
+ <12 1632000000>;
qcom,cpr-speed-bin-max-corners =
<0 0 2 4 6 9>,
- <1 0 2 4 6 10>;
+ <1 0 2 4 6 12>;
qcom,cpr-enable;
};
@@ -774,7 +776,7 @@
regulator-name = "apc1_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <15>;
+ regulator-max-microvolt = <17>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <640000 640000 745000 850000>;
@@ -841,17 +843,19 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1230000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4>;
+ qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 900000 900000 900000 900000
900000 1000000 1000000 1000000
1115000 1115000 1115000 1115000
- 1115000 1115000 1180000>;
+ 1115000 1115000 1180000 1180000
+ 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 640000 665000 690000
735000 745000 770000 785000
850000 860000 880000 900000
- 920000 935000 1000000>;
+ 920000 935000 1000000 1000000
+ 1000000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 0 4 4 4 4>,
<0xffffffff 0xffffffff 1 4 4 4 4>,
@@ -908,9 +912,11 @@
<12 1536000000>,
<13 1632000000>,
<14 1689600000>,
- <15 1824000000>;
+ <15 1824000000>,
+ <16 1958400000>,
+ <17 2016000000>;
qcom,cpr-speed-bin-max-corners =
- <0xFFFFFFFF 0 1 5 8 15>;
+ <0xFFFFFFFF 0 1 5 8 17>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 5ba420c5b9c..8892b569694 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -852,7 +852,9 @@
< 787200 3509 >,
< 864000 4173 >,
< 960000 5271 >,
- < 1440000 7102 >;
+ < 1440000 7102 >,
+ < 1536000 7102 >,
+ < 1632000 7102 >;
cpu-to-dev-map-4 =
< 384000 1525 >,
< 633600 2288 >,
@@ -860,16 +862,22 @@
< 864000 4173 >,
< 960000 5271 >,
< 1344000 5928 >,
- < 1824000 7102 >;
+ < 1824000 7102 >,
+ < 1958400 7102 >,
+ < 2016000 7102 >;
};
mincpubw-cpufreq {
target-dev = <&mincpubw>;
cpu-to-dev-map-0 =
- < 1440000 1525 >;
+ < 1440000 1525 >,
+ < 1536000 1525 >,
+ < 1632000 1525 >;
cpu-to-dev-map-4 =
< 1689600 1525 >,
- < 1824000 5928 >;
+ < 1824000 1525 >,
+ < 1958400 1525 >,
+ < 2016000 5928 >;
};
cci-cpufreq {
@@ -880,7 +888,9 @@
< 787200 384000 >,
< 864000 556800 >,
< 960000 729600 >,
- < 1440000 787200 >;
+ < 1440000 787200 >,
+ < 1536000 787200 >,
+ < 1632000 787200 >;
cpu-to-dev-map-4 =
< 384000 134400 >,
< 480000 300000 >,
@@ -888,7 +898,9 @@
< 768000 556800 >,
< 960000 600000 >,
< 1440000 729600 >,
- < 1824000 787200 >;
+ < 1824000 787200 >,
+ < 1958400 787200 >,
+ < 2016000 787200 >;
};
};
@@ -915,7 +927,9 @@
< 864000 >,
< 960000 >,
< 1248000 >,
- < 1440000 >;
+ < 1440000 >,
+ < 1536000 >,
+ < 1632000 >;
qcom,cpufreq-table-4 =
< 384000 >,
@@ -930,7 +944,9 @@
< 1536000 >,
< 1632000 >,
< 1689600 >,
- < 1824000 >;
+ < 1824000 >,
+ < 1958400 >,
+ < 2016000 >;
};
@@ -968,7 +984,9 @@
< 864000000 7>,
< 960000000 8>,
< 1248000000 9>,
- < 1440000000 10>;
+ < 1440000000 10>,
+ < 1536000000 11>,
+ < 1632000000 12>;
qcom,a57-speedbin0-v0 =
< 0 0>,
< 384000000 5>,
@@ -983,7 +1001,9 @@
< 1536000000 12>,
< 1632000000 13>,
< 1689600000 14>,
- < 1824000000 15>;
+ < 1824000000 15>,
+ < 1958400000 16>,
+ < 2016000000 17>;
qcom,cci-speedbin0-v0 =
< 0 0>,
< 134400000 2>,
diff --git a/drivers/clk/qcom/clock-cpu-8994.c b/drivers/clk/qcom/clock-cpu-8994.c
index 7928f2ec0ca..351a66d4469 100644
--- a/drivers/clk/qcom/clock-cpu-8994.c
+++ b/drivers/clk/qcom/clock-cpu-8994.c
@@ -191,13 +191,13 @@ static struct pll_clk a57_pll0 = {
.test_ctl_lo_val = 0x00010000,
},
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll0",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll0.c),
},
};
@@ -229,13 +229,13 @@ static struct pll_clk a57_pll1 = {
/* Necessary since we'll be setting a rate before handoff on V1 */
.src_rate = 19200000,
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll1",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll1.c),
},
};
diff --git a/drivers/cpufreq/qcom-cpufreq.c b/drivers/cpufreq/qcom-cpufreq.c
index e30b0cb7483..dd3a5898597 100644
--- a/drivers/cpufreq/qcom-cpufreq.c
+++ b/drivers/cpufreq/qcom-cpufreq.c
@@ -31,6 +31,40 @@
static DEFINE_MUTEX(l2bw_lock);
+static unsigned long arg_cpu_max_a53 = 1440000;
+
+static int __init cpufreq_read_cpu_max_a53(char *cpu_max_a53)
+{
+ unsigned long ui_khz;
+ int ret;
+
+ ret = kstrtoul(cpu_max_a53, 0, &ui_khz);
+ if (ret)
+ return -EINVAL;
+
+ arg_cpu_max_a53 = ui_khz;
+ printk("cpu_max_a53=%lu\n", arg_cpu_max_a53);
+ return ret;
+}
+__setup("cpu_max_a53=", cpufreq_read_cpu_max_a53);
+
+static unsigned long arg_cpu_max_a57 = 1824000;
+
+static int __init cpufreq_read_cpu_max_a57(char *cpu_max_a57)
+{
+ unsigned long ui_khz;
+ int ret;
+
+ ret = kstrtoul(cpu_max_a57, 0, &ui_khz);
+ if (ret)
+ return -EINVAL;
+
+ arg_cpu_max_a57 = ui_khz;
+ printk("cpu_max_a57=%lu\n", arg_cpu_max_a57);
+ return ret;
+}
+__setup("cpu_max_a57=", cpufreq_read_cpu_max_a57);
+
static struct clk *cpu_clk[NR_CPUS];
static struct clk *l2_clk;
static DEFINE_PER_CPU(struct cpufreq_frequency_table *, freq_table);
@@ -364,6 +398,13 @@ static struct cpufreq_frequency_table *cpufreq_parse_dt(struct device *dev,
if (i > 0 && f <= ftbl[i-1].frequency)
break;
+ //Custom max freq
+ if ((cpu < 4 && f > arg_cpu_max_a53) ||
+ (cpu >= 4 && f > arg_cpu_max_a57)) {
+ nf = i;
+ break;
+ }
+
ftbl[i].driver_data = i;
ftbl[i].frequency = f;
}

@ -1,47 +0,0 @@
From a7d2988f5ec81cd5e456eddba110d0ef1f809e50 Mon Sep 17 00:00:00 2001
From: Dan Sneddon <dsneddon@codeaurora.org>
Date: Fri, 27 Mar 2015 16:02:02 -0600
Subject: [PATCH] ARM: dts: msm: Adjust SPDM params on 8992
The current SPDM parameters cause a power increase
on 8992. This patch adjusts those parameters to
eliminate the negative power impact.
Change-Id: Ibdfaaf4cb50c346b6433a4a7dc910713bce8125f
Signed-off-by: Dan Sneddon <dsneddon@codeaurora.org>
---
arch/arm/boot/dts/qcom/msm8992-bus.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-bus.dtsi b/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
index 3efc2047d4a..e7b83cc11c0 100644
--- a/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-bus.dtsi
@@ -1516,8 +1516,8 @@
clocks = <&clock_cpu clk_cci_clk>;
qcom,bw-upstep = <1000>;
- qcom,bw-dwnstep = <1000>;
- qcom,max-vote = <10000>;
+ qcom,bw-dwnstep = <5000>;
+ qcom,max-vote = <5000>;
qcom,up-step-multp = <2>;
qcom,spdm-interval = <100>;
@@ -1527,14 +1527,14 @@
qcom,bucket-size = <8>;
/*max pl1 freq, max pl2 freq*/
- qcom,pl-freqs = <140000000 160000000>;
+ qcom,pl-freqs = <280000000 350000000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
qcom,reject-rate = <5000 5000 5000 5000 5000 5000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
qcom,response-time-us = <10000 10000 10000 10000 3000 3000>;
/* pl1 low, pl1 high, pl2 low, pl2 high, pl3 low, pl3 high */
- qcom,cci-response-time-us = <10000 10000 10000 10000 1000 1000>;
+ qcom,cci-response-time-us = <10000 10000 10000 10000 3000 3000>;
qcom,max-cci-freq = <787000000>;
};

@ -1,43 +0,0 @@
From a288adcbf6ed14fccaa7726159b01eb9fcd74dc7 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Mon, 21 Nov 2016 21:40:09 -0500
Subject: [PATCH] msm8992: bump oc voltages
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index 23b23ba4e1a..19a3c1ca720 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -673,11 +673,11 @@
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 800000 800000 900000 900000
1000000 1000000 1115000 1115000
- 1180000 1180000 1180000 1180000>;
+ 1180000 1180000 1180000 1200000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 655000 700000 735000
800000 835000 850000 875000
- 950000 1000000 1000000 1000000>;
+ 950000 1000000 1000000 1100000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 0 0 0 0 0>,
<0 0xffffffff 1 0 0 0 0>,
@@ -849,13 +849,13 @@
900000 1000000 1000000 1000000
1115000 1115000 1115000 1115000
1115000 1115000 1180000 1180000
- 1180000>;
+ 1200000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 640000 640000 665000 690000
735000 745000 770000 785000
850000 860000 880000 900000
920000 935000 1000000 1000000
- 1000000>;
+ 1100000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 0 4 4 4 4>,
<0xffffffff 0xffffffff 1 4 4 4 4>,

@ -1,32 +0,0 @@
From 1be9e1c5a09b3645e47a82ca199bf7153b7ffc35 Mon Sep 17 00:00:00 2001
From: Mathieu Maret <mmaret@genymobile.com>
Date: Wed, 4 Nov 2015 15:21:55 +0100
Subject: [PATCH] arm:dt:msm8994 Correct regulator timming
Documentation describe slew-rate as "time in us it takes for the regulator to change votlage value in one step".
2s seems a lot and qpnp-lab-slew-rate is only 5000us.
So correct it as if a 1000 factor was added.
This reduce the kernel boot time of the karin windy by 80s
Tested on karin windy only
Signed-off-by: Mathieu Maret <mmaret@genymobile.com>
Signed-off-by: mydongistiny <jaysonedson@gmail.com>
Signed-off-by: Joe Maples <joe@frap129.org>
---
arch/arm/boot/dts/qcom/msm-pmi8994.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
index 1303ba6a27b..de8259a53a7 100644
--- a/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
+++ b/arch/arm/boot/dts/qcom/msm-pmi8994.dtsi
@@ -459,7 +459,7 @@
qcom,qpnp-ibb-min-voltage = <1400000>;
qcom,qpnp-ibb-step-size = <100000>;
- qcom,qpnp-ibb-slew-rate = <2000000>;
+ qcom,qpnp-ibb-slew-rate = <2000>;
qcom,qpnp-ibb-use-default-voltage;
qcom,qpnp-ibb-init-voltage = <5500000>;
qcom,qpnp-ibb-init-amoled-voltage = <4000000>;

@ -1,69 +0,0 @@
From 2368a976be94becdac216b4a09919010fd78b7cb Mon Sep 17 00:00:00 2001
From: Andrew Miyaguchi <XDleader555@gmail.com>
Date: Fri, 28 Jul 2017 16:34:20 -0700
Subject: [PATCH] arm/dts: msm8992: Add clock-frequency property
This commit will remove the following error message at boot
[0.062725,0] /cpus/cpu@0: Missing clock-frequency property
[0.062741,0] /cpus/cpu@1: Missing clock-frequency property
[0.062754,0] /cpus/cpu@2: Missing clock-frequency property
[0.062768,0] /cpus/cpu@3: Missing clock-frequency property
[0.062783,0] /cpus/cpu@4: Missing clock-frequency property
[0.062798,0] /cpus/cpu@5: Missing clock-frequency property
---
arch/arm/boot/dts/qcom/msm8992.dtsi | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 38998c1b538..da44d9c5c61 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -75,6 +75,7 @@
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x0>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc0>;
@@ -110,6 +111,7 @@
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x1>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc1>;
@@ -139,6 +141,7 @@
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x2>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc2>;
@@ -168,6 +171,7 @@
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53";
+ clock-frequency = <1440000000>;
reg = <0x3>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc3>;
@@ -197,6 +201,7 @@
CPU4: cpu@4 {
device_type = "cpu";
compatible = "arm,cortex-a57";
+ clock-frequency = <1824000000>;
reg = <0x100>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc4>;
@@ -236,6 +241,7 @@
CPU5: cpu@5 {
device_type = "cpu";
compatible = "arm,cortex-a57";
+ clock-frequency = <1824000000>;
reg = <0x101>;
enable-method = "qcom,8994-arm-cortex-acc";
qcom,acc = <&acc5>;

@ -1,32 +0,0 @@
From 813c7c2c64746a1960274b4d1d6277ca01350c67 Mon Sep 17 00:00:00 2001
From: Francisco Franco <franciscofranco.1990@gmail.com>
Date: Thu, 6 Jul 2017 13:02:58 +0000
Subject: [PATCH] bullhead: don't hotplug the perf cluster on BCL event, it
destroys performance and don't throttle so hard
Signed-off-by: Francisco Franco <franciscofranco.1990@gmail.com>
---
arch/arm/boot/dts/qcom/msm8992.dtsi | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index da44d9c5c61..9ecfb89ebbe 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -2754,13 +2754,13 @@
compatible = "qcom,bcl";
qcom,bcl-enable;
qcom,bcl-framework-interface;
- qcom,bcl-hotplug-list = <&CPU4 &CPU5>;
+ /delete-property/ qcom,bcl-hotplug-list;
+ /delete-property/ qcom,bcl-soc-hotplug-list;
qcom,bcl-freq-control-list = <&CPU4 &CPU5>;
- qcom,bcl-soc-hotplug-list = <&CPU4 &CPU5>;
qcom,ibat-monitor {
qcom,low-threshold-uamp = <3400000>;
qcom,high-threshold-uamp = <4200000>;
- qcom,mitigation-freq-khz = <768000>;
+ qcom,mitigation-freq-khz = <960000>;
qcom,vph-high-threshold-uv = <3500000>;
qcom,vph-low-threshold-uv = <3300000>;
qcom,soc-low-threshold = <10>;

@ -1,79 +0,0 @@
From c1f428064fed404f1e2271dda76ac98fcb0f714f Mon Sep 17 00:00:00 2001
From: Andrew Miyaguchi <XDleader555@gmail.com>
Date: Thu, 4 Jan 2018 01:32:30 -0800
Subject: [PATCH] ARM: dts: msm: add support for 302MHz on both A53/A57
Minimalistic edit without touching CCI frequencies
Also update regulator so voltage requests aren't rejected
---
arch/arm/boot/dts/qcom/msm8992-regulator.dtsi | 6 +++---
arch/arm/boot/dts/qcom/msm8992.dtsi | 4 ++++
2 files changed, 7 insertions(+), 3 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
index 506a4542c50..20085cb75b5 100644
--- a/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992-regulator.dtsi
@@ -549,7 +549,7 @@
compatible = "qcom,spm-regulator";
reg = <0x2900 0x100>;
regulator-name = "pm8994_s8";
- regulator-min-microvolt = <700000>;
+ regulator-min-microvolt = <640000>;
regulator-max-microvolt = <1180000>;
qcom,cpu-num = <0>;
};
@@ -750,7 +750,7 @@
qcom,cpr-voltage-scaling-factor-max = <0 0 2000 2000>;
qcom,cpr-quot-adjust-scaling-factor-max = <0 2000 2000 2000>;
qcom,cpr-corner-frequency-map =
- <1 300000000>,
+ <1 302400000>,
<2 384000000>,
<3 460800000>,
<4 600000000>,
@@ -899,7 +899,7 @@
qcom,cpr-quot-adjust-scaling-factor-max = <0 0 2000 2000>;
qcom,cpr-corner-frequency-map =
<1 300000000>, /* SVS Fmin for "SVS2" */
- <2 300000000>,
+ <2 302400000>,
<3 384000000>,
<4 480000000>,
<5 633600000>,
diff --git a/arch/arm/boot/dts/qcom/msm8992.dtsi b/arch/arm/boot/dts/qcom/msm8992.dtsi
index 2f1c4399f19..7be0fa258ec 100644
--- a/arch/arm/boot/dts/qcom/msm8992.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8992.dtsi
@@ -923,6 +923,7 @@
qcom,governor-per-policy;
qcom,cpufreq-table-0 =
+ < 302400 >,
< 384000 >,
< 460800 >,
< 600000 >,
@@ -936,6 +937,7 @@
< 1632000 >;
qcom,cpufreq-table-4 =
+ < 302400 >,
< 384000 >,
< 480000 >,
< 633600 >,
@@ -980,6 +982,7 @@
< 1248000000 9>;
qcom,a53-speedbin1-v0 =
< 0 0>,
+ < 302400000 1>,
< 384000000 2>,
< 460800000 3>,
< 600000000 4>,
@@ -993,6 +996,7 @@
< 1632000000 12>;
qcom,a57-speedbin0-v0 =
< 0 0>,
+ < 302400000 5>,
< 384000000 5>,
< 480000000 5>,
< 633600000 5>,

@ -29,24 +29,8 @@ patch -p1 < "$patches/android_kernel_amazon_hdx-common/0004-Overclock.patch";
enter "kernel/lge/hammerhead";
patch -p1 < "$patches/android_kernel_lge_hammerhead/0001-Overclock.patch"; #2.26Ghz -> 2.95Ghz =+2.76Ghz XXX: Untested!
enter "kernel/lge/msm8992";
patch -p1 < "$patches/android_kernel_common_msm8992/0001-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0003-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0004-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0005-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0006-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0007-Overclock.patch";
enter "kernel/motorola/msm8916";
patch -p1 < "$patches/android_kernel_motorola_msm8916/0001-Overclock.patch"; #1.36Ghz -> 1.88Ghz =+ 2.07Ghz
enter "kernel/motorola/msm8992";
patch -p1 < "$patches/android_kernel_common_msm8992/0001-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0003-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0004-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0005-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0006-Overclock.patch";
patch -p1 < "$patches/android_kernel_common_msm8992/0007-Overclock.patch";
cd "$base";
echo "Overclocks applied!";

@ -23,15 +23,6 @@ echo "Applying overclocks...";
enter "kernel/huawei/angler";
patch -p1 < "$patches""android_kernel_huawei_angler/0001-Overclock.patch";
enter "kernel/lge/bullhead";
patch -p1 < "$patches""android_kernel_common_msm8992/0001-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0002-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0003-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0004-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0005-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0006-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0007-Overclock.patch";
enter "kernel/lge/g3";
patch -p1 < "$patches""android_kernel_lge_g3/0001-Overclock.patch"; #2.45Ghz -> 2.76Ghz =+1.24Ghz
patch -p1 < "$patches""android_kernel_lge_g3/0002-Overclock.patch";
@ -51,25 +42,9 @@ echo "CONFIG_LOW_CPUCLOCKS=y" >> arch/arm/configs/lineageos_mako_defconfig; #384
echo "CONFIG_CPU_OVERCLOCK=y" >> arch/arm/configs/lineageos_mako_defconfig; #1.51Ghz -> 1.70Ghz =+0.90Ghz
#echo "CPU_OVERCLOCK_ULTRA=y" >> arch/arm/configs/lineageos_mako_defconfig; #1.51Ghz -> 1.94Ghz =+1.72Ghz XXX: Causes excessive throttling
#enter "kernel/lge/msm8992";
#patch -p1 < "$patches""android_kernel_common_msm8992/0001-Overclock.patch";
#patch -p1 < "$patches""android_kernel_common_msm8992/0003-Overclock.patch";
#patch -p1 < "$patches""android_kernel_common_msm8992/0004-Overclock.patch";
#patch -p1 < "$patches""android_kernel_common_msm8992/0005-Overclock.patch";
#patch -p1 < "$patches""android_kernel_common_msm8992/0006-Overclock.patch";
#patch -p1 < "$patches""android_kernel_common_msm8992/0007-Overclock.patch";
#enter "kernel/motorola/msm8916";
#patch -p1 < "$patches""android_kernel_motorola_msm8916/0001-Overclock.patch"; #1.36Ghz -> 1.88Ghz =+ 2.07Ghz
enter "kernel/nextbit/msm8992";
patch -p1 < "$patches""android_kernel_common_msm8992/0001-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0003-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0004-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0005-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0006-Overclock.patch";
patch -p1 < "$patches""android_kernel_common_msm8992/0007-Overclock.patch";
enter "kernel/oppo/msm8974";
patch -p1 < "$patches""android_kernel_oppo_msm8974/0001-OverUnderClock-EXTREME.patch"; #300Mhz -> 268Mhz, 2.45Ghz -> 2.95Ghz =+2.02Ghz XXX: Not 100% stable under intense workloads