Git-Mirrors/DivestOS
1
0
Fork 0
mirror of https://github.com/Divested-Mobile/DivestOS-Build.git synced 2024-12-24 06:59:27 -05:00
Code Issues Packages Projects Releases Wiki Activity

Drop support for overclocking

Browse Source 
These patches have been disabled for years.
This commit is contained in:
Tad 2021-03-20 16:23:38 -04:00
parent 293c386322
commit add30db605
29 changed files with 0 additions and 5215 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
LICENSE
View File

@ -13,7 +13,6 @@ Patches/
android_kernel_* - GPLv2
[Everything Else] - Apache-2.0
Linux - See COPYING included (GPLv2)
Overclocks - GPLv2
Wallpapers - See LICENSE included (Unsplash)
PrebuiltApps - See LICENSE included
Scripts - GPLv3

56
Patches/Overclocks/android_kernel_amazon_hdx-common/0001-Overclock.patch
View File

@ -1,56 +0,0 @@
From 8b2ae0d4d7012ae908ec2c4d6439d9225818766a Mon Sep 17 00:00:00 2001
From: Paul Reioux <reioux@gmail.com>
Date: Wed, 5 Mar 2014 19:23:12 -0600
Subject: [PATCH] msm8974-regulator.dtsi: further reduce CPU retention voltage
this should help idel drain during processor retention c-state
Signed-off-by: Paul Reioux <reioux@gmail.com>
---
arch/arm/boot/dts/msm8974-regulator.dtsi | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974-regulator.dtsi b/arch/arm/boot/dts/msm8974-regulator.dtsi
index daefbadcb49..cd2da20691f 100644
--- a/arch/arm/boot/dts/msm8974-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974-regulator.dtsi
@@ -480,7 +480,8 @@
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
qcom,headroom-voltage = <150000>;
- qcom,retention-voltage = <675000>;
+ /* reduce retention voltage */
+ qcom,retention-voltage = <600000>;
qcom,ldo-default-voltage = <750000>;
qcom,ldo-threshold-voltage = <850000>;
qcom,ldo-delta-voltage = <50000>;
@@ -496,7 +497,8 @@
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
qcom,headroom-voltage = <150000>;
- qcom,retention-voltage = <675000>;
+ /* reduce retention voltage */
+ qcom,retention-voltage = <600000>;
qcom,ldo-default-voltage = <750000>;
qcom,ldo-threshold-voltage = <850000>;
qcom,ldo-delta-voltage = <50000>;
@@ -512,7 +514,8 @@
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
qcom,headroom-voltage = <150000>;
- qcom,retention-voltage = <675000>;
+ /* reduce retention voltage */
+ qcom,retention-voltage = <600000>;
qcom,ldo-default-voltage = <750000>;
qcom,ldo-threshold-voltage = <850000>;
qcom,ldo-delta-voltage = <50000>;
@@ -528,7 +531,8 @@
regulator-min-microvolt = <500000>;
regulator-max-microvolt = <1100000>;
qcom,headroom-voltage = <150000>;
- qcom,retention-voltage = <675000>;
+ /* reduce retention voltage */
+ qcom,retention-voltage = <600000>;
qcom,ldo-default-voltage = <750000>;
qcom,ldo-threshold-voltage = <850000>;
qcom,ldo-delta-voltage = <50000>;

105
Patches/Overclocks/android_kernel_amazon_hdx-common/0002-Overclock.patch
View File

@ -1,105 +0,0 @@
From d726de1fcf43edea54ddc4cfcf524025205aed30 Mon Sep 17 00:00:00 2001
From: Omar Einea <eineao@gmail.com>
Date: Wed, 11 Feb 2015 11:35:23 +0400
Subject: [PATCH] dts: msm8974: Add CPU overclocking upto 2.41 GHz
Thanks to faux123, DooMLoRD & Androguide
Signed-off-by: Omar Einea <eineao@gmail.com>
---
arch/arm/boot/dts/msm8974.dtsi | 30 ++++++++++++++++++++++--------
1 file changed, 22 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index db2191e9765..bd9798de95a 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1424,7 +1424,9 @@
< 2035200000 1030000 596 >,
< 2112000000 1045000 627 >,
< 2188800000 1060000 659 >,
- < 2265600000 1075000 691 >;
+ < 2265600000 1075000 691 >,
+ < 2342400000 1100000 714 >,
+ < 2419200000 1125000 738 >;
qcom,speed1-pvs1-bin-v0 =
< 0 0 0 >,
@@ -1454,7 +1456,9 @@
< 2035200000 1005000 596 >,
< 2112000000 1020000 627 >,
< 2188800000 1035000 659 >,
- < 2265600000 1050000 691 >;
+ < 2265600000 1050000 691 >,
+ < 2342400000 1075000 714 >,
+ < 2419200000 1100000 738 >;
qcom,speed1-pvs2-bin-v0 =
< 0 0 0 >,
@@ -1484,7 +1488,9 @@
< 2035200000 980000 596 >,
< 2112000000 995000 627 >,
< 2188800000 1010000 659 >,
- < 2265600000 1025000 691 >;
+ < 2265600000 1025000 691 >,
+ < 2342400000 1050000 714 >,
+ < 2419200000 1075000 738 >;
qcom,speed1-pvs3-bin-v0 =
< 0 0 0 >,
@@ -1514,7 +1520,9 @@
< 2035200000 960000 596 >,
< 2112000000 970000 627 >,
< 2188800000 985000 659 >,
- < 2265600000 1000000 691 >;
+ < 2265600000 1000000 691 >,
+ < 2342400000 1025000 714 >,
+ < 2419200000 1050000 738 >;
qcom,speed1-pvs4-bin-v0 =
< 0 0 0 >,
@@ -1544,7 +1552,9 @@
< 2035200000 935000 596 >,
< 2112000000 950000 627 >,
< 2188800000 960000 659 >,
- < 2265600000 975000 691 >;
+ < 2265600000 975000 691 >,
+ < 2342400000 1000000 714 >,
+ < 2419200000 1025000 738 >;
qcom,speed1-pvs5-bin-v0 =
< 0 0 0 >,
@@ -1574,7 +1584,9 @@
< 2035200000 915000 596 >,
< 2112000000 930000 627 >,
< 2188800000 940000 659 >,
- < 2265600000 950000 691 >;
+ < 2265600000 950000 691 >,
+ < 2342400000 975000 714 >,
+ < 2419200000 1000000 738 >;
qcom,speed1-pvs6-bin-v0 =
< 0 0 0 >,
@@ -1604,7 +1616,9 @@
< 2035200000 895000 596 >,
< 2112000000 905000 627 >,
< 2188800000 915000 659 >,
- < 2265600000 925000 691 >;
+ < 2265600000 925000 691 >,
+ < 2342400000 950000 714 >,
+ < 2419200000 975000 738 >;
};
qcom,cpubw {
@@ -1647,7 +1661,7 @@
< 1728000 1651200 6103 >,
< 1958400 1728000 7102 >,
< 2265600 1728000 7102 >,
- < 2457600 1728000 7102 >;
+ < 2419200 1728000 7102 >;
};
usb3: qcom,ssusb@f9200000 {
--
2.15.1

80
Patches/Overclocks/android_kernel_amazon_hdx-common/0003-Overclock.patch
View File

@ -1,80 +0,0 @@
From 7ed2132140ebf5c552e3f4db43cec085eebb73ae Mon Sep 17 00:00:00 2001
From: Omar Einea <eineao@gmail.com>
Date: Thu, 12 Feb 2015 13:15:33 +0400
Subject: [PATCH] dts: msm8974: allow CPU underclocking to 268.8 Mhz
Thanks to CoolDevelopment
Signed-off-by: Omar Einea <eineao@gmail.com>
---
arch/arm/boot/dts/msm8974.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 25f191c44b4..01731c11efa 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1337,6 +1337,7 @@
qcom,speed1-pvs0-bin-v0 =
< 0 0 0 >,
+ < 268800000 770000 65 >,
< 300000000 775000 72 >,
< 345600000 775000 83 >,
< 422400000 775000 101 >,
@@ -1369,6 +1370,7 @@
qcom,speed1-pvs1-bin-v0 =
< 0 0 0 >,
+ < 268800000 770000 65 >,
< 300000000 775000 72 >,
< 345600000 775000 83 >,
< 422400000 775000 101 >,
@@ -1401,6 +1403,7 @@
qcom,speed1-pvs2-bin-v0 =
< 0 0 0 >,
+ < 268800000 745000 65 >,
< 300000000 750000 72 >,
< 345600000 750000 83 >,
< 422400000 750000 101 >,
@@ -1433,6 +1436,7 @@
qcom,speed1-pvs3-bin-v0 =
< 0 0 0 >,
+ < 268800000 745000 65 >,
< 300000000 750000 72 >,
< 345600000 750000 83 >,
< 422400000 750000 101 >,
@@ -1465,6 +1469,7 @@
qcom,speed1-pvs4-bin-v0 =
< 0 0 0 >,
+ < 268800000 745000 65 >,
< 300000000 750000 72 >,
< 345600000 750000 83 >,
< 422400000 750000 101 >,
@@ -1497,6 +1502,7 @@
qcom,speed1-pvs5-bin-v0 =
< 0 0 0 >,
+ < 268800000 720000 65 >,
< 300000000 725000 72 >,
< 345600000 725000 83 >,
< 422400000 725000 101 >,
@@ -1529,6 +1535,7 @@
qcom,speed1-pvs6-bin-v0 =
< 0 0 0 >,
+ < 268800000 720000 65 >,
< 300000000 725000 72 >,
< 345600000 725000 83 >,
< 422400000 725000 101 >,
@@ -1586,6 +1593,7 @@
reg = <0 4>;
compatible = "qcom,msm-cpufreq";
qcom,cpufreq-table =
+ < 268800 268800 381 >,
< 300000 300000 572 >,
< 422400 422400 1144 >,
< 652800 499200 1525 >,

26
Patches/Overclocks/android_kernel_amazon_hdx-common/0004-Overclock.patch
View File

@ -1,26 +0,0 @@
From 0306bd6028b3198fd69c8051acaa518614199dbf Mon Sep 17 00:00:00 2001
From: Omar Einea <eineao@gmail.com>
Date: Sat, 14 Feb 2015 12:45:11 +0400
Subject: [PATCH] dts: msm8974: Use 2.34 GHz and 2.11 GHz CPU freq steps
Thanks to Androguide
Signed-off-by: Omar Einea <eineao@gmail.com>
---
arch/arm/boot/dts/msm8974.dtsi | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 01731c11efa..213e7af1efc 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1607,7 +1607,9 @@
< 1574400 1574400 6103 >,
< 1728000 1651200 6103 >,
< 1958400 1728000 7102 >,
+ < 2112000 1728000 7102 >,
< 2265600 1728000 7102 >,
+ < 2342400 1728000 7102 >,
< 2419200 1728000 7102 >;
};

336
Patches/Overclocks/android_kernel_asus_grouper/0001-Overclock.patch
View File

@ -1,336 +0,0 @@
From b557b85341913b39dc667a48ea52451bb5b0a75e Mon Sep 17 00:00:00 2001
From: faux123 <reioux@gmail.com>
Date: Sun, 29 Jul 2012 00:22:34 -0700
Subject: [PATCH 1/5] Overclocking: enable CPU overclocking
this is done via speedo id hax by forcing Nexus 7 Tegra3 to identify as
AP33 variant instead of as T33
---
arch/arm/mach-tegra/Kconfig | 7 +++++++
arch/arm/mach-tegra/tegra3_speedo.c | 15 +++++++++++++++
2 files changed, 22 insertions(+)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 37d3f11cdd5..a4159c60eeb 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -700,6 +700,13 @@ config TEGRA_PLLM_RESTRICTED
disabled, PLLM is used as a clock source with no restrictions (which
may effectively increase lower limit for core voltage).
+config TEGRA_CPU_OVERCLOCK
+ bool "Tegra3 CPU Overclocking"
+ depends on ARCH_TEGRA_3x_SOC
+ default n
+ help
+ Tegra3 CPU overclocking
+
config TEGRA_WDT_RECOVERY
bool "Enable suspend/resume watchdog recovery mechanism"
default n
diff --git a/arch/arm/mach-tegra/tegra3_speedo.c b/arch/arm/mach-tegra/tegra3_speedo.c
index d9a3bbbe99e..b7a3142ebe6 100644
--- a/arch/arm/mach-tegra/tegra3_speedo.c
+++ b/arch/arm/mach-tegra/tegra3_speedo.c
@@ -246,9 +246,16 @@ static void rev_sku_to_speedo_ids(int rev, int sku)
case 0x83: /* T30L or T30S */
switch (package_id) {
case 1: /* MID => T30L */
+#ifdef CONFIG_TEGRA_CPU_OVERCLOCK
+ /* fake it to behave as AP33 variant */
+ cpu_speedo_id = 4;
+ soc_speedo_id = 1;
+ threshold_index = 7;
+#else
cpu_speedo_id = 7;
soc_speedo_id = 1;
threshold_index = 10;
+#endif
break;
case 2: /* DSC => T30S */
cpu_speedo_id = 3;
@@ -445,7 +452,11 @@ void tegra_init_speedo_data(void)
break;
}
}
+#if CONFIG_TEGRA_CPU_OVERCLOCK
+ cpu_process_id = 3; /* fake it to behave as AP33 cpu variant 3 */
+#else
cpu_process_id = iv -1;
+#endif
if (cpu_process_id == -1) {
pr_err("****************************************************");
@@ -465,7 +476,11 @@ void tegra_init_speedo_data(void)
break;
}
}
+#if CONFIG_TEGRA_CPU_OVERCLOCK
+ core_process_id = 1; /* fake it to behave as AP33 core variant 1 */
+#else
core_process_id = iv -1;
+#endif
if (core_process_id == -1) {
pr_err("****************************************************");
--
2.18.0
From 39e22197dc10a0d53dbfe646b33976f93d572492 Mon Sep 17 00:00:00 2001
From: faux123 <reioux@gmail.com>
Date: Fri, 3 Aug 2012 21:50:57 -0700
Subject: [PATCH 2/5] Overclocking: GPU overclocking from 416MHz to 520Mhz
---
arch/arm/mach-tegra/Kconfig | 7 +++++++
arch/arm/mach-tegra/tegra3_dvfs.c | 14 ++++++++++++++
2 files changed, 21 insertions(+)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index a4159c60eeb..92cab1a6049 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -707,6 +707,13 @@ config TEGRA_CPU_OVERCLOCK
help
Tegra3 CPU overclocking
+config TEGRA_GPU_OVERCLOCK
+ bool "Tegra3 GPU Overclocking"
+ depends on ARCH_TEGRA_3x_SOC
+ default n
+ help
+ Tegra3 GPU overclocking
+
config TEGRA_WDT_RECOVERY
bool "Enable suspend/resume watchdog recovery mechanism"
default n
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 2f2f09edf57..84c47aa11af 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -290,6 +290,15 @@ static struct dvfs core_dvfs_table[] = {
CORE_DVFS("vi", 2, 1, KHZ, 1, 219000, 267000, 300000, 371000, 409000, 425000, 425000, 425000),
CORE_DVFS("vi", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 470000, 470000, 470000),
+#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
+ CORE_DVFS("vde", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+ CORE_DVFS("mpe", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+ CORE_DVFS("2d", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+ CORE_DVFS("epp", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+ CORE_DVFS("3d", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+ CORE_DVFS("3d2", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+ CORE_DVFS("se", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+#else
CORE_DVFS("vde", 0, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
CORE_DVFS("mpe", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
CORE_DVFS("2d", 0, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
@@ -297,6 +306,7 @@ static struct dvfs core_dvfs_table[] = {
CORE_DVFS("3d", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
CORE_DVFS("3d2", 0, 1, KHZ, 1, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
CORE_DVFS("se", 0, 1, KHZ, 1, 267000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
+#endif
CORE_DVFS("vde", 1, 1, KHZ, 200000, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
CORE_DVFS("mpe", 1, 1, KHZ, 200000, 234000, 285000, 332000, 380000, 416000, 416000, 416000, 416000),
@@ -327,7 +337,11 @@ static struct dvfs core_dvfs_table[] = {
CORE_DVFS("host1x", 2, 1, KHZ, 100000, 152000, 188000, 222000, 254000, 267000, 267000, 267000, 300000),
CORE_DVFS("host1x", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 242000, 242000, 242000),
+#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
+ CORE_DVFS("cbus", 1, 1, KHZ, 1, 247000, 304000, 400000, 484000, 520000, 520000, 520000, 520000),
+#else
CORE_DVFS("cbus", 0, 1, KHZ, 1, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
+#endif
CORE_DVFS("cbus", 1, 1, KHZ, 200000, 228000, 275000, 332000, 380000, 416000, 416000, 416000, 416000),
CORE_DVFS("cbus", 2, 1, KHZ, 200000, 247000, 304000, 352000, 400000, 437000, 484000, 520000, 600000),
CORE_DVFS("cbus", 3, 1, KHZ, 1, 1, 1, 1, 1, 1, 484000, 484000, 484000),
--
2.18.0
From 014b0edd51cb109bb83e9fe6729c039bf641919c Mon Sep 17 00:00:00 2001
From: faux123 <reioux@gmail.com>
Date: Sat, 4 Aug 2012 14:30:44 -0700
Subject: [PATCH 3/5] Overclock: add ultimate edition to allow quadcore up to
1.55 GHz
Also add Tegra3 Gaming Fix to disallow 1 single core to have higher
frequecy than rest
---
arch/arm/mach-tegra/Kconfig | 14 ++++++++++++++
arch/arm/mach-tegra/edp.c | 11 +++++++++++
arch/arm/mach-tegra/tegra3_dvfs.c | 5 ++++-
3 files changed, 29 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 92cab1a6049..b82662df89c 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -707,6 +707,13 @@ config TEGRA_CPU_OVERCLOCK
help
Tegra3 CPU overclocking
+config TEGRA_CPU_OVERCLOCK_ULTIMATE
+ bool "Tegra3 CPU Overclocking Ultimate"
+ depends on ARCH_TEGRA_3x_SOC && TEGRA_CPU_OVERCLOCK
+ default n
+ help
+ Tegra3 CPU overclocking Ultimate edition
+
config TEGRA_GPU_OVERCLOCK
bool "Tegra3 GPU Overclocking"
depends on ARCH_TEGRA_3x_SOC
@@ -714,6 +721,13 @@ config TEGRA_GPU_OVERCLOCK
help
Tegra3 GPU overclocking
+config TEGRA_GAMING_FIX
+ bool "Tegra3 Gaming Fix"
+ depends on ARCH_TEGRA_3x_SOC
+ default n
+ help
+ Tegra3 Quadcore Gaming Fix
+
config TEGRA_WDT_RECOVERY
bool "Enable suspend/resume watchdog recovery mechanism"
default n
diff --git a/arch/arm/mach-tegra/edp.c b/arch/arm/mach-tegra/edp.c
index 713853637a5..8a5e3566088 100644
--- a/arch/arm/mach-tegra/edp.c
+++ b/arch/arm/mach-tegra/edp.c
@@ -778,10 +778,21 @@ static int __init init_cpu_edp_limits_lookup(void)
for (j = 0; j < edp_limits_size; j++) {
e[j].temperature = (int)t[i+j].temperature;
+#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
+ e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]+5) * 10000;
+ e[j].freq_limits[1] = (unsigned int)(t[i+j].freq_limits[1]+15) * 10000;
+ e[j].freq_limits[2] = (unsigned int)(t[i+j].freq_limits[2]+15) * 10000;
+ e[j].freq_limits[3] = (unsigned int)(t[i+j].freq_limits[3]+15) * 10000;
+#else
+#ifdef CONFIG_TEGRA_GAMING_FIX
+ e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]-10) * 10000;
+#else
e[j].freq_limits[0] = (unsigned int)t[i+j].freq_limits[0]*10000;
+#endif
e[j].freq_limits[1] = (unsigned int)t[i+j].freq_limits[1]*10000;
e[j].freq_limits[2] = (unsigned int)t[i+j].freq_limits[2]*10000;
e[j].freq_limits[3] = (unsigned int)t[i+j].freq_limits[3]*10000;
+#endif
}
if (edp_limits != edp_default_limits)
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 84c47aa11af..23b472742c2 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -199,8 +199,11 @@ static struct dvfs cpu_dvfs_table[] = {
CPU_DVFS("cpu_g", 4, 0, MHZ, 1, 1, 1, 1, 460, 460, 460, 550, 550, 550, 550, 680, 680, 680, 680, 680, 680, 680, 820, 820, 970, 970, 970, 1040, 1040, 1080, 1080, 1150, 1150, 1200, 1200, 1240, 1240, 1280, 1280, 1320, 1320, 1360, 1360, 1500),
CPU_DVFS("cpu_g", 4, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1360, 1360, 1400, 1400, 1500),
CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1340, 1340, 1380, 1380, 1500),
+#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
+ CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1550, 1550, 1600),
+#else
CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1500),
-
+#endif
CPU_DVFS("cpu_g", 5, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1470, 1470, 1500, 1500, 1500, 1500, 1540, 1540, 1700),
CPU_DVFS("cpu_g", 5, 4, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 940, 940, 940, 940, 940, 940, 940, 1160, 1160, 1240, 1240, 1240, 1280, 1280, 1360, 1360, 1390, 1390, 1470, 1470, 1500, 1500, 1520, 1520, 1520, 1520, 1590, 1700),
--
2.18.0
From bd6e9cb668affd03706557566ec1694941ec16d4 Mon Sep 17 00:00:00 2001
From: faux123 <reioux@gmail.com>
Date: Wed, 29 Aug 2012 23:11:22 -0700
Subject: [PATCH 4/5] overclock: boost ultimate from 1.55 quad to 1.6 quad
also boost the dot pixel clock from 68MHz to 85MHz
---
arch/arm/mach-tegra/board-grouper-panel.c | 4 ++++
arch/arm/mach-tegra/edp.c | 8 ++++----
arch/arm/mach-tegra/tegra3_dvfs.c | 2 +-
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-tegra/board-grouper-panel.c b/arch/arm/mach-tegra/board-grouper-panel.c
index 44e00674dfc..a2ffaf7ab24 100644
--- a/arch/arm/mach-tegra/board-grouper-panel.c
+++ b/arch/arm/mach-tegra/board-grouper-panel.c
@@ -219,7 +219,11 @@ static struct resource grouper_disp1_resources[] = {
static struct tegra_dc_mode grouper_panel_modes[] = {
{
/* 1280x800@60Hz */
+#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
.pclk = 68000000,
+#else
+ .pclk = 85000000,
+#endif
.h_ref_to_sync = 1,
.v_ref_to_sync = 1,
.h_sync_width = 24,
diff --git a/arch/arm/mach-tegra/edp.c b/arch/arm/mach-tegra/edp.c
index 8a5e3566088..bd37f9de86e 100644
--- a/arch/arm/mach-tegra/edp.c
+++ b/arch/arm/mach-tegra/edp.c
@@ -779,10 +779,10 @@ static int __init init_cpu_edp_limits_lookup(void)
for (j = 0; j < edp_limits_size; j++) {
e[j].temperature = (int)t[i+j].temperature;
#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
- e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]+5) * 10000;
- e[j].freq_limits[1] = (unsigned int)(t[i+j].freq_limits[1]+15) * 10000;
- e[j].freq_limits[2] = (unsigned int)(t[i+j].freq_limits[2]+15) * 10000;
- e[j].freq_limits[3] = (unsigned int)(t[i+j].freq_limits[3]+15) * 10000;
+ e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]+10) * 10000;
+ e[j].freq_limits[1] = (unsigned int)(t[i+j].freq_limits[1]+20) * 10000;
+ e[j].freq_limits[2] = (unsigned int)(t[i+j].freq_limits[2]+20) * 10000;
+ e[j].freq_limits[3] = (unsigned int)(t[i+j].freq_limits[3]+20) * 10000;
#else
#ifdef CONFIG_TEGRA_GAMING_FIX
e[j].freq_limits[0] = (unsigned int)(t[i+j].freq_limits[0]-10) * 10000;
diff --git a/arch/arm/mach-tegra/tegra3_dvfs.c b/arch/arm/mach-tegra/tegra3_dvfs.c
index 23b472742c2..9af43c1adb7 100644
--- a/arch/arm/mach-tegra/tegra3_dvfs.c
+++ b/arch/arm/mach-tegra/tegra3_dvfs.c
@@ -200,7 +200,7 @@ static struct dvfs cpu_dvfs_table[] = {
CPU_DVFS("cpu_g", 4, 1, MHZ, 1, 1, 1, 1, 480, 480, 480, 650, 650, 650, 650, 780, 780, 780, 780, 780, 780, 780, 990, 990, 1040, 1040, 1040, 1100, 1100, 1200, 1200, 1250, 1250, 1300, 1300, 1330, 1330, 1360, 1360, 1400, 1400, 1500),
CPU_DVFS("cpu_g", 4, 2, MHZ, 1, 1, 1, 1, 520, 520, 520, 700, 700, 700, 700, 860, 860, 860, 860, 860, 860, 860, 1050, 1050, 1150, 1150, 1150, 1200, 1200, 1280, 1280, 1300, 1300, 1340, 1340, 1380, 1380, 1500),
#ifdef CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE
- CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1550, 1550, 1600),
+ CPU_DVFS("cpu_g", 4, 3, MHZ, 550, 550, 770, 770, 910, 910, 1150, 1230, 1280, 1330, 1370, 1400, 1470, 1500, 1500, 1550, 1600, 1700),
#else
CPU_DVFS("cpu_g", 4, 3, MHZ, 1, 1, 1, 1, 550, 550, 550, 770, 770, 770, 770, 910, 910, 910, 910, 910, 910, 910, 1150, 1150, 1230, 1230, 1230, 1280, 1280, 1330, 1330, 1370, 1370, 1400, 1400, 1500),
#endif
--
2.18.0
From 54fa5d91acc795e7818d522bacf1767bfc7a3b8c Mon Sep 17 00:00:00 2001
From: faux123 <reioux@gmail.com>
Date: Tue, 4 Sep 2012 19:22:55 -0700
Subject: [PATCH 5/5] board/panel: remove pclk boost (causing screen tearing)
---
arch/arm/mach-tegra/board-grouper-panel.c | 4 ----
1 file changed, 4 deletions(-)
diff --git a/arch/arm/mach-tegra/board-grouper-panel.c b/arch/arm/mach-tegra/board-grouper-panel.c
index a2ffaf7ab24..44e00674dfc 100644
--- a/arch/arm/mach-tegra/board-grouper-panel.c
+++ b/arch/arm/mach-tegra/board-grouper-panel.c
@@ -219,11 +219,7 @@ static struct resource grouper_disp1_resources[] = {
static struct tegra_dc_mode grouper_panel_modes[] = {
{
/* 1280x800@60Hz */
-#ifdef CONFIG_TEGRA_GPU_OVERCLOCK
.pclk = 68000000,
-#else
- .pclk = 85000000,
-#endif
.h_ref_to_sync = 1,
.v_ref_to_sync = 1,
.h_sync_width = 24,
--
2.18.0

424
Patches/Overclocks/android_kernel_huawei_angler/0001-Overclock.patch
View File

@ -1,424 +0,0 @@
From e6fbf9568b5cfa91d9aa1006da1a799bd34f0c8f Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Tue, 3 Nov 2015 23:24:01 -0500
Subject: [PATCH] msm8994 overclocking
---
arch/arm/boot/dts/qcom/msm8994-regulator.dtsi | 172 +++++++++++++-------------
arch/arm/boot/dts/qcom/msm8994-v2.dtsi | 40 ++++--
drivers/clk/qcom/clock-cpu-8994.c | 8 +-
3 files changed, 122 insertions(+), 98 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi
index 93c9c647d9b..c245a55182f 100644
--- a/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8994-regulator.dtsi
@@ -606,7 +606,7 @@
regulator-name = "apc0_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <13>;
+ regulator-max-microvolt = <15>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1180000>;
qcom,cpr-voltage-floor = <700000 700000 780000 835000>;
@@ -666,17 +666,17 @@
qcom,cpr-init-voltage-ref = <800000 900000 1000000 1225000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 2 2 2 3 3 3 4 4 4 4 4 4>;
+ qcom,cpr-corner-map = <1 2 2 2 3 3 3 4 4 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0xFFFFFFFF 0 900000 900000 900000 900000
1000000 1000000 1000000 1115000
1115000 1180000 1180000 1180000
- 1180000>;
+ 1180000 1180000 1180000>;
qcom,cpr-voltage-floor-override =
<0xFFFFFFFF 0 700000 700000 700000 725000
780000 800000 825000 835000
850000 915000 970000 980000
- 1000000>;
+ 1000000 1000000 1000000>;
qcom,cpr-fuse-version-map =
<0xffffffff 0xffffffff 1 0 0 0 0>,
@@ -716,9 +716,11 @@
<10 1248000000>,
<11 1344000000>,
<12 1478400000>,
- <13 1555200000>;
+ <13 1555200000>,
+ <14 1632000000>,
+ <15 1708800000>;
qcom,cpr-speed-bin-max-corners =
- <0xFFFFFFFF 0 1 4 7 13>;
+ <0xFFFFFFFF 0 1 4 7 15>;
qcom,cpr-enable;
};
@@ -730,7 +732,7 @@
regulator-name = "apc1_corner";
qcom,cpr-fuse-corners = <4>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <17>;
+ regulator-max-microvolt = <19>;
qcom,cpr-voltage-ceiling = <900000 900000 1000000 1225000>;
qcom,cpr-voltage-floor = <700000 700000 750000 835000>;
@@ -792,25 +794,25 @@
qcom,cpr-init-voltage-ref = <900000 900000 1000000 1225000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4 4 4>;
+ qcom,cpr-corner-map = <1 2 2 2 2 3 3 3 4 4 4 4 4 4 4 4 4 4 4>;
qcom,cpr-voltage-ceiling-override =
<0 0 900000 900000 900000 900000 900000
1000000 1000000 1000000 1160000 1160000
1160000 1160000 1160000 1225000 1225000
- 1225000 1225000>,
+ 1225000 1225000 1225000 1225000>,
<1 0 900000 900000 900000 900000 900000
1000000 1000000 1000000 1160000 1160000
1160000 1160000 1160000 1225000 1225000
- 1225000 1225000>;
+ 1225000 1225000 1225000 1225000>;
qcom,cpr-voltage-floor-override =
<0 0 700000 700000 700000 700000 725000
750000 775000 795000 835000 860000
880000 895000 915000 935000 945000
- 950000 980000>,
+ 950000 980000 980000 980000>,
<1 0 700000 700000 700000 700000 725000
750000 775000 795000 835000 860000
880000 895000 915000 935000 945000
- 950000 980000>;
+ 950000 980000 980000 980000>;
qcom,cpr-fuse-version-map =
<0 0xffffffff 1 6 6 6 6>,
@@ -848,90 +850,90 @@
qcom,cpr-cpus = <&CPU4 &CPU5 &CPU6 &CPU7>;
qcom,cpr-online-cpu-virtual-corner-init-voltage-adjustment =
/* 1st fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 2nd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 3rd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 4th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 5th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 6th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 7th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) >, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) >, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10000) (-10000) (-10000) (-15000) (-15000) (-20000) 0 (-20000) (-30000) (-30000) (-30000) >, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-5000) (-5000) (-5000) (-5000) (-5000) (-10000) 0 (-10000) (-10000) (-10000) (-10000) >, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
qcom,cpr-online-cpu-virtual-corner-quotient-adjustment =
/* 1st fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6) (-6) (-6)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 2nd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-6) (-6) (-6) (-9) (-9) (-12) 0 (-12) (-18) (-18) (-18)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-3) (-3) (-3) (-3) (-3) (-6) 0 (-6) (-6) (-6) (-6)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 3rd fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 4th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 5th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 6th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 4 CPUs online */
/* 7th fuse version tuple matched */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 0 CPUs online */
- <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63)>, /* 1 CPUs online */
- <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21)>, /* 2 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
- <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 0 CPUs online */
+ <0 0 0 0 0 0 0 0 (-21) (-21) (-21) (-31) (-31) (-42) 0 (-42) (-63) (-63) (-63)>, /* 1 CPUs online */
+ <0 0 0 0 0 0 0 0 (-10) (-10) (-10) (-10) (-10) (-21) 0 (-21) (-21) (-21) (-21)>, /* 2 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>, /* 3 CPUs online */
+ <0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0>; /* 4 CPUs online */
qcom,cpr-online-cpu-init-voltage-as-ceiling;
qcom,cpr-voltage-scaling-factor-max = <0 0 2000 2000>;
@@ -953,9 +955,11 @@
<14 1728000000>,
<15 1766400000>,
<16 1824000000>,
- <17 1958400000>;
+ <17 1958400000>,
+ <18 2016000000>,
+ <19 2054400000>;
qcom,cpr-speed-bin-max-corners =
- <0 0 1 5 8 17>,
+ <0 0 1 5 8 19>,
<1 0 1 5 8 15>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/qcom/msm8994-v2.dtsi b/arch/arm/boot/dts/qcom/msm8994-v2.dtsi
index add83045413..3fea4251dfc 100644
--- a/arch/arm/boot/dts/qcom/msm8994-v2.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8994-v2.dtsi
@@ -83,7 +83,9 @@
< 1248000000 10>,
< 1344000000 11>,
< 1478400000 12>,
- < 1555200000 13>;
+ < 1555200000 13>,
+ < 1632000000 14>,
+ < 1708800000 15>;
qcom,a57-speedbin0-v0 =
< 0 0>,
< 384000000 5>,
@@ -99,7 +101,9 @@
< 1632000000 13>,
< 1728000000 14>,
< 1824000000 16>,
- < 1958400000 17>;
+ < 1958400000 17>,
+ < 2016000000 18>,
+ < 2054400000 19>;
qcom,a57-speedbin1-v0 =
< 0 0>,
< 384000000 5>,
@@ -146,7 +150,9 @@
< 1248000 >,
< 1344000 >,
< 1478400 >,
- < 1555200 >;
+ < 1555200 >,
+ < 1632000 >,
+ < 1708800 >;
qcom,cpufreq-table-4 =
< 384000 >,
@@ -162,7 +168,9 @@
< 1632000 >,
< 1728000 >,
< 1824000 >,
- < 1958400 >;
+ < 1958400 >,
+ < 2016000 >,
+ < 2054400 >;
};
&devfreq_cpufreq {
@@ -178,7 +186,9 @@
< 1248000 7904 >,
< 1344000 9887 >,
< 1478400 11863 >,
- < 1555200 11863 >;
+ < 1555200 11863 >,
+ < 1632000 11863 >,
+ < 1708800 11863 >;
cpu-to-dev-map-4 =
< 384000 1525 >,
< 480000 2288 >,
@@ -193,7 +203,9 @@
< 1632000 9887 >,
< 1728000 9887 >,
< 1824000 11863 >,
- < 1958400 11863 >;
+ < 1958400 11863 >,
+ < 2016000 11863 >,
+ < 2054400 11863 >;
};
mincpubw-cpufreq {
@@ -209,7 +221,9 @@
< 1248000 1525 >,
< 1344000 1525 >,
< 1478400 1525 >,
- < 1555200 1525 >;
+ < 1555200 1525 >,
+ < 1632000 1525 >,
+ < 1708800 1525 >;
cpu-to-dev-map-4 =
< 384000 1525 >,
< 480000 1525 >,
@@ -224,7 +238,9 @@
< 1632000 1525 >,
< 1728000 1525 >,
< 1824000 1525 >,
- < 1958400 7904 >;
+ < 1958400 7904 >,
+ < 2016000 7904 >,
+ < 2054400 7904 >;
};
cci-cpufreq {
@@ -239,7 +255,9 @@
< 1248000 729600 >,
< 1344000 787200 >,
< 1478400 787200 >,
- < 1555200 787200 >;
+ < 1555200 787200 >,
+ < 1632000 787200 >,
+ < 1708800 787200 >;
cpu-to-dev-map-4 =
< 384000 300000 >,
< 480000 300000 >,
@@ -254,7 +272,9 @@
< 1632000 787200 >,
< 1728000 787200 >,
< 1824000 787200 >,
- < 1958400 787200 >;
+ < 1958400 787200 >,
+ < 2016000 787200 >,
+ < 2054400 787200 >;
};
};
diff --git a/drivers/clk/qcom/clock-cpu-8994.c b/drivers/clk/qcom/clock-cpu-8994.c
index 7928f2ec0ca..351a66d4469 100644
--- a/drivers/clk/qcom/clock-cpu-8994.c
+++ b/drivers/clk/qcom/clock-cpu-8994.c
@@ -191,13 +191,13 @@ static struct pll_clk a57_pll0 = {
.test_ctl_lo_val = 0x00010000,
},
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll0",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll0.c),
},
};
@@ -229,13 +229,13 @@ static struct pll_clk a57_pll1 = {
/* Necessary since we'll be setting a rate before handoff on V1 */
.src_rate = 19200000,
.min_rate = 1209600000,
- .max_rate = 1996800000,
+ .max_rate = 2073600000,
.base = &vbases[C1_PLL_BASE],
.c = {
.parent = &xo_ao.c,
.dbg_name = "a57_pll1",
.ops = &clk_ops_variable_rate_pll,
- VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 1996800000),
+ VDD_DIG_FMAX_MAP2(LOW, 1593600000, NOMINAL, 2073600000),
CLK_INIT(a57_pll1.c),
},
};

280
Patches/Overclocks/android_kernel_lge_g3/0001-Overclock.patch
View File

@ -1,280 +0,0 @@
From 74c64c5ec0f3ade9f3938b9e8634f85c77daeb42 Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Thu, 23 Oct 2014 15:41:10 +0200
Subject: [PATCH] arch/arm/boot/dts: Overclocking up 2.7 Ghz
---
arch/arm/boot/dts/msm8974-regulator.dtsi | 8 +--
arch/arm/boot/dts/msm8974.dtsi | 6 +-
arch/arm/boot/dts/msm8974pro.dtsi | 96 ++++++++++++++++++++++++++------
3 files changed, 89 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974-regulator.dtsi b/arch/arm/boot/dts/msm8974-regulator.dtsi
index d5e8530a96f..9e29db34874 100644
--- a/arch/arm/boot/dts/msm8974-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974-regulator.dtsi
@@ -475,7 +475,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -491,7 +491,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -507,7 +507,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -523,7 +523,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 495117ff6e4..fc19c18e716 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1582,7 +1582,11 @@
< 1728000 1651200 6103 >,
< 1958400 1728000 7102 >,
< 2265600 1728000 7102 >,
- < 2457600 1728000 7102 >;
+ < 2457600 1728000 7102 >,
+ < 2534400 1728000 7102 >,
+ < 2611200 1728000 7102 >,
+ < 2688000 1728000 7102 >,
+ < 2764800 1728000 7102 >;
};
usb3: qcom,ssusb@f9200000 {
diff --git a/arch/arm/boot/dts/msm8974pro.dtsi b/arch/arm/boot/dts/msm8974pro.dtsi
index 3d03d9d2ee6..b01788d0020 100644
--- a/arch/arm/boot/dts/msm8974pro.dtsi
+++ b/arch/arm/boot/dts/msm8974pro.dtsi
@@ -1036,7 +1036,11 @@
< 2265600000 1085000 716 >,
< 2342400000 1100000 751 >,
< 2419200000 1115000 786 >,
- < 2457600000 1120000 802 >;
+ < 2457600000 1120000 802 >,
+ < 2534400000 1135000 837 >,
+ < 2611200000 1150000 872 >,
+ < 2688000000 1165000 907 >,
+ < 2764800000 1180000 942 >;
qcom,speed3-pvs1-bin-v1 =
< 0 0 0 >,
@@ -1070,7 +1074,11 @@
< 2265600000 1075000 716 >,
< 2342400000 1090000 751 >,
< 2419200000 1105000 786 >,
- < 2457600000 1110000 802 >;
+ < 2457600000 1110000 802 >,
+ < 2534400000 1125000 837 >,
+ < 2611200000 1140000 872 >,
+ < 2688000000 1155000 907 >,
+ < 2764800000 1170000 942 >;
qcom,speed3-pvs2-bin-v1 =
< 0 0 0 >,
@@ -1104,7 +1112,11 @@
< 2265600000 1065000 716 >,
< 2342400000 1080000 751 >,
< 2419200000 1095000 786 >,
- < 2457600000 1100000 802 >;
+ < 2457600000 1100000 802 >,
+ < 2534400000 1115000 837 >,
+ < 2611200000 1130000 872 >,
+ < 2688000000 1145000 907 >,
+ < 2764800000 1160000 942 >;
qcom,speed3-pvs3-bin-v1 =
< 0 0 0 >,
@@ -1138,7 +1150,11 @@
< 2265600000 1055000 716 >,
< 2342400000 1070000 751 >,
< 2419200000 1085000 786 >,
- < 2457600000 1090000 802 >;
+ < 2457600000 1090000 802 >,
+ < 2534400000 1105000 837 >,
+ < 2611200000 1120000 872 >,
+ < 2688000000 1135000 907 >,
+ < 2764800000 1150000 942 >;
qcom,speed3-pvs4-bin-v1 =
< 0 0 0 >,
@@ -1172,7 +1188,11 @@
< 2265600000 1045000 716 >,
< 2342400000 1060000 751 >,
< 2419200000 1075000 786 >,
- < 2457600000 1080000 802 >;
+ < 2457600000 1080000 802 >,
+ < 2534400000 1095000 837 >,
+ < 2611200000 1110000 872 >,
+ < 2688000000 1125000 907 >,
+ < 2764800000 1140000 942 >;
qcom,speed3-pvs5-bin-v1 =
< 0 0 0 >,
@@ -1206,7 +1226,11 @@
< 2265600000 1035000 716 >,
< 2342400000 1050000 751 >,
< 2419200000 1065000 786 >,
- < 2457600000 1070000 802 >;
+ < 2457600000 1070000 802 >,
+ < 2534400000 1085000 837 >,
+ < 2611200000 1100000 872 >,
+ < 2688000000 1115000 907 >,
+ < 2764800000 1130000 942 >;
qcom,speed3-pvs6-bin-v1 =
< 0 0 0 >,
@@ -1240,7 +1264,11 @@
< 2265600000 1025000 716 >,
< 2342400000 1040000 751 >,
< 2419200000 1055000 786 >,
- < 2457600000 1060000 802 >;
+ < 2457600000 1060000 802 >,
+ < 2534400000 1075000 837 >,
+ < 2611200000 1090000 872 >,
+ < 2688000000 1105000 907 >,
+ < 2764800000 1120000 942 >;
qcom,speed3-pvs7-bin-v1 =
< 0 0 0 >,
@@ -1274,7 +1302,11 @@
< 2265600000 1015000 716 >,
< 2342400000 1030000 751 >,
< 2419200000 1045000 786 >,
- < 2457600000 1050000 802 >;
+ < 2457600000 1050000 802 >,
+ < 2534400000 1065000 837 >,
+ < 2611200000 1080000 872 >,
+ < 2688000000 1095000 907 >,
+ < 2764800000 1110000 942 >;
qcom,speed3-pvs8-bin-v1 =
< 0 0 0 >,
@@ -1308,7 +1340,11 @@
< 2265600000 1005000 716 >,
< 2342400000 1020000 751 >,
< 2419200000 1035000 786 >,
- < 2457600000 1040000 802 >;
+ < 2457600000 1040000 802 >,
+ < 2534400000 1055000 837 >,
+ < 2611200000 1070000 872 >,
+ < 2688000000 1085000 907 >,
+ < 2764800000 1100000 942 >;
qcom,speed3-pvs9-bin-v1 =
< 0 0 0 >,
@@ -1342,7 +1378,11 @@
< 2265600000 995000 716 >,
< 2342400000 1010000 751 >,
< 2419200000 1025000 786 >,
- < 2457600000 1030000 802 >;
+ < 2457600000 1030000 802 >,
+ < 2534400000 1045000 837 >,
+ < 2611200000 1060000 872 >,
+ < 2688000000 1075000 907 >,
+ < 2764800000 1090000 942 >;
qcom,speed3-pvs10-bin-v1 =
< 0 0 0 >,
@@ -1376,7 +1416,11 @@
< 2265600000 985000 716 >,
< 2342400000 1000000 751 >,
< 2419200000 1015000 786 >,
- < 2457600000 1020000 802 >;
+ < 2457600000 1020000 802 >,
+ < 2534400000 1035000 837 >,
+ < 2611200000 1050000 872 >,
+ < 2688000000 1065000 907 >,
+ < 2764800000 1080000 942 >;
qcom,speed3-pvs11-bin-v1 =
< 0 0 0 >,
@@ -1410,7 +1454,11 @@
< 2265600000 975000 716 >,
< 2342400000 990000 751 >,
< 2419200000 1005000 786 >,
- < 2457600000 1010000 802 >;
+ < 2457600000 1010000 802 >,
+ < 2534400000 1025000 837 >,
+ < 2611200000 1040000 872 >,
+ < 2688000000 1055000 907 >,
+ < 2764800000 1070000 942 >;
qcom,speed3-pvs12-bin-v1 =
< 0 0 0 >,
@@ -1444,7 +1492,11 @@
< 2265600000 965000 716 >,
< 2342400000 980000 751 >,
< 2419200000 995000 786 >,
- < 2457600000 1000000 802 >;
+ < 2457600000 1000000 802 >,
+ < 2534400000 1015000 837 >,
+ < 2611200000 1030000 872 >,
+ < 2688000000 1045000 907 >,
+ < 2764800000 1060000 942 >;
qcom,speed3-pvs13-bin-v1 =
< 0 0 0 >,
@@ -1478,7 +1530,11 @@
< 2265600000 955000 716 >,
< 2342400000 970000 751 >,
< 2419200000 985000 786 >,
- < 2457600000 990000 802 >;
+ < 2457600000 990000 802 >,
+ < 2534400000 1005000 837 >,
+ < 2611200000 1020000 872 >,
+ < 2688000000 1035000 907 >,
+ < 2764800000 1050000 942 >;
qcom,speed3-pvs14-bin-v1 =
< 0 0 0 >,
@@ -1512,7 +1568,11 @@
< 2265600000 945000 716 >,
< 2342400000 960000 751 >,
< 2419200000 975000 786 >,
- < 2457600000 980000 802 >;
+ < 2457600000 980000 802 >,
+ < 2534400000 995000 837 >,
+ < 2611200000 1010000 872 >,
+ < 2688000000 1025000 907 >,
+ < 2764800000 1040000 942 >;
qcom,speed3-pvs15-bin-v1 =
< 0 0 0 >,
@@ -1546,7 +1606,11 @@
< 2265600000 935000 716 >,
< 2342400000 950000 751 >,
< 2419200000 965000 786 >,
- < 2457600000 970000 802 >;
+ < 2457600000 970000 802 >,
+ < 2534400000 985000 837 >,
+ < 2611200000 1000000 872 >,
+ < 2688000000 1015000 907 >,
+ < 2764800000 1030000 942 >;
};
i2c@f9928000 { /* BLSP-1 QUP-6 */

82
Patches/Overclocks/android_kernel_lge_g3/0002-Overclock.patch
View File

@ -1,82 +0,0 @@
From 2d16761887d7fb80da131b5cf38e32bcc94a3011 Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Mon, 17 Nov 2014 21:21:08 +0100
Subject: [PATCH] arch/arm/boot/dts: Raise max microvolt at cpu for pm8941 and
pma8084
---
arch/arm/boot/dts/msm8974pro-pm8941.dtsi | 8 ++++----
arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi | 8 ++++----
2 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974pro-pm8941.dtsi b/arch/arm/boot/dts/msm8974pro-pm8941.dtsi
index b5020789bbb..2c5dd3d4416 100644
--- a/arch/arm/boot/dts/msm8974pro-pm8941.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-pm8941.dtsi
@@ -39,22 +39,22 @@
};
&krait0_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
&krait1_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
&krait2_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
&krait3_vreg {
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,ldo-delta-voltage = <12500>;
};
diff --git a/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi b/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi
index 433d466a3ee..8674dee3096 100644
--- a/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974pro-pma8084-regulator.dtsi
@@ -492,7 +492,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -508,7 +508,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -524,7 +524,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -540,7 +540,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1120000>;
+ regulator-max-microvolt = <1180000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;

38
Patches/Overclocks/android_kernel_lge_g3/0003-Overclock.patch
View File

@ -1,38 +0,0 @@
From 74a364df2dfe05460cffd081ac3bab672faf346c Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Thu, 20 Nov 2014 21:28:16 +0100
Subject: [PATCH] arch/arm/boot/dts: Add more frequencies for UC
---
arch/arm/boot/dts/msm8974.dtsi | 8 ++++++++
1 file changed, 8 insertions(+)
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index fc19c18e716..83ead25e266 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1569,6 +1569,7 @@
compatible = "qcom,msm-cpufreq";
qcom,cpufreq-table =
< 300000 300000 572 >,
+ < 345600 300000 572 >,
< 422400 422400 1144 >,
< 652800 499200 1525 >,
< 729600 576000 2342 >,
@@ -1579,9 +1580,16 @@
< 1267200 1267200 4684 >,
< 1497600 1497600 4684 >,
< 1574400 1574400 6103 >,
+ < 1651200 1574400 6103 >,
< 1728000 1651200 6103 >,
+ < 1804800 1651200 6103 >,
< 1958400 1728000 7102 >,
+ < 2035200 1728000 7102 >,
+ < 2112000 1728000 7102 >,
+ < 2188800 1728000 7102 >,
< 2265600 1728000 7102 >,
+ < 2342400 1728000 7102 >,
+ < 2419200 1728000 7102 >,
< 2457600 1728000 7102 >,
< 2534400 1728000 7102 >,
< 2611200 1728000 7102 >,

39
Patches/Overclocks/android_kernel_lge_g3/0004-Overclock.patch
View File

@ -1,39 +0,0 @@
From 52b1a7fd2f9379f703d0d9f368faba1e993c37b8 Mon Sep 17 00:00:00 2001
From: Tectas <adrian.stoeckl@gmail.com>
Date: Wed, 26 Nov 2014 09:36:19 +0100
Subject: [PATCH] arch/arm/boot/dts: Remove some UC steps for better
performance
---
arch/arm/boot/dts/msm8974.dtsi | 5 -----
1 file changed, 5 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974.dtsi b/arch/arm/boot/dts/msm8974.dtsi
index 83ead25e266..de83da943dd 100644
--- a/arch/arm/boot/dts/msm8974.dtsi
+++ b/arch/arm/boot/dts/msm8974.dtsi
@@ -1569,7 +1569,6 @@
compatible = "qcom,msm-cpufreq";
qcom,cpufreq-table =
< 300000 300000 572 >,
- < 345600 300000 572 >,
< 422400 422400 1144 >,
< 652800 499200 1525 >,
< 729600 576000 2342 >,
@@ -1580,16 +1579,12 @@
< 1267200 1267200 4684 >,
< 1497600 1497600 4684 >,
< 1574400 1574400 6103 >,
- < 1651200 1574400 6103 >,
< 1728000 1651200 6103 >,
< 1804800 1651200 6103 >,
< 1958400 1728000 7102 >,
- < 2035200 1728000 7102 >,
< 2112000 1728000 7102 >,
< 2188800 1728000 7102 >,
- < 2265600 1728000 7102 >,
< 2342400 1728000 7102 >,
- < 2419200 1728000 7102 >,
< 2457600 1728000 7102 >,
< 2534400 1728000 7102 >,
< 2611200 1728000 7102 >,

757
Patches/Overclocks/android_kernel_lge_hammerhead/0001-Overclock.patch
View File

@ -1,757 +0,0 @@
From ec5d8918e9d3149ce489900f48d6e6ebd2fd5031 Mon Sep 17 00:00:00 2001
From: Paul Reioux <reioux@gmail.com>
Date: Sun, 20 Oct 2013 22:30:36 -0500
Subject: [PATCH 1/5] Voltage Control: initial voltage control for MSM
Snapdragon 800 SOC
Signed-off-by: Paul Reioux <reioux@gmail.com>
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/Kconfig | 6 +++++
arch/arm/mach-msm/acpuclock-krait.c | 48 +++++++++++++++++++++++++++++++++++++
2 files changed, 54 insertions(+)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index ba5a33c..44db2ca 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1918,6 +1918,12 @@ config MSM_CPU_FREQ_MIN
endif # CPU_FREQ_MSM
+config CPU_VOLTAGE_TABLE
+ bool "Enable CPU Voltage Table via sysfs for adjustements"
+ default n
+ help
+ Krait User Votlage Control
+
config MSM_AVS_HW
bool "Enable Adaptive Voltage Scaling (AVS)"
default n
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 84e2fc1..c7eceb1 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -937,6 +937,54 @@ static void __init bus_init(const struct l2_level *l2_level)
dev_err(drv.dev, "initial bandwidth req failed (%d)\n", ret);
}
+#ifdef CONFIG_CPU_VOLTAGE_TABLE
+
+#define HFPLL_MIN_VDD 800000
+#define HFPLL_MAX_VDD 1350000
+
+ssize_t acpuclk_get_vdd_levels_str(char *buf) {
+
+ int i, len = 0;
+
+ if (buf) {
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ /* updated to use uv required by 8x60 architecture - faux123 */
+ len += sprintf(buf + len, "%8lu: %8d\n", drv.acpu_freq_tbl[i].speed.khz,
+ drv.acpu_freq_tbl[i].vdd_core );
+ }
+
+ mutex_unlock(&driver_lock);
+ }
+ return len;
+}
+
+/* updated to use uv required by 8x60 architecture - faux123 */
+void acpuclk_set_vdd(unsigned int khz, int vdd_uv) {
+
+ int i;
+ unsigned int new_vdd_uv;
+
+ mutex_lock(&driver_lock);
+
+ for (i = 0; drv.acpu_freq_tbl[i].speed.khz; i++) {
+ if (khz == 0)
+ new_vdd_uv = min(max((unsigned int)(drv.acpu_freq_tbl[i].vdd_core + vdd_uv),
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else if ( drv.acpu_freq_tbl[i].speed.khz == khz)
+ new_vdd_uv = min(max((unsigned int)vdd_uv,
+ (unsigned int)HFPLL_MIN_VDD), (unsigned int)HFPLL_MAX_VDD);
+ else
+ continue;
+
+ drv.acpu_freq_tbl[i].vdd_core = new_vdd_uv;
+ }
+ pr_warn("faux123: user voltage table modified!\n");
+ mutex_unlock(&driver_lock);
+}
+#endif /* CONFIG_CPU_VOTALGE_TABLE */
+
#ifdef CONFIG_CPU_FREQ_MSM
static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
--
2.9.3
From 1e4ac53ff15efeaf4cb3998b9ba009095d582413 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Sat, 9 Nov 2013 00:17:33 -0500
Subject: [PATCH 2/5] Increase voltage limits
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/boot/dts/msm8974-regulator.dtsi | 8 ++++----
arch/arm/mach-msm/acpuclock-8974.c | 8 ++++----
arch/arm/mach-msm/acpuclock-krait.c | 4 ++--
3 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/arm/boot/dts/msm8974-regulator.dtsi b/arch/arm/boot/dts/msm8974-regulator.dtsi
index 9de41f4..6a38980 100644
--- a/arch/arm/boot/dts/msm8974-regulator.dtsi
+++ b/arch/arm/boot/dts/msm8974-regulator.dtsi
@@ -477,7 +477,7 @@
<0xf908a800 0x1000>; /* APCS_ALIAS0_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -493,7 +493,7 @@
<0xf909a800 0x1000>; /* APCS_ALIAS1_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -509,7 +509,7 @@
<0xf90aa800 0x1000>; /* APCS_ALIAS2_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
@@ -525,7 +525,7 @@
<0xf90ba800 0x1000>; /* APCS_ALIAS3_KPSS_MDD */
reg-names = "acs", "mdd";
regulator-min-microvolt = <500000>;
- regulator-max-microvolt = <1100000>;
+ regulator-max-microvolt = <1200000>;
qcom,headroom-voltage = <150000>;
qcom,retention-voltage = <675000>;
qcom,ldo-default-voltage = <750000>;
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 694d783..8b7d74e 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -55,7 +55,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF908A000,
.l2cpmr_iaddr = 0x4501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait0", 1100000 },
+ .vreg[VREG_CORE] = { "krait0", 1200000 },
.vreg[VREG_MEM] = { "krait0_mem", 1050000 },
.vreg[VREG_DIG] = { "krait0_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -64,7 +64,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF909A000,
.l2cpmr_iaddr = 0x5501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait1", 1100000 },
+ .vreg[VREG_CORE] = { "krait1", 1200000 },
.vreg[VREG_MEM] = { "krait1_mem", 1050000 },
.vreg[VREG_DIG] = { "krait1_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
@@ -73,7 +73,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF90AA000,
.l2cpmr_iaddr = 0x6501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait2", 1100000 },
+ .vreg[VREG_CORE] = { "krait2", 1200000 },
.vreg[VREG_MEM] = { "krait2_mem", 1050000 },
.vreg[VREG_DIG] = { "krait2_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
@@ -82,7 +82,7 @@ static struct scalable scalable[] __initdata = {
.hfpll_phys_base = 0xF90BA000,
.l2cpmr_iaddr = 0x7501,
.sec_clk_sel = 2,
- .vreg[VREG_CORE] = { "krait3", 1100000 },
+ .vreg[VREG_CORE] = { "krait3", 1200000 },
.vreg[VREG_MEM] = { "krait3_mem", 1050000 },
.vreg[VREG_DIG] = { "krait3_dig", LVL_HIGH },
.vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index c7eceb1..2211ad3 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -939,8 +939,8 @@ static void __init bus_init(const struct l2_level *l2_level)
#ifdef CONFIG_CPU_VOLTAGE_TABLE
-#define HFPLL_MIN_VDD 800000
-#define HFPLL_MAX_VDD 1350000
+#define HFPLL_MIN_VDD 500000
+#define HFPLL_MAX_VDD 1200000
ssize_t acpuclk_get_vdd_levels_str(char *buf) {
--
2.9.3
From 28d7063d0b5a45d328633e4a59d20ac148f1fadd Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Sat, 9 Nov 2013 01:27:36 -0500
Subject: [PATCH 3/5] CPU overclocking
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/acpuclock-8974.c | 42 ++++++++++
arch/arm/mach-msm/acpuclock-krait.c | 148 +++++++++++++++++++++++++++++++++++-
2 files changed, 189 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 8b7d74e..cb878d9 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -710,6 +710,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs0[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1070000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1085000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1100000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1115000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1130000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1145000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1160000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1175000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1195000, 831 },
{ 0, { 0 } }
};
@@ -741,6 +747,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs1[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1045000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1060000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1075000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1090000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1105000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1120000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1135000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1150000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1165000, 831 },
{ 0, { 0 } }
};
@@ -772,6 +784,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs2[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 1020000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1035000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1050000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1065000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1080000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1095000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1110000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1125000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1140000, 831 },
{ 0, { 0 } }
};
@@ -803,6 +821,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs3[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 995000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 1010000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1025000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1040000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1055000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1070000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1085000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1100000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1115000, 831 },
{ 0, { 0 } }
};
@@ -834,6 +858,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs4[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 975000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 985000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 1000000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 1015000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1030000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1045000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1060000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1075000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1090000, 831 },
{ 0, { 0 } }
};
@@ -865,6 +895,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs5[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 955000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 965000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 975000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 990000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 1005000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 1020000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1035000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1050000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1065000, 831 },
{ 0, { 0 } }
};
@@ -896,6 +932,12 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs6[] __initdata = {
{ 0, { 2112000, HFPLL, 1, 110 }, L2(19), 930000, 627 },
{ 0, { 2188800, HFPLL, 1, 114 }, L2(19), 940000, 659 },
{ 1, { 2265600, HFPLL, 1, 118 }, L2(19), 950000, 691 },
+ { 1, { 2342400, HFPLL, 1, 122 }, L2(19), 960000, 714 },
+ { 1, { 2419200, HFPLL, 1, 126 }, L2(19), 975000, 738 },
+ { 1, { 2496000, HFPLL, 1, 130 }, L2(19), 990000, 761 },
+ { 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1005000, 784 },
+ { 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1020000, 808 },
+ { 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1035000, 831 },
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 2211ad3..bcd3e44 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -45,6 +45,113 @@
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
+
+/** elementalx defs **/
+static int uv_bin = 2;
+static uint32_t arg_max_oc0 = 2265600;
+static uint32_t arg_max_oc1 = 2265600;
+static uint32_t arg_max_oc2 = 2265600;
+static uint32_t arg_max_oc3 = 2265600;
+
+int pvs_number = 0;
+module_param(pvs_number, int, 0755);
+
+/* boot arg max_oc */
+static int __init cpufreq_read_arg_max_oc0(char *max_oc0)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc0, 0, &ui_khz);
+ if (err) {
+ arg_max_oc0 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc0='%i'\n", arg_max_oc0);
+ return 1;
+ }
+
+ arg_max_oc0 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc0=", cpufreq_read_arg_max_oc0);
+
+static int __init cpufreq_read_arg_max_oc1(char *max_oc1)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc1, 0, &ui_khz);
+ if (err) {
+ arg_max_oc1 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc1='%i'\n", arg_max_oc1);
+ return 1;
+ }
+
+ arg_max_oc1 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc1=", cpufreq_read_arg_max_oc1);
+
+static int __init cpufreq_read_arg_max_oc2(char *max_oc2)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc2, 0, &ui_khz);
+ if (err) {
+ arg_max_oc2 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc2='%i'\n", arg_max_oc2);
+ return 1;
+ }
+
+ arg_max_oc2 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc2=", cpufreq_read_arg_max_oc2);
+
+static int __init cpufreq_read_arg_max_oc3(char *max_oc3)
+{
+ unsigned long ui_khz;
+ int err;
+ err = strict_strtoul(max_oc3, 0, &ui_khz);
+ if (err) {
+ arg_max_oc3 = 2265600;
+ printk(KERN_INFO "[elementalx]: max_oc3='%i'\n", arg_max_oc3);
+ return 1;
+ }
+
+ arg_max_oc3 = ui_khz;
+
+ return 0;
+}
+__setup("max_oc3=", cpufreq_read_arg_max_oc3);
+
+static int __init get_uv_level(char *vdd_uv)
+{
+ if (strcmp(vdd_uv, "0") == 0) {
+ uv_bin = 0;
+ } else if (strcmp(vdd_uv, "1") == 0) {
+ uv_bin = 1;
+ } else if (strcmp(vdd_uv, "2") == 0) {
+ uv_bin = 2;
+ } else if (strcmp(vdd_uv, "3") == 0) {
+ uv_bin = 3;
+ } else if (strcmp(vdd_uv, "4") == 0) {
+ uv_bin = 4;
+ } else if (strcmp(vdd_uv, "5") == 0) {
+ uv_bin = 5;
+ } else if (strcmp(vdd_uv, "6") == 0) {
+ uv_bin = 6;
+ } else {
+ uv_bin = 0;
+ }
+ return 0;
+}
+
+__setup("vdd_uv=", get_uv_level);
+
+/** end elementalx defs **/
+
+
static DEFINE_MUTEX(driver_lock);
static DEFINE_SPINLOCK(l2_lock);
@@ -992,13 +1099,14 @@ static void __init cpufreq_table_init(void)
{
int cpu;
int freq_cnt = 0;
+ uint32_t limit_max_oc[4] = {arg_max_oc0, arg_max_oc1, arg_max_oc2, arg_max_oc3};
for_each_possible_cpu(cpu) {
int i;
/* Construct the freq_table tables from acpu_freq_tbl. */
for (i = 0, freq_cnt = 0; drv.acpu_freq_tbl[i].speed.khz != 0
&& freq_cnt < ARRAY_SIZE(*freq_table); i++) {
- if (drv.acpu_freq_tbl[i].use_for_scaling) {
+ if (drv.acpu_freq_tbl[i].speed.khz <= limit_max_oc[cpu]) {
freq_table[cpu][freq_cnt].index = freq_cnt;
freq_table[cpu][freq_cnt].frequency
= drv.acpu_freq_tbl[i].speed.khz;
@@ -1109,6 +1217,39 @@ static void __init krait_apply_vmin(struct acpu_level *tbl)
}
}
+static void apply_undervolting(void)
+{
+ if (uv_bin == 6) {
+ drv.acpu_freq_tbl[0].vdd_core = 625000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 5) {
+ drv.acpu_freq_tbl[0].vdd_core = 650000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 4) {
+ drv.acpu_freq_tbl[0].vdd_core = 675000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 3) {
+ drv.acpu_freq_tbl[0].vdd_core = 700000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 2) {
+ drv.acpu_freq_tbl[0].vdd_core = 725000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+
+ if (uv_bin == 1) {
+ drv.acpu_freq_tbl[0].vdd_core = 750000;
+ printk(KERN_INFO "[elementalx]: min_voltage='%i'\n", drv.acpu_freq_tbl[0].vdd_core );
+ }
+}
+
void __init get_krait_bin_format_a(void __iomem *base, struct bin_info *bin)
{
u32 pte_efuse = readl_relaxed(base);
@@ -1143,6 +1284,8 @@ void __init get_krait_bin_format_b(void __iomem *base, struct bin_info *bin)
}
bin->speed_valid = true;
+ pvs_number = bin->pvs;
+
/* Check PVS_BLOW_STATUS */
pte_efuse = readl_relaxed(base + 0x4);
bin->pvs_valid = !!(pte_efuse & BIT(21));
@@ -1229,6 +1372,9 @@ static void __init hw_init(void)
if (krait_needs_vmin())
krait_apply_vmin(drv.acpu_freq_tbl);
+ if (uv_bin)
+ apply_undervolting();
+
l2->hfpll_base = ioremap(l2->hfpll_phys_base, SZ_32);
BUG_ON(!l2->hfpll_base);
--
2.9.3
From cbc2f6c8893c773d4dbdf9d5f538f6b44a02baa4 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Sat, 9 Nov 2013 08:43:31 -0500
Subject: [PATCH 4/5] L2 cache and bus bandwidth overclocking
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/acpuclock-8974.c | 46 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-msm/acpuclock-krait.c | 2 +-
2 files changed, 47 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index cb878d9..933bd0e 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -28,6 +28,8 @@
#define LVL_NOM RPM_REGULATOR_CORNER_NORMAL
#define LVL_HIGH RPM_REGULATOR_CORNER_SUPER_TURBO
+static int opt_bin = 0;
+
static struct hfpll_data hfpll_data __initdata = {
.mode_offset = 0x00,
.l_offset = 0x04,
@@ -257,6 +259,7 @@ static struct msm_bus_paths bw_level_tbl_v2[] __initdata = {
[6] = BW_MBPS(4912), /* At least 614 MHz on bus. */
[7] = BW_MBPS(6400), /* At least 800 MHz on bus. */
[8] = BW_MBPS(7448), /* At least 931 MHz on bus. */
+ [9] = BW_MBPS(8000), /* At least 1000 MHz on bus. */
};
static struct l2_level l2_freq_tbl_v2[] __initdata = {
@@ -283,6 +286,30 @@ static struct l2_level l2_freq_tbl_v2[] __initdata = {
{ }
};
+static struct l2_level l2_freq_tbl_v2_elementalx[] __initdata = {
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
+ [1] = { { 345600, HFPLL, 2, 36 }, LVL_LOW, 950000, 1 },
+ [2] = { { 422400, HFPLL, 2, 44 }, LVL_LOW, 950000, 2 },
+ [3] = { { 499200, HFPLL, 2, 52 }, LVL_LOW, 950000, 3 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_LOW, 950000, 4 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 4 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 4 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 4 },
+ [8] = { { 883200, HFPLL, 1, 46 }, LVL_NOM, 950000, 5 },
+ [9] = { { 960000, HFPLL, 1, 50 }, LVL_NOM, 950000, 5 },
+ [10] = { { 1036800, HFPLL, 1, 54 }, LVL_NOM, 950000, 5 },
+ [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 6 },
+ [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 6 },
+ [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 6 },
+ [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 6 },
+ [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 6 },
+ [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 6 },
+ [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 7 },
+ [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 7 },
+ [19] = { { 1804800, HFPLL, 1, 94 }, LVL_HIGH, 1050000, 9 },
+ { }
+};
+
static struct acpu_level acpu_freq_tbl_2g_pvs0[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 815000, 73 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 825000, 85 },
@@ -1003,6 +1030,20 @@ static struct acpuclk_krait_params acpuclk_8974_params __initdata = {
.stby_khz = 300000,
};
+static int __init get_opt_level(char *l2_opt)
+{
+ if (strcmp(l2_opt, "0") == 0) {
+ opt_bin = 0;
+ } else if (strcmp(l2_opt, "1") == 0) {
+ opt_bin = 1;
+ } else {
+ opt_bin = 0;
+ }
+ return 0;
+}
+
+__setup("l2_opt=", get_opt_level);
+
static void __init apply_v1_l2_workaround(void)
{
static struct l2_level resticted_l2_tbl[] __initdata = {
@@ -1042,6 +1083,11 @@ static int __init acpuclk_8974_probe(struct platform_device *pdev)
apply_v1_l2_workaround();
}
+ if (opt_bin == 1) {
+ acpuclk_8974_params.l2_freq_tbl = l2_freq_tbl_v2_elementalx;
+ acpuclk_8974_params.l2_freq_tbl_size = sizeof(l2_freq_tbl_v2_elementalx);
+ }
+
return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
}
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index bcd3e44..a1c8fbb 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -47,7 +47,7 @@
/** elementalx defs **/
-static int uv_bin = 2;
+static int uv_bin = 0;
static uint32_t arg_max_oc0 = 2265600;
static uint32_t arg_max_oc1 = 2265600;
static uint32_t arg_max_oc2 = 2265600;
--
2.9.3
From bfd08d2e2a997ac4f5b6e8353be663472643b746 Mon Sep 17 00:00:00 2001
From: flar2 <asegaert@gmail.com>
Date: Mon, 11 Nov 2013 00:42:12 -0500
Subject: [PATCH 5/5] More overclocking options
Signed-off-by: flar2 <asegaert@gmail.com>
---
arch/arm/mach-msm/acpuclock-8974.c | 50 ++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/arch/arm/mach-msm/acpuclock-8974.c b/arch/arm/mach-msm/acpuclock-8974.c
index 933bd0e..b436816 100644
--- a/arch/arm/mach-msm/acpuclock-8974.c
+++ b/arch/arm/mach-msm/acpuclock-8974.c
@@ -310,6 +310,29 @@ static struct l2_level l2_freq_tbl_v2_elementalx[] __initdata = {
{ }
};
+static struct l2_level l2_freq_tbl_v2_ultra[] __initdata = {
+ [0] = { { 300000, PLL_0, 0, 0 }, LVL_LOW, 950000, 0 },
+ [1] = { { 345600, HFPLL, 2, 36 }, LVL_LOW, 950000, 1 },
+ [2] = { { 422400, HFPLL, 2, 44 }, LVL_LOW, 950000, 2 },
+ [3] = { { 499200, HFPLL, 2, 52 }, LVL_LOW, 950000, 3 },
+ [4] = { { 576000, HFPLL, 1, 30 }, LVL_LOW, 950000, 4 },
+ [5] = { { 652800, HFPLL, 1, 34 }, LVL_NOM, 950000, 4 },
+ [6] = { { 729600, HFPLL, 1, 38 }, LVL_NOM, 950000, 4 },
+ [7] = { { 806400, HFPLL, 1, 42 }, LVL_NOM, 950000, 4 },
+ [8] = { { 883200, HFPLL, 1, 46 }, LVL_NOM, 950000, 5 },
+ [9] = { { 960000, HFPLL, 1, 50 }, LVL_NOM, 950000, 5 },
+ [10] = { { 1036800, HFPLL, 1, 54 }, LVL_NOM, 950000, 5 },
+ [11] = { { 1113600, HFPLL, 1, 58 }, LVL_HIGH, 1050000, 6 },
+ [12] = { { 1190400, HFPLL, 1, 62 }, LVL_HIGH, 1050000, 6 },
+ [13] = { { 1267200, HFPLL, 1, 66 }, LVL_HIGH, 1050000, 6 },
+ [14] = { { 1344000, HFPLL, 1, 70 }, LVL_HIGH, 1050000, 6 },
+ [15] = { { 1420800, HFPLL, 1, 74 }, LVL_HIGH, 1050000, 6 },
+ [16] = { { 1497600, HFPLL, 1, 78 }, LVL_HIGH, 1050000, 6 },
+ [17] = { { 1574400, HFPLL, 1, 82 }, LVL_HIGH, 1050000, 7 },
+ [18] = { { 1651200, HFPLL, 1, 86 }, LVL_HIGH, 1050000, 7 },
+ [19] = { { 1920000, HFPLL, 1, 100 }, LVL_HIGH, 1050000, 9 },
+ { }
+};
static struct acpu_level acpu_freq_tbl_2g_pvs0[] __initdata = {
{ 1, { 300000, PLL_0, 0, 0 }, L2(0), 815000, 73 },
{ 0, { 345600, HFPLL, 2, 36 }, L2(1), 825000, 85 },
@@ -743,6 +766,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs0[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1160000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1175000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1195000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1195000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1195000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1195000, 897 },
{ 0, { 0 } }
};
@@ -780,6 +806,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs1[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1135000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1150000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1165000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1180000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1195000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1195000, 897 },
{ 0, { 0 } }
};
@@ -817,6 +846,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs2[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1110000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1125000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1140000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1165000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1180000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1195000, 897 },
{ 0, { 0 } }
};
@@ -854,6 +886,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs3[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1085000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1100000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1115000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1130000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1145000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1160000, 897 },
{ 0, { 0 } }
};
@@ -891,6 +926,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs4[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1060000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1075000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1090000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1105000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1120000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1135000, 897 },
{ 0, { 0 } }
};
@@ -928,6 +966,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs5[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1035000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1050000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1065000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1080000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1095000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1110000, 897 },
{ 0, { 0 } }
};
@@ -965,6 +1006,9 @@ static struct acpu_level acpu_freq_tbl_2p3g_pvs6[] __initdata = {
{ 1, { 2572800, HFPLL, 1, 134 }, L2(19), 1005000, 784 },
{ 1, { 2649600, HFPLL, 1, 138 }, L2(19), 1020000, 808 },
{ 1, { 2726400, HFPLL, 1, 142 }, L2(19), 1035000, 831 },
+ { 1, { 2803200, HFPLL, 1, 146 }, L2(19), 1050000, 854 },
+ { 1, { 2880000, HFPLL, 1, 150 }, L2(19), 1065000, 876 },
+ { 1, { 2956800, HFPLL, 1, 154 }, L2(19), 1080000, 897 },
{ 0, { 0 } }
};
@@ -1036,6 +1080,8 @@ static int __init get_opt_level(char *l2_opt)
opt_bin = 0;
} else if (strcmp(l2_opt, "1") == 0) {
opt_bin = 1;
+ } else if (strcmp(l2_opt, "2") == 0) {
+ opt_bin = 2;
} else {
opt_bin = 0;
}
@@ -1087,6 +1133,10 @@ static int __init acpuclk_8974_probe(struct platform_device *pdev)
acpuclk_8974_params.l2_freq_tbl = l2_freq_tbl_v2_elementalx;
acpuclk_8974_params.l2_freq_tbl_size = sizeof(l2_freq_tbl_v2_elementalx);
}
+ if (opt_bin == 2) {
+ acpuclk_8974_params.l2_freq_tbl = l2_freq_tbl_v2_ultra;
+ acpuclk_8974_params.l2_freq_tbl_size = sizeof(l2_freq_tbl_v2_ultra);
+ }
return acpuclk_krait_init(&pdev->dev, &acpuclk_8974_params);
}
--
2.9.3

272
Patches/Overclocks/android_kernel_lge_mako/0001-Overclock.patch
View File

@ -1,272 +0,0 @@
From 5858badcc16994ea21140b5a905536d365da45b4 Mon Sep 17 00:00:00 2001
From: anarkia1976 <stefano.villa1976@gmail.com>
Date: Sun, 12 Jan 2014 20:26:27 +0100
Subject: [PATCH] msm: cpu: overclock: added low (162Mhz) and high (1944Mhz)
cpu
---
arch/arm/mach-msm/Kconfig | 13 ++++++
arch/arm/mach-msm/acpuclock-8064.c | 91 +++++++++++++++++++++++++++++++++++++
arch/arm/mach-msm/acpuclock-krait.c | 8 +++-
arch/arm/mach-msm/msm_dcvs.c | 5 ++
4 files changed, 116 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 890c96e3a1f..814ab1a88b4 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1633,6 +1633,19 @@ config MSM_CPU_FREQ_MIN
endif # CPU_FREQ_MSM
+config LOW_CPUCLOCKS
+ bool "Enable ultra low CPU clocks"
+ default n
+ help
+ Ultra low cpu frequencies enabled for CPU and L2 Cache
+
+config CPU_OVERCLOCK
+ bool "Enable CPU Overclocking option"
+ default n
+ help
+ Krait overclocking up to 1.9 GHz
+
+
config MSM_AVS_HW
bool "Enable Adaptive Voltage Scaling (AVS)"
default n
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 8262946e016..f40edd3d687 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -47,7 +47,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait0", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait0", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -58,7 +62,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait1", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait1", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
@@ -69,7 +77,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x6501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait2", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait2", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait2_mem", 1150000 },
.vreg[VREG_DIG] = { "krait2_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait2_hfpll", 1800000 },
@@ -80,7 +92,11 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x7501,
+#ifdef CONFIG_CPU_OVERCLOCK
+ .vreg[VREG_CORE] = { "krait3", 1450000 },
+#else
.vreg[VREG_CORE] = { "krait3", 1300000 },
+#endif
.vreg[VREG_MEM] = { "krait3_mem", 1150000 },
.vreg[VREG_DIG] = { "krait3_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait3_hfpll", 1800000 },
@@ -116,6 +132,24 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
};
static struct l2_level l2_freq_tbl[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ [0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 },
+ [1] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
+ [2] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
+ [3] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
+ [4] = { { 540000, HFPLL, 2, 0x28 }, 1050000, 1050000, 2 },
+ [5] = { { 594000, HFPLL, 1, 0x16 }, 1050000, 1050000, 2 },
+ [6] = { { 648000, HFPLL, 1, 0x18 }, 1050000, 1050000, 4 },
+ [7] = { { 702000, HFPLL, 1, 0x1A }, 1150000, 1150000, 4 },
+ [8] = { { 756000, HFPLL, 1, 0x1C }, 1150000, 1150000, 4 },
+ [9] = { { 810000, HFPLL, 1, 0x1E }, 1150000, 1150000, 4 },
+ [10] = { { 864000, HFPLL, 1, 0x20 }, 1150000, 1150000, 4 },
+ [11] = { { 918000, HFPLL, 1, 0x22 }, 1150000, 1150000, 5 },
+ [12] = { { 972000, HFPLL, 1, 0x24 }, 1150000, 1150000, 5 },
+ [13] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
+ [14] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
+ [15] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+#else
[0] = { { 384000, PLL_8, 0, 0x00 }, 950000, 1050000, 1 },
[1] = { { 432000, HFPLL, 2, 0x20 }, 1050000, 1050000, 2 },
[2] = { { 486000, HFPLL, 2, 0x24 }, 1050000, 1050000, 2 },
@@ -131,11 +165,19 @@ static struct l2_level l2_freq_tbl[] __initdata = {
[12] = { { 1026000, HFPLL, 1, 0x26 }, 1150000, 1150000, 5 },
[13] = { { 1080000, HFPLL, 1, 0x28 }, 1150000, 1150000, 5 },
[14] = { { 1134000, HFPLL, 1, 0x2A }, 1150000, 1150000, 5 },
+#endif
{ }
};
static struct acpu_level tbl_slow[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
@@ -157,11 +199,25 @@ static struct acpu_level tbl_slow[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 },
+#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_nom[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 },
@@ -183,11 +239,25 @@ static struct acpu_level tbl_nom[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 },
+#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_fast[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
@@ -209,11 +279,25 @@ static struct acpu_level tbl_fast[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 },
+#endif
{ 0, { 0 } }
};
static struct acpu_level tbl_faster[] __initdata = {
+#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
+ //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
+ { 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
+#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
+#endif
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
@@ -235,6 +319,13 @@ static struct acpu_level tbl_faster[] __initdata = {
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },
{ 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1125000 },
+#ifdef CONFIG_CPU_OVERCLOCK
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 },
+ { 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 },
+ { 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 },
+#endif
{ 0, { 0 } }
};
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index e3a3f5486e4..97f6f3909f5 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -45,6 +45,12 @@
#define PRI_SRC_SEL_HFPLL 1
#define PRI_SRC_SEL_HFPLL_DIV2 2
+#ifdef CONFIG_LOW_CPUCLOCKS
+#define FREQ_TABLE_SIZE 39
+#else
+#define FREQ_TABLE_SIZE 35
+#endif
+
static DEFINE_MUTEX(driver_lock);
static DEFINE_SPINLOCK(l2_lock);
@@ -913,7 +919,7 @@ static void __init bus_init(const struct l2_level *l2_level)
}
#ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][FREQ_TABLE_SIZE];
static void __init cpufreq_table_init(void)
{
diff --git a/arch/arm/mach-msm/msm_dcvs.c b/arch/arm/mach-msm/msm_dcvs.c
index 1a919fcf577..1d5e289b9b8 100644
--- a/arch/arm/mach-msm/msm_dcvs.c
+++ b/arch/arm/mach-msm/msm_dcvs.c
@@ -146,7 +146,12 @@ static struct dcvs_core core_list[CORES_MAX];
static struct kobject *cores_kobj;
+#ifdef CONFIG_CPU_OVERCLOCK
+#define DCVS_MAX_NUM_FREQS 20
+#else
#define DCVS_MAX_NUM_FREQS 15
+#endif
+
static struct msm_dcvs_freq_entry cpu_freq_tbl[DCVS_MAX_NUM_FREQS];
static unsigned num_cpu_freqs;
static struct msm_dcvs_platform_data *dcvs_pdata;
--
2.15.1

60
Patches/Overclocks/android_kernel_lge_mako/0002-Overclock.patch
View File

@ -1,60 +0,0 @@
From e4ec1877adef9b5c222793f77390b607e5f5c900 Mon Sep 17 00:00:00 2001
From: anarkia1976 <stefano.villa1976@gmail.com>
Date: Wed, 5 Feb 2014 07:15:12 +0100
Subject: [PATCH] msm: cpu: overclock: added ultra low (81Mhz) cpu clock
frequencies
---
arch/arm/mach-msm/acpuclock-8064.c | 4 ++++
arch/arm/mach-msm/acpuclock-krait.c | 2 +-
2 files changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index e15d4b4ff4d..7879be1d564 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -172,6 +172,7 @@ static struct l2_level l2_freq_tbl[] __initdata = {
static struct acpu_level tbl_slow[] __initdata = {
#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 },
//{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 },
@@ -212,6 +213,7 @@ static struct acpu_level tbl_slow[] __initdata = {
static struct acpu_level tbl_nom[] __initdata = {
#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 },
//{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 },
@@ -252,6 +254,7 @@ static struct acpu_level tbl_nom[] __initdata = {
static struct acpu_level tbl_fast[] __initdata = {
#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
//{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
@@ -292,6 +295,7 @@ static struct acpu_level tbl_fast[] __initdata = {
static struct acpu_level tbl_faster[] __initdata = {
#ifdef CONFIG_LOW_CPUCLOCKS
+ { 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
//{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index 33be3163c63..12db7f9e9f6 100644
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -46,7 +46,7 @@
#define PRI_SRC_SEL_HFPLL_DIV2 2
#ifdef CONFIG_LOW_CPUCLOCKS
-#define FREQ_TABLE_SIZE 39
+#define FREQ_TABLE_SIZE 40
#else
#define FREQ_TABLE_SIZE 35
#endif

243
Patches/Overclocks/android_kernel_lge_mako/0003-Overclock.patch
View File

@ -1,243 +0,0 @@
From 946a09f5411890b1b1ec945b8c882bfa042f4523 Mon Sep 17 00:00:00 2001
From: anarkia1976 <stefano.villa1976@gmail.com>
Date: Wed, 5 Feb 2014 07:12:48 +0100
Subject: [PATCH] msm: cpu: overclock: use higher bus speed at lower CPU freqs
Thanks to @bedalus and @mrg666
Bedalus suggested that if lower CPU frequencies can offer higher bus
speed,
GPU use during games wouldn't require higher CPU frequency.
My testing demonstrated 4C drop in CPU temp during 3DMark benchmark.
Still needs to be tested for everyday use.
---
arch/arm/mach-msm/acpuclock-8064.c | 172 +++++++++++++++++++------------------
1 file changed, 88 insertions(+), 84 deletions(-)
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 7879be1d564..cd045cf0c97 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -132,6 +132,14 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
.name = "acpuclk-8064",
};
+#ifdef CONFIG_LOW_CPUCLOCKS
+#define L2_BW_MID 6
+#define L2_BW_HIGH 15
+#else
+#define L2_BW_MID 5
+#define L2_BW_HIGH 14
+#endif
+
static struct l2_level l2_freq_tbl[] __initdata = {
#ifdef CONFIG_LOW_CPUCLOCKS
[0] = { { 378000, HFPLL, 2, 0x1C }, 950000, 1050000, 1 },
@@ -175,32 +183,31 @@ static struct acpu_level tbl_slow[] __initdata = {
{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 },
- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 950000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 925000 },
#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 950000 },
#endif
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 975000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 975000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 1000000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 1000000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 1025000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 1025000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1075000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1075000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1100000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1100000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1125000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1125000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1175000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1175000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1200000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1200000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1225000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1225000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1237500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1237500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1250000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 975000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 975000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 1000000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 1000000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 1025000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 1025000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 1075000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 1075000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1100000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1100000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1125000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1125000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1175000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1175000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1200000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1200000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1225000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1225000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1237500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1237500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1250000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 },
@@ -216,32 +223,31 @@ static struct acpu_level tbl_nom[] __initdata = {
{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 825000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 850000 },
- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 875000 },
#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
#endif
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 925000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 925000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 950000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 950000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 975000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 975000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 1025000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 1025000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1050000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1050000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1075000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1075000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1125000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1125000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1150000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1150000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1175000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1175000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1187500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1187500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1200000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 925000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 925000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 950000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 950000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 975000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 975000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 1025000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 1025000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1050000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1050000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1075000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1075000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1125000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1125000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1150000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1150000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1175000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1175000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1187500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1187500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1200000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 },
@@ -257,32 +263,31 @@ static struct acpu_level tbl_fast[] __initdata = {
{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
#endif
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 975000 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 975000 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 1000000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 1000000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1025000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1025000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1075000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1075000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1100000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1100000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1125000 },
- { 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1125000 },
- { 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1137500 },
- { 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1137500 },
- { 1, { 1512000, HFPLL, 1, 0x38 }, L2(14), 1150000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 900000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 925000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 975000 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 975000 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 1000000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 1000000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1025000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1025000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1075000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1075000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1100000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1100000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(L2_BW_HIGH), 1125000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(L2_BW_HIGH), 1137500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(L2_BW_HIGH), 1137500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(L2_BW_HIGH), 1150000 },
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
@@ -298,28 +303,27 @@ static struct acpu_level tbl_faster[] __initdata = {
{ 1, { 81000, HFPLL, 2, 0x06 }, L2(0), 750000 },
{ 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 775000 },
{ 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 800000 },
- //{ 1, { 378000, HFPLL, 2, 0x1C }, L2(0), 850000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(1), 825000 },
#else
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 850000 },
#endif
- { 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 875000 },
- { 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 875000 },
- { 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 900000 },
- { 1, { 594000, HFPLL, 1, 0x16 }, L2(5), 900000 },
- { 0, { 648000, HFPLL, 1, 0x18 }, L2(5), 925000 },
- { 1, { 702000, HFPLL, 1, 0x1A }, L2(5), 925000 },
- { 0, { 756000, HFPLL, 1, 0x1C }, L2(5), 962500 },
- { 1, { 810000, HFPLL, 1, 0x1E }, L2(5), 962500 },
- { 0, { 864000, HFPLL, 1, 0x20 }, L2(5), 975000 },
- { 1, { 918000, HFPLL, 1, 0x22 }, L2(5), 975000 },
- { 0, { 972000, HFPLL, 1, 0x24 }, L2(5), 1000000 },
- { 1, { 1026000, HFPLL, 1, 0x26 }, L2(5), 1000000 },
- { 0, { 1080000, HFPLL, 1, 0x28 }, L2(14), 1050000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(14), 1050000 },
- { 0, { 1188000, HFPLL, 1, 0x2C }, L2(14), 1075000 },
- { 1, { 1242000, HFPLL, 1, 0x2E }, L2(14), 1075000 },
- { 0, { 1296000, HFPLL, 1, 0x30 }, L2(14), 1100000 },
+ { 0, { 432000, HFPLL, 2, 0x20 }, L2(L2_BW_MID), 875000 },
+ { 1, { 486000, HFPLL, 2, 0x24 }, L2(L2_BW_MID), 875000 },
+ { 0, { 540000, HFPLL, 2, 0x28 }, L2(L2_BW_MID), 900000 },
+ { 1, { 594000, HFPLL, 1, 0x16 }, L2(L2_BW_MID), 900000 },
+ { 0, { 648000, HFPLL, 1, 0x18 }, L2(L2_BW_MID), 925000 },
+ { 1, { 702000, HFPLL, 1, 0x1A }, L2(L2_BW_HIGH), 925000 },
+ { 0, { 756000, HFPLL, 1, 0x1C }, L2(L2_BW_HIGH), 962500 },
+ { 1, { 810000, HFPLL, 1, 0x1E }, L2(L2_BW_HIGH), 962500 },
+ { 0, { 864000, HFPLL, 1, 0x20 }, L2(L2_BW_HIGH), 975000 },
+ { 1, { 918000, HFPLL, 1, 0x22 }, L2(L2_BW_HIGH), 975000 },
+ { 0, { 972000, HFPLL, 1, 0x24 }, L2(L2_BW_HIGH), 1000000 },
+ { 1, { 1026000, HFPLL, 1, 0x26 }, L2(L2_BW_HIGH), 1000000 },
+ { 0, { 1080000, HFPLL, 1, 0x28 }, L2(L2_BW_HIGH), 1050000 },
+ { 1, { 1134000, HFPLL, 1, 0x2A }, L2(L2_BW_HIGH), 1050000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(L2_BW_HIGH), 1075000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(L2_BW_HIGH), 1075000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(L2_BW_HIGH), 1100000 },
{ 1, { 1350000, HFPLL, 1, 0x32 }, L2(14), 1100000 },
{ 0, { 1404000, HFPLL, 1, 0x34 }, L2(14), 1112500 },
{ 1, { 1458000, HFPLL, 1, 0x36 }, L2(14), 1112500 },

109
Patches/Overclocks/android_kernel_lge_mako/0004-Overclock.patch
View File

@ -1,109 +0,0 @@
From 8d6d2378e62e1b5236eea4f35d4405e0271cf4d5 Mon Sep 17 00:00:00 2001
From: anarkia1976 <stefano.villa1976@gmail.com>
Date: Wed, 30 Apr 2014 15:04:21 +0200
Subject: [PATCH] msm: cpu: overclock: modded for cpu ultra overclock and
normal
---
arch/arm/mach-msm/Kconfig | 7 ++++++-
arch/arm/mach-msm/acpuclock-8064.c | 16 ++++++++++++----
2 files changed, 18 insertions(+), 5 deletions(-)
diff --git a/arch/arm/mach-msm/Kconfig b/arch/arm/mach-msm/Kconfig
index 814ab1a88b4..b79e485f71f 100644
--- a/arch/arm/mach-msm/Kconfig
+++ b/arch/arm/mach-msm/Kconfig
@@ -1643,8 +1643,13 @@ config CPU_OVERCLOCK
bool "Enable CPU Overclocking option"
default n
help
- Krait overclocking up to 1.9 GHz
+ Krait overclocking up to 1.7 GHz
+config CPU_OVERCLOCK_ULTRA
+ bool "Enable CPU Overclocking option"
+ default n
+ help
+ Krait overclocking up to 1.9 GHz
config MSM_AVS_HW
bool "Enable Adaptive Voltage Scaling (AVS)"
diff --git a/arch/arm/mach-msm/acpuclock-8064.c b/arch/arm/mach-msm/acpuclock-8064.c
index 611776ed185..03974d36bba 100644
--- a/arch/arm/mach-msm/acpuclock-8064.c
+++ b/arch/arm/mach-msm/acpuclock-8064.c
@@ -47,7 +47,7 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
.vreg[VREG_CORE] = { "krait0", 1450000 },
#else
.vreg[VREG_CORE] = { "krait0", 1300000 },
@@ -62,7 +62,7 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
.vreg[VREG_CORE] = { "krait1", 1450000 },
#else
.vreg[VREG_CORE] = { "krait1", 1300000 },
@@ -77,7 +77,7 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x6501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
.vreg[VREG_CORE] = { "krait2", 1450000 },
#else
.vreg[VREG_CORE] = { "krait2", 1300000 },
@@ -92,7 +92,7 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x7501,
-#ifdef CONFIG_CPU_OVERCLOCK
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
.vreg[VREG_CORE] = { "krait3", 1450000 },
#else
.vreg[VREG_CORE] = { "krait3", 1300000 },
@@ -210,6 +210,8 @@ static struct acpu_level tbl_slow[] __initdata = {
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1300000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1350000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1400000 },
{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1425000 },
{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1450000 },
@@ -250,6 +252,8 @@ static struct acpu_level tbl_nom[] __initdata = {
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1250000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1300000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1350000 },
{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1375000 },
{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1400000 },
@@ -290,6 +294,8 @@ static struct acpu_level tbl_fast[] __initdata = {
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1200000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1250000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1300000 },
{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1325000 },
{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1350000 },
@@ -330,6 +336,8 @@ static struct acpu_level tbl_faster[] __initdata = {
#ifdef CONFIG_CPU_OVERCLOCK
{ 1, { 1620000, HFPLL, 1, 0x3C }, L2(15), 1150000 },
{ 1, { 1728000, HFPLL, 1, 0x40 }, L2(15), 1200000 },
+#endif
+#ifdef CONFIG_CPU_OVERCLOCK_ULTRA
{ 1, { 1836000, HFPLL, 1, 0x44 }, L2(15), 1250000 },
{ 1, { 1890000, HFPLL, 1, 0x45 }, L2(15), 1275000 },
{ 1, { 1944000, HFPLL, 1, 0x46 }, L2(15), 1300000 },
--
2.15.1

25
Patches/Overclocks/android_kernel_lge_mako/0005-Overclock.patch
View File

@ -1,25 +0,0 @@
From 0753d75eadea50214530dd5f3efcfa9169a5bd18 Mon Sep 17 00:00:00 2001
From: Stratos Karafotis <stratosk@semaphore.gr>
Date: Sat, 1 Jun 2013 23:59:40 +0300
Subject: [PATCH] msm: cpufreq: Break out early if target frequency is the same
as the current
Signed-off-by: Stratos Karafotis <stratosk@semaphore.gr>
---
arch/arm/mach-msm/cpufreq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-msm/cpufreq.c b/arch/arm/mach-msm/cpufreq.c
index d968075548e..ad56ed54ec7 100644
--- a/arch/arm/mach-msm/cpufreq.c
+++ b/arch/arm/mach-msm/cpufreq.c
@@ -241,6 +241,9 @@ static int msm_cpufreq_target(struct cpufreq_policy *policy,
goto done;
}
+ if (table[index].frequency == policy->cur)
+ goto done;
+
pr_debug("CPU[%d] target %d relation %d (%d-%d) selected %d\n",
policy->cpu, target_freq, relation,
policy->min, policy->max, table[index].frequency);

490
Patches/Overclocks/android_kernel_motorola_msm8916/0001-Overclock.patch
View File

@ -1,490 +0,0 @@
From 0f5855241796b323b7a71b0c2f02df15b69fbbe1 Mon Sep 17 00:00:00 2001
From: nguyenquangduc2000 <nguyenquangduc2000@gmail.com>
Date: Thu, 7 Jul 2016 15:08:14 +0700
Subject: [PATCH] Overclock 1.9Ghz/720Mhz
---
arch/arm/boot/dts/qcom/msm8916-gpu.dtsi | 114 ++++++++++++++++++------
arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi | 36 +++++++-
arch/arm/boot/dts/qcom/msm8916-regulator.dtsi | 27 +++---
arch/arm/boot/dts/qcom/msm8916.dtsi | 40 +++++++--
drivers/clk/qcom/clock-gcc-8916.c | 35 +++++---
5 files changed, 195 insertions(+), 57 deletions(-)
diff --git a/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi b/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
index 84e183f..d9269d7 100644
--- a/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916-gpu.dtsi
@@ -27,9 +27,8 @@
qcom,chipid = <0x03000600>;
- qcom,initial-pwrlevel = <1>;
-
- /* Idle Timeout */
+ qcom,initial-pwrlevel = <8>;
+ /* Idle Timeout = msec */
qcom,idle-timeout = <80>;
qcom,strtstp-sleepwake;
@@ -82,30 +81,59 @@
#size-cells = <0>;
compatible = "qcom,gpu-pwrlevels";
+ qcom,gpu-pwrlevel@0 {
+ reg = <0>;
+ qcom,gpu-freq = <720000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@0 {
- reg = <0>;
- qcom,gpu-freq = <400000000>;
- qcom,bus-freq = <3>;
- };
+ qcom,gpu-pwrlevel@1 {
+ reg = <1>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@1 {
- reg = <1>;
- qcom,gpu-freq = <310000000>;
- qcom,bus-freq = <2>;
- };
+ qcom,gpu-pwrlevel@2 {
+ reg = <2>;
+ qcom,gpu-freq = <550000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@2 {
- reg = <2>;
- qcom,gpu-freq = <200000000>;
- qcom,bus-freq = <1>;
- };
+ qcom,gpu-pwrlevel@3 {
+ reg = <3>;
+ qcom,gpu-freq = <475000000>;
+ qcom,bus-freq = <3>;
+ };
- qcom,gpu-pwrlevel@3 {
- reg = <3>;
- qcom,gpu-freq = <19200000>;
- qcom,bus-freq = <0>;
- };
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <3>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <310000000>;
+ qcom,bus-freq = <2>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <200000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <100000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@8 {
+ reg = <8>;
+ qcom,gpu-freq = <19200000>;
+ qcom,bus-freq = <0>;
+ };
};
/* Speed levels */
qcom,gpu-speed-config@2 {
@@ -129,24 +157,54 @@
qcom,gpu-pwrlevel@0 {
reg = <0>;
- qcom,gpu-freq = <465000000>;
+ qcom,gpu-freq = <720000000>;
qcom,bus-freq = <3>;
};
qcom,gpu-pwrlevel@1 {
reg = <1>;
- qcom,gpu-freq = <310000000>;
- qcom,bus-freq = <2>;
+ qcom,gpu-freq = <650000000>;
+ qcom,bus-freq = <3>;
};
qcom,gpu-pwrlevel@2 {
reg = <2>;
- qcom,gpu-freq = <200000000>;
- qcom,bus-freq = <1>;
+ qcom,gpu-freq = <550000000>;
+ qcom,bus-freq = <3>;
};
qcom,gpu-pwrlevel@3 {
reg = <3>;
+ qcom,gpu-freq = <475000000>;
+ qcom,bus-freq = <3>;
+ };
+
+ qcom,gpu-pwrlevel@4 {
+ reg = <4>;
+ qcom,gpu-freq = <400000000>;
+ qcom,bus-freq = <3>;
+ };
+
+ qcom,gpu-pwrlevel@5 {
+ reg = <5>;
+ qcom,gpu-freq = <310000000>;
+ qcom,bus-freq = <2>;
+ };
+
+ qcom,gpu-pwrlevel@6 {
+ reg = <6>;
+ qcom,gpu-freq = <200000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@7 {
+ reg = <7>;
+ qcom,gpu-freq = <100000000>;
+ qcom,bus-freq = <1>;
+ };
+
+ qcom,gpu-pwrlevel@8 {
+ reg = <8>;
qcom,gpu-freq = <19200000>;
qcom,bus-freq = <0>;
};
diff --git a/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi b/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
index 5ef1add..453531d 100644
--- a/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916-moto-common.dtsi
@@ -30,7 +30,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
CPU1: cpu@1 {
current = < 23670 //200000 kHz
@@ -41,7 +48,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
CPU2: cpu@2 {
current = < 23670 //200000 kHz
@@ -52,7 +66,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
CPU3: cpu@3 {
current = < 23670 //200000 kHz
@@ -63,7 +84,14 @@
113830 //1094400 kHz
128540 //1152000 kHz
142800 //1209600 kHz
- 157750>; //1363200 kHz
+ 145520 //1248000 kHz
+ 157750 //1363200 kHz
+ 160470 //1401600 kHz
+ 167270 //1497600 kHz
+ 174070 //1593600 kHz
+ 180870 //1689600 kHz
+ 187670 //1785600 kHz
+ 194570>; //1881600 kHz
};
};
diff --git a/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi b/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
index c456002..79de247 100644
--- a/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916-regulator.dtsi
@@ -17,8 +17,8 @@
compatible = "qcom,spm-regulator";
regulator-name = "8916_s2";
reg = <0x1700 0x100>;
- regulator-min-microvolt = <1050000>;
- regulator-max-microvolt = <1350000>;
+ regulator-min-microvolt = <1000000>;
+ regulator-max-microvolt = <1385000>;
};
};
};
@@ -48,10 +48,10 @@
regulator-name = "apc_corner";
qcom,cpr-fuse-corners = <3>;
regulator-min-microvolt = <1>;
- regulator-max-microvolt = <9>;
+ regulator-max-microvolt = <16>;
- qcom,cpr-voltage-ceiling = <1050000 1150000 1350000>;
- qcom,cpr-voltage-floor = <1050000 1050000 1162500>;
+ qcom,cpr-voltage-ceiling = <1000000 1150000 1385000>;
+ qcom,cpr-voltage-floor = <1000000 1050000 1275000>;
vdd-apc-supply = <&pm8916_s2>;
qcom,vdd-mx-corner-map = <4 5 7>;
@@ -83,9 +83,9 @@
<27 36 6 0>,
<27 18 6 0>,
<27 0 6 0>;
- qcom,cpr-init-voltage-ref = <1050000 1150000 1350000>;
+ qcom,cpr-init-voltage-ref = <1000000 1150000 1385000>;
qcom,cpr-init-voltage-step = <10000>;
- qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3>;
+ qcom,cpr-corner-map = <1 1 2 2 3 3 3 3 3 3 3 3 3 3 3 3>;
qcom,cpr-corner-frequency-map =
<1 200000000>,
<2 400000000>,
@@ -95,13 +95,20 @@
<6 1094400000>,
<7 1152000000>,
<8 1209600000>,
- <9 1363200000>;
+ <9 1248000000>,
+ <10 1363200000>,
+ <11 1401600000>,
+ <12 1497600000>,
+ <13 1593600000>,
+ <14 1689600000>,
+ <15 1785600000>,
+ <16 1881600000>;
qcom,speed-bin-fuse-sel = <1 34 3 0>;
qcom,pvs-version-fuse-sel = <0 55 2 0>;
qcom,cpr-speed-bin-max-corners =
- <0 0 2 4 8>,
+ <0 0 2 4 16>,
<0 1 2 4 7>,
- <2 0 2 4 9>;
+ <2 0 2 4 16>;
qcom,cpr-quot-adjust-scaling-factor-max = <650>;
qcom,cpr-enable;
};
diff --git a/arch/arm/boot/dts/qcom/msm8916.dtsi b/arch/arm/boot/dts/qcom/msm8916.dtsi
index 07c754a..b572220 100644
--- a/arch/arm/boot/dts/qcom/msm8916.dtsi
+++ b/arch/arm/boot/dts/qcom/msm8916.dtsi
@@ -24,7 +24,7 @@
interrupt-parent = <&intc>;
chosen {
- bootargs = "sched_enable_hmp=1";
+ bootargs = "boot_cpus=0,1,2,3 sched_enable_hmp=1";
};
aliases {
@@ -318,7 +318,15 @@
< 998400000 5>,
< 1094400000 6>,
< 1152000000 7>,
- < 1209600000 8>;
+ < 1209600000 8>,
+ < 1248000000 9>,
+ < 1363200000 10>,
+ < 1401600000 11>,
+ < 1497600000 12>,
+ < 1593600000 13>,
+ < 1689600000 14>,
+ < 1785600000 15>,
+ < 1881600000 16>;
qcom,speed1-bin-v0 =
< 0 0>,
@@ -339,7 +347,15 @@
< 998400000 5>,
< 1094400000 6>,
< 1152000000 7>,
- < 1209600000 8>;
+ < 1209600000 8>,
+ < 1248000000 9>,
+ < 1363200000 10>,
+ < 1401600000 11>,
+ < 1497600000 12>,
+ < 1593600000 13>,
+ < 1689600000 14>,
+ < 1785600000 15>,
+ < 1881600000 16>;
qcom,speed2-bin-v1 =
< 0 0>,
@@ -351,7 +367,14 @@
< 1094400000 6>,
< 1152000000 7>,
< 1209600000 8>,
- < 1363200000 9>;
+ < 1248000000 9>,
+ < 1363200000 10>,
+ < 1401600000 11>,
+ < 1497600000 12>,
+ < 1593600000 13>,
+ < 1689600000 14>,
+ < 1785600000 15>,
+ < 1881600000 16>;
};
cpubw: qcom,cpubw {
@@ -396,7 +419,14 @@
< 1094400 >,
< 1152000 >,
< 1209600 >,
- < 1363200 >;
+ < 1248000 >,
+ < 1363200 >,
+ < 1401600 >,
+ < 1497600 >,
+ < 1593600 >,
+ < 1689600 >,
+ < 1785600 >,
+ < 1881600 >;
};
qcom,sps {
diff --git a/drivers/clk/qcom/clock-gcc-8916.c b/drivers/clk/qcom/clock-gcc-8916.c
index 7ed59c1..c7e4fe94 100644
--- a/drivers/clk/qcom/clock-gcc-8916.c
+++ b/drivers/clk/qcom/clock-gcc-8916.c
@@ -348,6 +348,11 @@ static struct pll_freq_tbl apcs_pll_freq[] = {
F_APCS_PLL(1248000000, 65, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL(1363200000, 71, 0x0, 0x1, 0x0, 0x0, 0x0),
F_APCS_PLL(1401600000, 73, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1497600000, 78, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1593600000, 83, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1689600000, 88, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1785600000, 93, 0x0, 0x1, 0x0, 0x0, 0x0),
+ F_APCS_PLL(1881600000, 98, 0x0, 0x1, 0x0, 0x0, 0x0),
PLL_F_END
};
@@ -551,7 +556,10 @@ static struct clk_freq_tbl ftbl_gcc_camss_vfe0_clk[] = {
F( 266670000, gpll0, 3, 0, 0),
F( 320000000, gpll0, 2.5, 0, 0),
F( 400000000, gpll0, 2, 0, 0),
- F( 465000000, gpll2, 2, 0, 0),
+ F( 475000000, gpll2, 2, 0, 0),
+ F( 550000000, gpll2, 2, 0, 0),
+ F( 650000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -565,12 +573,12 @@ static struct rcg_clk vfe0_clk_src = {
.dbg_name = "vfe0_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 160000000, NOMINAL, 320000000, HIGH,
- 465000000),
+ 720000000),
CLK_INIT(vfe0_clk_src.c),
},
};
-static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_465_clk[] = {
+static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_720_clk[] = {
F( 19200000, xo, 1, 0, 0),
F( 50000000, gpll0_aux, 16, 0, 0),
F( 80000000, gpll0_aux, 10, 0, 0),
@@ -582,7 +590,10 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_465_clk[] = {
F( 294912000, gpll1, 3, 0, 0),
F( 310000000, gpll2, 3, 0, 0),
F( 400000000, gpll0_aux, 2, 0, 0),
- F( 465000000, gpll2, 2, 0, 0),
+ F( 475000000, gpll2, 2, 0, 0),
+ F( 550000000, gpll2, 2, 0, 0),
+ F( 650000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -598,6 +609,10 @@ static struct clk_freq_tbl ftbl_gcc_oxili_gfx3d_clk[] = {
F( 294912000, gpll1, 3, 0, 0),
F( 310000000, gpll2, 3, 0, 0),
F( 400000000, gpll0_aux, 2, 0, 0),
+ F( 475000000, gpll2, 2, 0, 0),
+ F( 550000000, gpll2, 2, 0, 0),
+ F( 650000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -610,8 +625,8 @@ static struct rcg_clk gfx3d_clk_src = {
.c = {
.dbg_name = "gfx3d_clk_src",
.ops = &clk_ops_rcg,
- VDD_DIG_FMAX_MAP3(LOW, 200000000, NOMINAL, 310000000, HIGH,
- 400000000),
+ VDD_DIG_FMAX_MAP3(LOW, 100000000, NOMINAL, 310000000, HIGH,
+ 720000000),
CLK_INIT(gfx3d_clk_src.c),
},
};
@@ -995,7 +1010,7 @@ static struct rcg_clk csi1phytimer_clk_src = {
static struct clk_freq_tbl ftbl_gcc_camss_cpp_clk[] = {
F( 160000000, gpll0, 5, 0, 0),
F( 320000000, gpll0, 2.5, 0, 0),
- F( 465000000, gpll2, 2, 0, 0),
+ F( 720000000, gpll2, 2, 0, 0),
F_END
};
@@ -1009,7 +1024,7 @@ static struct rcg_clk cpp_clk_src = {
.dbg_name = "cpp_clk_src",
.ops = &clk_ops_rcg,
VDD_DIG_FMAX_MAP3(LOW, 160000000, NOMINAL, 320000000, HIGH,
- 465000000),
+ 720000000),
CLK_INIT(cpp_clk_src.c),
},
};
@@ -2798,8 +2813,8 @@ static void gcc_gfx3d_fmax(struct platform_device *pdev)
pr_info("%s, Version: %d, bin: %d\n", __func__, version,
bin);
- gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 465000000;
- gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_465_clk;
+ gfx3d_clk_src.c.fmax[VDD_DIG_HIGH] = 720000000;
+ gfx3d_clk_src.freq_tbl = ftbl_gcc_oxili_gfx3d_720_clk;
}
static int msm_gcc_probe(struct platform_device *pdev)
--
2.9.3

1369
Patches/Overclocks/android_kernel_oppo_msm8974/0001-OverUnderClock-EXTREME.patch
View File

File diff suppressed because it is too large Load Diff

324
Patches/Overclocks/android_kernel_zte_msm8930/0001-Overclock.patch
View File

@ -1,324 +0,0 @@
From 4dba87655f582d250574f7e85c28419d54b4bf4f Mon Sep 17 00:00:00 2001
From: superr <superr@ddayweb.com>
Date: Fri, 27 Mar 2015 15:39:54 -0500
Subject: [PATCH 1/3] Add OC
---
arch/arm/mach-msm/acpuclock-8930.c | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
index 2dfb3dd..0b35c76 100644
--- a/arch/arm/mach-msm/acpuclock-8930.c
+++ b/arch/arm/mach-msm/acpuclock-8930.c
@@ -149,6 +149,8 @@ static struct l2_level l2_freq_tbl[] __initdata = {
[13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
[14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
[15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
+ [16] = { { 1242000, HFPLL, 1, 0x30 }, LVL_HIGH, 1150000, 7 },
+ [17] = { { 1296000, HFPLL, 1, 0x32 }, LVL_HIGH, 1150000, 7 },
{ }
};
@@ -169,6 +171,10 @@ static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
+ { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
+ { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1237500 },
+ { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1250000 },
+ { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1275000 },
{ 0, { 0 } }
};
@@ -189,6 +195,10 @@ static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
+ { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1200000 },
+ { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1212500 },
+ { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1225000 },
+ { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1250000 },
{ 0, { 0 } }
};
@@ -209,6 +219,10 @@ static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
+ { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1150000 },
+ { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1162500 },
+ { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1175000 },
+ { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1200000 },
{ 0, { 0 } }
};
--
1.8.3.1
From dc06c5c02d0dbe74ffeac7b4ca4fd01b2fdc3627 Mon Sep 17 00:00:00 2001
From: superr <superr@ddayweb.com>
Date: Sat, 28 Mar 2015 09:34:32 -0500
Subject: [PATCH 2/3] OC to 2GHz
---
arch/arm/mach-msm/acpuclock-8930.c | 96 ++++++++++++++++++++++++--------------
1 file changed, 62 insertions(+), 34 deletions(-)
diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
index 0b35c76..9067efc 100644
--- a/arch/arm/mach-msm/acpuclock-8930.c
+++ b/arch/arm/mach-msm/acpuclock-8930.c
@@ -123,6 +123,9 @@ static struct msm_bus_paths bw_level_tbl[] __initdata = {
[5] = BW_MBPS(3600), /* At least 450 MHz on bus. */
[6] = BW_MBPS(3936), /* At least 492 MHz on bus. */
[7] = BW_MBPS(4264), /* At least 533 MHz on bus. */
+ [8] = BW_MBPS(4532), /* At least 566 MHz on bus. */
+ [9] = BW_MBPS(4624), /* At least 578 MHz on bus. */
+ [10] = BW_MBPS(4800), /* At least 600 MHz on bus. */
};
static struct msm_bus_scale_pdata bus_scale_data __initdata = {
@@ -133,24 +136,25 @@ static struct msm_bus_scale_pdata bus_scale_data __initdata = {
};
static struct l2_level l2_freq_tbl[] __initdata = {
- [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 },
- [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 },
- [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 },
- [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 },
- [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 },
- [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 },
- [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 },
- [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 },
- [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 },
- [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 },
- [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 },
- [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 },
- [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 },
- [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 },
- [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 },
- [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 },
- [16] = { { 1242000, HFPLL, 1, 0x30 }, LVL_HIGH, 1150000, 7 },
- [17] = { { 1296000, HFPLL, 1, 0x32 }, LVL_HIGH, 1150000, 7 },
+ [0] = { { 384000, PLL_8, 0, 0x00 }, LVL_LOW, 1050000, 1 }, //133mhz fsb
+ [1] = { { 432000, HFPLL, 2, 0x20 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
+ [2] = { { 486000, HFPLL, 2, 0x24 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
+ [3] = { { 540000, HFPLL, 2, 0x28 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
+ [4] = { { 594000, HFPLL, 1, 0x16 }, LVL_NOM, 1050000, 2 }, //266mhz fsb
+ [5] = { { 648000, HFPLL, 1, 0x18 }, LVL_NOM, 1050000, 4 }, //400mhz fsb
+ [6] = { { 702000, HFPLL, 1, 0x1A }, LVL_NOM, 1050000, 4 }, //400mhz fsb
+ [7] = { { 756000, HFPLL, 1, 0x1C }, LVL_HIGH, 1150000, 4 }, //400mhz fsb
+ [8] = { { 810000, HFPLL, 1, 0x1E }, LVL_HIGH, 1150000, 4 }, //400mhz fsb
+ [9] = { { 864000, HFPLL, 1, 0x20 }, LVL_HIGH, 1150000, 4 }, //400mhz fsb
+ [10] = { { 918000, HFPLL, 1, 0x22 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
+ [11] = { { 972000, HFPLL, 1, 0x24 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
+ [12] = { { 1026000, HFPLL, 1, 0x26 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
+ [13] = { { 1080000, HFPLL, 1, 0x28 }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
+ [14] = { { 1134000, HFPLL, 1, 0x2A }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
+ [15] = { { 1188000, HFPLL, 1, 0x2C }, LVL_HIGH, 1150000, 7 }, //533mhz fsb
+ [16] = { { 1242000, HFPLL, 1, 0x2E }, LVL_HIGH, 1150000, 7 },
+ [17] = { { 1296000, HFPLL, 1, 0x30 }, LVL_HIGH, 1150000, 7 },
+ [18] = { { 1350000, HFPLL, 1, 0x32 }, LVL_HIGH, 1150000, 10 }, //600mhz fsb
{ }
};
@@ -171,14 +175,13 @@ static struct acpu_level acpu_freq_tbl_slow[] __initdata = {
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1175000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1175000 },
{ 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1200000 },
- { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1225000 },
- { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1237500 },
- { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1250000 },
- { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1275000 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 875000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 900000 },
+ { 0, { 378000, HFPLL, 2, 0x1C }, L2(0), 925000 },
{ 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 925000 },
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 950000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 950000 },
@@ -193,17 +196,31 @@ static struct acpu_level acpu_freq_tbl_nom[] __initdata = {
{ 0, { 972000, HFPLL, 1, 0x24 }, L2(10), 1100000 },
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1100000 },
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1150000 },
- { 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1175000 },
- { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1200000 },
- { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1212500 },
- { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1225000 },
- { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1250000 },
+ { 0, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1150000 },
+ { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1150000 },
+ { 1, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1150000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1175000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1175000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1187500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1187500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1200000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(18), 1225000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(18), 1237500 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(18), 1250000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(18), 1267500 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(18), 1275000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(18), 1300000 },
+ { 1, { 1944000, HFPLL, 1, 0x48 }, L2(18), 1312500 },
+ { 1, { 1998000, HFPLL, 1, 0x4A }, L2(18), 1325000 },
+ { 1, { 2052000, HFPLL, 1, 0x4C }, L2(18), 1337500 },
{ 0, { 0 } }
};
static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
- { 1, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
+ { 1, { 162000, HFPLL, 2, 0x0C }, L2(0), 850000 },
+ { 1, { 270000, HFPLL, 2, 0x14 }, L2(0), 875000 },
+ { 0, { 378000, HFPLL, 2, 0x1C }, L2(0), 900000 },
+ { 0, { 384000, PLL_8, 0, 0x00 }, L2(0), 900000 },
{ 0, { 432000, HFPLL, 2, 0x20 }, L2(5), 900000 },
{ 1, { 486000, HFPLL, 2, 0x24 }, L2(5), 900000 },
{ 0, { 540000, HFPLL, 2, 0x28 }, L2(5), 925000 },
@@ -218,11 +235,22 @@ static struct acpu_level acpu_freq_tbl_fast[] __initdata = {
{ 1, { 1026000, HFPLL, 1, 0x26 }, L2(10), 1050000 },
{ 0, { 1080000, HFPLL, 1, 0x28 }, L2(15), 1100000 },
{ 1, { 1134000, HFPLL, 1, 0x2A }, L2(15), 1100000 },
- { 1, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
- { 1, { 1300000, HFPLL, 1, 0x30 }, L2(15), 1150000 },
- { 1, { 1400000, HFPLL, 1, 0x32 }, L2(15), 1162500 },
- { 1, { 1500000, HFPLL, 1, 0x34 }, L2(15), 1175000 },
- { 1, { 1600000, HFPLL, 1, 0x36 }, L2(15), 1200000 },
+ { 0, { 1188000, HFPLL, 1, 0x2C }, L2(15), 1125000 },
+ { 0, { 1242000, HFPLL, 1, 0x2E }, L2(18), 1125000 },
+ { 0, { 1296000, HFPLL, 1, 0x30 }, L2(18), 1125000 },
+ { 1, { 1350000, HFPLL, 1, 0x32 }, L2(18), 1125000 },
+ { 0, { 1404000, HFPLL, 1, 0x34 }, L2(18), 1137500 },
+ { 1, { 1458000, HFPLL, 1, 0x36 }, L2(18), 1137500 },
+ { 1, { 1512000, HFPLL, 1, 0x38 }, L2(18), 1150000 },
+ { 1, { 1566000, HFPLL, 1, 0x3A }, L2(18), 1175000 },
+ { 1, { 1620000, HFPLL, 1, 0x3C }, L2(18), 1190000 },
+ { 1, { 1674000, HFPLL, 1, 0x3E }, L2(18), 1200000 },
+ { 1, { 1728000, HFPLL, 1, 0x40 }, L2(18), 1225000 },
+ { 1, { 1836000, HFPLL, 1, 0x44 }, L2(18), 1250000 },
+ { 1, { 1890000, HFPLL, 1, 0x46 }, L2(18), 1275000 },
+ { 1, { 1944000, HFPLL, 1, 0x48 }, L2(18), 1312500 },
+ { 1, { 1998000, HFPLL, 1, 0x4A }, L2(18), 1325000 },
+ { 1, { 2052000, HFPLL, 1, 0x4C }, L2(18), 1337500 },
{ 0, { 0 } }
};
--
1.8.3.1
From d11c45b7a335452b8144c5e125d8a10b07f8feb6 Mon Sep 17 00:00:00 2001
From: Tad <tad@spotco.us>
Date: Sun, 11 Dec 2016 20:41:35 -0500
Subject: [PATCH 3/3] Max OC
Change-Id: I6e2089eb1f8de9200964acd6271649f6af70edfd
---
arch/arm/mach-msm/acpuclock-8930.c | 9 +++++----
arch/arm/mach-msm/acpuclock-krait.c | 2 +-
arch/arm/mach-msm/board-8930-regulator-pm8038.c | 4 ++--
arch/arm/mach-msm/board-8930-regulator-pm8917.c | 4 ++--
4 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/arch/arm/mach-msm/acpuclock-8930.c b/arch/arm/mach-msm/acpuclock-8930.c
index 9067efc..693a254 100644
--- a/arch/arm/mach-msm/acpuclock-8930.c
+++ b/arch/arm/mach-msm/acpuclock-8930.c
@@ -52,7 +52,7 @@ static struct scalable scalable_pm8917[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_CORE] = { "krait0", 1400000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_s8", 2050000 },
@@ -64,7 +64,7 @@ static struct scalable scalable_pm8917[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_CORE] = { "krait1", 1400000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_s8", 2050000 },
@@ -88,7 +88,7 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x4501,
- .vreg[VREG_CORE] = { "krait0", 1300000 },
+ .vreg[VREG_CORE] = { "krait0", 1400000 },
.vreg[VREG_MEM] = { "krait0_mem", 1150000 },
.vreg[VREG_DIG] = { "krait0_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait0_hfpll", 1800000 },
@@ -99,7 +99,7 @@ static struct scalable scalable[] __initdata = {
.aux_clk_sel = 3,
.sec_clk_sel = 2,
.l2cpmr_iaddr = 0x5501,
- .vreg[VREG_CORE] = { "krait1", 1300000 },
+ .vreg[VREG_CORE] = { "krait1", 1400000 },
.vreg[VREG_MEM] = { "krait1_mem", 1150000 },
.vreg[VREG_DIG] = { "krait1_dig", 1150000 },
.vreg[VREG_HFPLL_A] = { "krait1_hfpll", 1800000 },
@@ -126,6 +126,7 @@ static struct msm_bus_paths bw_level_tbl[] __initdata = {
[8] = BW_MBPS(4532), /* At least 566 MHz on bus. */
[9] = BW_MBPS(4624), /* At least 578 MHz on bus. */
[10] = BW_MBPS(4800), /* At least 600 MHz on bus. */
+ [11] = BW_MBPS(5336), /* At least 667 MHz on bus. */
};
static struct msm_bus_scale_pdata bus_scale_data __initdata = {
diff --git a/arch/arm/mach-msm/acpuclock-krait.c b/arch/arm/mach-msm/acpuclock-krait.c
index f216ee5..cfbf338 100755
--- a/arch/arm/mach-msm/acpuclock-krait.c
+++ b/arch/arm/mach-msm/acpuclock-krait.c
@@ -932,7 +932,7 @@ static void __init bus_init(const struct l2_level *l2_level)
}
#ifdef CONFIG_CPU_FREQ_MSM
-static struct cpufreq_frequency_table freq_table[NR_CPUS][35];
+static struct cpufreq_frequency_table freq_table[NR_CPUS][53];
static void __init cpufreq_table_init(void)
{
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8038.c b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
index 4cf0f54..b5a6602 100755
--- a/arch/arm/mach-msm/board-8930-regulator-pm8038.c
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8038.c
@@ -541,9 +541,9 @@ msm8930_pm8038_gpio_regulator_pdata[] __devinitdata = {
/* SAW regulator constraints */
struct regulator_init_data msm8930_pm8038_saw_regulator_core0_pdata =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(S5, "8038_s5", 850000, 1300000);
+ SAW_VREG_INIT(S5, "8038_s5", 850000, 1400000);
struct regulator_init_data msm8930_pm8038_saw_regulator_core1_pdata =
- SAW_VREG_INIT(S6, "8038_s6", 850000, 1300000);
+ SAW_VREG_INIT(S6, "8038_s6", 850000, 1400000);
/* PM8038 regulator constraints */
struct pm8xxx_regulator_platform_data
diff --git a/arch/arm/mach-msm/board-8930-regulator-pm8917.c b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
index b0dedad..ce3a17f 100644
--- a/arch/arm/mach-msm/board-8930-regulator-pm8917.c
+++ b/arch/arm/mach-msm/board-8930-regulator-pm8917.c
@@ -501,9 +501,9 @@ msm8930_pm8917_gpio_regulator_pdata[] __devinitdata = {
/* SAW regulator constraints */
struct regulator_init_data msm8930_pm8917_saw_regulator_core0_pdata =
/* ID vreg_name min_uV max_uV */
- SAW_VREG_INIT(S5, "8917_s5", 850000, 1300000);
+ SAW_VREG_INIT(S5, "8917_s5", 850000, 1400000);
struct regulator_init_data msm8930_pm8917_saw_regulator_core1_pdata =
- SAW_VREG_INIT(S6, "8917_s6", 850000, 1300000);
+ SAW_VREG_INIT(S6, "8917_s6", 850000, 1400000);
/* PM8917 regulator constraints */
struct pm8xxx_regulator_platform_data
--
1.8.3.1

88
Scripts/Common/Overclock.sh
View File

@ -1,88 +0,0 @@
#!/bin/bash
#DivestOS: A privacy focused mobile distribution
#Copyright (c) 2017-2018 Divested Computing Group
#
#This program is free software: you can redistribute it and/or modify
#it under the terms of the GNU General Public License as published by
#the Free Software Foundation, either version 3 of the License, or
#(at your option) any later version.
#
#This program is distributed in the hope that it will be useful,
#but WITHOUT ANY WARRANTY; without even the implied warranty of
#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
#GNU General Public License for more details.
#
#You should have received a copy of the GNU General Public License
#along with this program. If not, see <https://www.gnu.org/licenses/>.
#Overclocks the CPU to increase performance
#Last verified: 2018-04-27
echo "Applying overclocks...";
if enter "kernel/amazon/hdx-common"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_amazon_hdx-common/0001-Overclock.patch"; #300MHz -> 268MHz, 2.26GHz -> 2.41GHz
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_amazon_hdx-common/0002-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_amazon_hdx-common/0003-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_amazon_hdx-common/0004-Overclock.patch";
fi;
if enter "kernel/asus/grouper-DISABLED"; then #XXX: Disabled
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_asus_grouper/0001-Overclock.patch";
echo "CONFIG_TEGRA_CPU_OVERCLOCK=y" >> arch/arm/configs/grouper_defconfig; #1.30GHz -> 1.50GHz
echo "CONFIG_TEGRA_CPU_OVERCLOCK_ULTIMATE=y" >> arch/arm/configs/grouper_defconfig; #1.30GHz -> 1.60GHz
echo "CONFIG_TEGRA_GPU_OVERCLOCK=y" >> arch/arm/configs/grouper_defconfig; #416MHz -> 520MHz
echo "CONFIG_TEGRA_GAMING_FIX=y" >> arch/arm/configs/grouper_defconfig;
fi;
if enter "kernel/huawei/angler"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_huawei_angler/0001-Overclock.patch";
fi;
if enter "kernel/lge/g3"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_g3/0001-Overclock.patch"; #2.45GHz -> 2.76GHz
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_g3/0002-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_g3/0003-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_g3/0004-Overclock.patch";
fi;
if enter "kernel/lge/hammerhead"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_hammerhead/0001-Overclock.patch"; #2.26GHz -> 2.95GHz
fi;
if enter "kernel/lge/mako"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_mako/0001-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_mako/0002-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_mako/0003-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_mako/0004-Overclock.patch";
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_lge_mako/0005-Overclock.patch";
echo "CONFIG_LOW_CPUCLOCKS=y" >> arch/arm/configs/lineageos_mako_defconfig; #384MHz -> 81MHz
echo "CONFIG_CPU_OVERCLOCK=y" >> arch/arm/configs/lineageos_mako_defconfig; #1.51GHz -> 1.70GHz
#echo "CONFIG_CPU_OVERCLOCK_ULTRA=y" >> arch/arm/configs/lineageos_mako_defconfig; #1.51GHz -> 1.94GHz XXX: Throttles
if enter "device/lge/mako"; then
sed -i 's/scaling_min_freq 384000/scaling_min_freq 81000/' rootdir/etc/init.mako.power.rc;
#sed -i 's/scaling_max_freq 1512000/scaling_max_freq 1728000/' rootdir/etc/init.mako.power.rc;
#sed -i 's/NORMAL_FREQ "1512000"/NORMAL_FREQ "1728000"/' power/power_mako.c;
#sed -i 's/scaling_max_freq 1512000/scaling_max_freq 1944000/' rootdir/etc/init.mako.power.rc;
#sed -i 's/NORMAL_FREQ "1512000"/NORMAL_FREQ "1944000"/' power/power_mako.c;
fi;
fi;
if enter "kernel/motorola/msm8916"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_motorola_msm8916/0001-Overclock.patch"; #1.36GHz -> 1.88GHz
fi;
if enter "kernel/oneplus/msm8974"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_oppo_msm8974/0001-OverUnderClock-EXTREME.patch"; #300MHz -> 268MHz, 2.45GHz -> 2.95GHz
fi;
if enter "kernel/oppo/msm8974"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_oppo_msm8974/0001-OverUnderClock-EXTREME.patch"; #300MHz -> 268MHz, 2.45GHz -> 2.95GHz
fi;
if enter "kernel/zte/msm8930-DISABLED"; then
patch -p1 < "$DOS_PATCHES_OVERCLOCKS/android_kernel_zte_msm8930/0001-Overclock.patch";
fi;
cd "$DOS_BUILD_BASE";
echo "Overclocks applied!";

1
Scripts/LineageOS-11.0/Functions.sh
View File

@ -65,7 +65,6 @@ patchWorkspace() {
source "$DOS_SCRIPTS/Patch.sh";
source "$DOS_SCRIPTS/Defaults.sh";
source "$DOS_SCRIPTS/Rebrand.sh";
if [ "$DOS_OVERCLOCKS_ENABLED" = true ]; then source "$DOS_SCRIPTS_COMMON/Overclock.sh"; fi;
source "$DOS_SCRIPTS_COMMON/Optimize.sh";
source "$DOS_SCRIPTS_COMMON/Deblob.sh";
source "$DOS_SCRIPTS_COMMON/Patch_CVE.sh";

1
Scripts/LineageOS-14.1/Functions.sh
View File

@ -104,7 +104,6 @@ patchWorkspace() {
source "$DOS_SCRIPTS/Defaults.sh";
source "$DOS_SCRIPTS/Rebrand.sh";
source "$DOS_SCRIPTS/Theme.sh";
if [ "$DOS_OVERCLOCKS_ENABLED" = true ]; then source "$DOS_SCRIPTS_COMMON/Overclock.sh"; fi;
source "$DOS_SCRIPTS_COMMON/Optimize.sh";
source "$DOS_SCRIPTS_COMMON/Deblob.sh";
source "$DOS_SCRIPTS_COMMON/Patch_CVE.sh";

1
Scripts/LineageOS-15.1/Functions.sh
View File

@ -97,7 +97,6 @@ patchWorkspace() {
source "$DOS_SCRIPTS_COMMON/Copy_Keys.sh";
source "$DOS_SCRIPTS/Defaults.sh";
source "$DOS_SCRIPTS/Rebrand.sh";
if [ "$DOS_OVERCLOCKS_ENABLED" = true ]; then source "$DOS_SCRIPTS_COMMON/Overclock.sh"; fi;
source "$DOS_SCRIPTS_COMMON/Optimize.sh";
source "$DOS_SCRIPTS_COMMON/Deblob.sh";
source "$DOS_SCRIPTS_COMMON/Patch_CVE.sh";

1
Scripts/LineageOS-16.0/Functions.sh
View File

@ -91,7 +91,6 @@ patchWorkspace() {
source "$DOS_SCRIPTS_COMMON/Copy_Keys.sh";
source "$DOS_SCRIPTS/Defaults.sh";
source "$DOS_SCRIPTS/Rebrand.sh";
if [ "$DOS_OVERCLOCKS_ENABLED" = true ]; then source "$DOS_SCRIPTS_COMMON/Overclock.sh"; fi;
source "$DOS_SCRIPTS_COMMON/Optimize.sh";
source "$DOS_SCRIPTS_COMMON/Deblob.sh";
source "$DOS_SCRIPTS_COMMON/Patch_CVE.sh";

1
Scripts/LineageOS-17.1/Functions.sh
View File

@ -139,7 +139,6 @@ patchWorkspace() {
source "$DOS_SCRIPTS_COMMON/Copy_Keys.sh";
source "$DOS_SCRIPTS/Defaults.sh";
source "$DOS_SCRIPTS/Rebrand.sh";
if [ "$DOS_OVERCLOCKS_ENABLED" = true ]; then source "$DOS_SCRIPTS_COMMON/Overclock.sh"; fi;
source "$DOS_SCRIPTS_COMMON/Optimize.sh";
source "$DOS_SCRIPTS_COMMON/Deblob.sh";
source "$DOS_SCRIPTS_COMMON/Patch_CVE.sh";

2
Scripts/init.sh
View File

@ -60,7 +60,6 @@ export DOS_LOWRAM_ENABLED=false; #Set true to enable low_ram on all devices
export DOS_MICROG_INCLUDED="NLP"; #Determines inclusion of microG. Options: NLP, FULL
export DOS_NON_COMMERCIAL_USE_PATCHES=false; #Set true to allow inclusion of non-commercial use patches XXX: Unused, see 1dc9247
export DOS_OPTIMIZE_IMAGES=false; #Set true to apply lossless optimizations to image resources
export DOS_OVERCLOCKS_ENABLED=false; #Set true to enable overclocks #XXX: Most devices have their processors directly under their RAM, heatsinking is mostly into the ground plane, potentially inflicting damage to RAM and the processor itself
export DOS_STRONG_ENCRYPTION_ENABLED=false; #Set true to enable AES 256-bit FDE encryption on 14.1+15.1 XXX: THIS WILL **DESTROY** EXISTING INSTALLS!
#Servers
@ -139,7 +138,6 @@ export DOS_HOSTS_FILE="$DOS_TMP_DIR/hosts";
export DOS_PREBUILT_APPS=$DOS_WORKSPACE_ROOT"PrebuiltApps/";
export DOS_PATCHES_COMMON=$DOS_WORKSPACE_ROOT"Patches/Common/";
export DOS_PATCHES=$DOS_WORKSPACE_ROOT"Patches/$BUILD_WORKING_DIR/";
export DOS_PATCHES_OVERCLOCKS=$DOS_WORKSPACE_ROOT"Patches/Overclocks/";
export DOS_PATCHES_LINUX_CVES=$DOS_WORKSPACE_ROOT"Patches/Linux/";
export DOS_WALLPAPERS=$DOS_WORKSPACE_ROOT"Patches/Wallpapers/";

3
TODO
View File

@ -21,9 +21,6 @@ Medium Priority
- Update cryptocurrency addresses
Low Priority
Build
- Add more device overclocks
- Move overclocks to separate repo
Website
- Switch to a wiki (?)
WiFiDatabaseMerger

1
fix_permissions.sh
View File

@ -29,7 +29,6 @@ setStrict Patches/LineageOS-16.0;
setStrict Patches/LineageOS-17.1;
setStrict Patches/Linux; #XXX: move this into the repo
chmod -v 700 Patches/Linux/*.sh;
setStrict Patches/Overclocks;
#PrebuiltApps has its own fix_permissions.sh
#Patches/Wallpapers has its own fix_permissions.sh
setStrict Scripts;